CN216979623U - ARM core board with EtherCAT protocol interface - Google Patents
ARM core board with EtherCAT protocol interface Download PDFInfo
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Abstract
The utility model relates to an ARM core board with an EtherCAT protocol interface, which is applied to an industrial equipment control system and comprises a data acquisition interface, a master control chip, a static memory and a slave controller; the master control chip is connected with the data acquisition interface, the slave station controller and the static memory. The data acquisition interface acquires real-time monitoring data and sends the real-time monitoring data to the main control chip; the main control chip receives the real-time monitoring data, sends real-time analysis data to the slave station controller, receives an operation instruction of the slave station controller, sends a control signal to the slave station controller, and writes or reads the stored data in the static memory; the slave station controller sends real-time analysis data to the master station industrial equipment, receives an operation instruction sent by the master station industrial equipment, receives a control signal of the master control chip and sends the control signal to the slave station industrial equipment; the static memory stores the stored data. The industrial data transmission delay can be reduced, and the communication reliability is improved.
Description
Technical Field
The utility model relates to the technical field of embedded core boards, in particular to an ARM core board with an EtherCAT protocol interface.
Background
At present, the embedded technology plays an increasingly important role in the fields of communication, network, industrial control, medical treatment, electronics and the like. The ARM core board has rich functions and ultrahigh cost performance, is suitable for learning and research of numerous embedded developers, and is widely applied to industries such as industrial control, communication, Internet of things, Internet of vehicles and the like.
However, the conventional ARM core board has a single function, and cannot provide corresponding functions according to actual use requirements. When the industrial control system is applied to an industrial control scene, due to the fact that an EtherCAT protocol is not compatible, relevant processing of protocol compatibility is needed when an ARM core board is integrated into an industrial control product, the real-time performance and the reliability of communication among industrial devices are not high, and the ARM core board does not exert the advantages of the ARM core board in the field of industrial control.
Therefore, an ARM core board with an EtherCAT protocol interface needs to be designed, so that the complexity of the application of the ARM core board in industrial control is reduced, and the real-time performance and reliability of data interaction of industrial equipment are improved.
SUMMERY OF THE UTILITY MODEL
In view of this, it is necessary to provide an ARM core board with an EtherCAT protocol interface to solve the problems of high integration difficulty and low communication efficiency of the ARM core board in the industrial control in the prior art.
In order to achieve the technical purpose, the utility model adopts the following technical scheme:
the utility model provides an ARM core board with an EtherCAT protocol interface, which is applied to an industrial equipment control system and comprises the following components: the system comprises a data acquisition interface, a master control chip, a static memory and a slave station controller; the master control chip is connected with the data acquisition interface, the slave station controller and the static memory;
the data acquisition interface is used for acquiring real-time monitoring data and sending the real-time monitoring data to the main control chip;
the master control chip is used for receiving the real-time monitoring data sent by the data acquisition interface, sending real-time analysis data to the slave station controller according to the real-time monitoring data, receiving an operation instruction returned by the slave station controller, sending a control signal to the slave station controller according to the operation instruction, and writing or reading storage data in the static memory;
the slave station controller is used for receiving the real-time analysis data sent by the master control chip, sending the real-time analysis data to the master station industrial equipment, receiving the operation instruction sent by the master station industrial equipment, sending the operation instruction to the master control chip, receiving the control signal sent by the master control chip and sending the control signal to the slave station industrial equipment;
and the static memory is used for storing the storage data.
Further, the static memory further comprises an address decoder, wherein the address decoder is connected with the main control chip and the static memory;
the address decoder is used for receiving the address information sent by the main control chip, decoding the address information to obtain storage unit information, sending the storage unit information to the main control chip, and performing enable control on the static memory;
the main control chip is further configured to send address information to the address decoder, receive storage unit information sent by the address decoder, and write or read storage data in the static memory according to the storage unit information.
Further, the slave station controller includes a plurality of ethernet ports and a plurality of PHY chips.
Further, the slave station controller includes an HBI interface.
Further, the data acquisition interface comprises a temperature and humidity sensor and a digital-to-analog conversion circuit.
Further, the device also comprises a downloading circuit; the download circuit is connected with the main control chip;
the download circuit is used for updating the control program of the main control chip.
Further, the circuit also comprises a reset circuit; the reset circuit is connected with the main control chip;
the reset circuit is used for restarting the main control chip.
Further, the device also comprises a state indicating circuit; the state indicating circuit is connected with the main control chip;
the state indicating circuit is used for displaying the working state of the main control chip.
Further, the main control chip comprises an FSMC interface.
Further, the main control chip comprises a hash processing module.
Compared with the prior art, the utility model has the beneficial effects that: acquiring real-time monitoring data of an equipment operating environment through a data acquisition interface, analyzing the real-time monitoring data through the main control chip to obtain real-time analysis data, and sending the real-time analysis data to the slave station controller; the slave station controller sends real-time analysis data to the master station industrial equipment, receives an operation instruction sent by the master station industrial equipment and sends the operation instruction to the master control chip; and the master control chip sends a control signal to the slave station controller after receiving the operation instruction, and the slave station controller sends the control signal to the slave station industrial equipment. According to the utility model, the master station industrial equipment can rapidly acquire the change of the running state of the equipment through the master control chip and the slave station controller, control information is sent to the slave station industrial equipment in time, the running mode of the slave station industrial equipment is adjusted, and the condition of abnormal running of the equipment is avoided; the transmission delay of the communication between the master station industrial equipment and the slave station industrial equipment is greatly reduced, the full duplex characteristic of EtherCAT is fully utilized, the real-time performance of the communication is improved, the communication stability, the communication reliability and the effective data utilization rate are also obviously improved, and the complexity of the ARM core board in industrial control is reduced. The static memory is used for storing the data, so that a data base is provided for subsequent data analysis and industrial equipment management optimization, and historical data can be prevented from being deleted by mistake when a system fails.
Drawings
Fig. 1 is a structural framework diagram of an embodiment of an ARM core board with an EtherCAT protocol interface according to the present invention;
fig. 2 is a structural framework diagram of another embodiment of an ARM core board with an EtherCAT protocol interface according to the present invention;
FIG. 3 is a circuit diagram of one embodiment of a slave station controller provided by the present invention;
FIG. 4 is a circuit diagram of an embodiment of a static memory according to the present invention;
fig. 5 is a circuit diagram of an address decoder according to an embodiment of the present invention.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the utility model and together with the description, serve to explain the principles of the utility model and not to limit the scope of the utility model.
In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the utility model. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The present invention provides an ARM core board with an EtherCAT protocol interface, please refer to fig. 1, where fig. 1 is a structural framework diagram of the ARM core board with the EtherCAT protocol interface provided in this embodiment, and includes: a data acquisition interface 101, a master control chip 102, a static memory 104 and a slave station controller 103; the master control chip 102 is connected to the data acquisition interface 101, the slave station controller 103 and the static memory 104.
The data acquisition interface 101 is configured to acquire real-time monitoring data and send the real-time monitoring data to the main control chip 102;
the master control chip 102 is configured to receive real-time monitoring data sent by the data acquisition interface 101, send real-time analysis data to the slave station controller 103 according to the real-time monitoring data, receive an operation instruction returned by the slave station controller 103, send a control signal to the slave station controller 103 according to the operation instruction, and write or read storage data in the static memory 104;
the slave station controller 103 is configured to receive the real-time analysis data sent by the master control chip 102, send the real-time analysis data to a master station industrial device, receive an operation instruction sent by the master station industrial device, send the operation instruction to the master control chip 102, receive a control signal sent by the master control chip 102, and send the control signal to a slave station industrial device;
the static memory 104 is used for storing the storage data.
According to the ARM core board with the EtherCAT protocol interface, provided by the embodiment of the utility model, real-time monitoring data of an equipment operation environment are obtained through a data acquisition interface, the real-time monitoring data are analyzed through the main control chip to obtain real-time analysis data, and the real-time analysis data are sent to the slave station controller; the slave station controller sends real-time analysis data to the master station industrial equipment, receives an operation instruction sent by the master station industrial equipment and sends the operation instruction to the master control chip; and the master control chip sends a control signal to the slave station controller after receiving the operation instruction, and the slave station controller sends the control signal to the slave station industrial equipment. According to the utility model, the master station industrial equipment can rapidly acquire the change of the running state of the equipment through the master control chip and the slave station controller, control information is sent to the slave station industrial equipment in time, the running mode of the slave station industrial equipment is adjusted, and the condition of abnormal running of the equipment is avoided; the transmission delay existing in the communication between the master station industrial equipment and the slave station industrial equipment is greatly reduced, the EtherCAT full duplex characteristic is fully utilized, the communication real-time performance is improved, the communication stability, the communication reliability and the effective data utilization rate are also obviously improved, and the complexity of the ARM core board in the industrial control is reduced. The data are stored through the static memory, a data base is provided for subsequent data analysis and industrial equipment management optimization, and historical data are prevented from being deleted by mistake when a system fails.
In order to fully utilize the storage space of the static memory and improve the data read-write speed, as shown in fig. 2, as a preferred embodiment, the static memory further includes an address decoder 105, and the address decoder 105 is connected to the main control chip 102 and the static memory 104;
the address decoder 105 is configured to receive address information sent by the main control chip 102, decode the address information to obtain storage unit information, send the storage unit information to the main control chip 102, and enable and control the static memory 104;
the main control chip 102 is further configured to send address information to the address decoder 105, receive storage unit information sent by the address decoder 105, and write or read storage data in the static memory 104 according to the storage unit information.
The master control chip mainly completes the application layer function in the EtherCAT communication, and the slave station controller mainly realizes the data link layer function in the EtherCAT communication mode and is responsible for processing the protocol between the master station industrial equipment and the slave station industrial equipment. As a preferred embodiment, the slave station controller includes a plurality of ethernet ports and a plurality of PHY chips; various topological structures such as linear connection, star connection, tree connection and the like of industrial equipment can be realized through a plurality of Ethernet ports; the plurality of PHY chips can configure the transmission mode, thereby providing great convenience for the function development of developers.
As a preferred embodiment, the slave station controller comprises an HBI interface. High-speed communication of data can be realized through the HBI interface.
As a preferred embodiment, the data acquisition interface includes a temperature and humidity sensor and a digital-to-analog conversion circuit. The temperature and the humidity of the industrial equipment can be monitored in real time through the temperature and humidity sensor, and the running state of the industrial equipment is judged according to a preset temperature and humidity threshold value. Through a digital-to-analog conversion circuit, analog signals sent by the external equipment connected with the data acquisition interface can be converted into digital signals, and basic monitoring data are provided for industrial equipment system control.
As a preferred embodiment, also include the download circuit; the download circuit is connected with the main control chip;
the download circuit is used for updating the control program of the main control chip.
According to different industrial equipment operation requirements, the control program of the main control chip is updated, and the actual requirements of the industrial equipment control system are met.
As a preferred embodiment, the device further comprises a reset circuit; the reset circuit is connected with the main control chip;
the reset circuit is used for restarting the main control chip.
Restart when master control chip breaks down through reset circuit, ensure the stability of ARM nuclear core plate operation.
As a preferred embodiment, further comprises a status indication circuit; the state indicating circuit is connected with the main control chip;
the state indicating circuit is used for displaying the working state of the main control chip.
As a preferred embodiment, the master control chip includes an FSMC interface. The communication with the slave station controller is carried out through the FSMC interface, so that the compatibility of slave station controllers of different models is realized, and the data communication efficiency is higher.
As a specific embodiment, the ARM core board with the EtherCAT protocol interface is powered by a 5V dc power supply, can be conveniently integrated into products such as industrial control, and is suitable for embedded learning, prototype development and control modules of intelligent systems.
The above technical solution is explained in detail with reference to fig. 3 to 5.
The model of main control chip is STM32F407IGT6, main control chip includes 32 bit zone FPU floating point Cortex-M4 kernels, has the advantage that the performance is high, the real-time is good and the low power dissipation. The main control chip is provided with an internal FLASH of 1MB and a parallel bus FSMC, wherein the FLASH has 1 ten thousand erasing and writing life; the parallel bus FSMC supports CF, SRAM, PSRAM, NOR and NAND memory LCD parallel ports, 8080/6800, etc. modes. By adopting the STM32F407IGT6 as a main control chip, the data processing precision and efficiency in industrial control can be met, and the real-time performance of industrial data communication is improved.
As shown in fig. 3, the slave station controller has a model of LAN9252, and fig. 3 is a circuit configuration diagram of the slave station controller. Two PHY chips are integrated in the LAN9252, and the LAN can be configured to be a full-double 100Mbps copper cable (100BASE-TX) or a 100Mbps optical fiber (100BASE-FX) transmission mode. The LAN9252 has the advantages of low pin count and small package size, and contains two ethernet PHYs, which is greatly convenient for developers to develop. LAN9252 has 4KB of DPRAM, 3 fieldbus memory management interfaces FMMU, and 4 SM channel managers. In addition, the LAN9252 supports the HP Auto-MDIX function, has 3 ethernet ports, and can implement various topologies such as linear connection, star connection, and tree connection.
The main control chip STM32F407IGT6 performs data interaction with the HBI interface of the slave station controller LAN9252 through the FSMC interface, and the real-time performance and the reliability of communication are ensured.
As shown in fig. 4, fig. 4 IS a circuit structure diagram of the static memory, and the model of the static memory IS61WV102416 BLL. The static memory is used for storing the data, so that a data base is provided for subsequent data analysis and industrial equipment management optimization, and historical data can be prevented from being deleted by mistake when a system fails.
As shown in fig. 5, fig. 5 is a circuit structure diagram of the address decoder, and the address decoder implements an address and data multiplexing addressing mode of 16-bit single-stage latch, and improves data reading and writing rates.
As a preferred embodiment, the main control chip includes a hash processing module. The data is encrypted through the Hash processing module, and the safety of industrial data communication is guaranteed.
As a specific embodiment, the model of the master control chip is STM32F415 or STM32F 417. The STM32F415/417 is provided with a hash processing module and can encrypt communication data of the industrial equipment to ensure the safety of data transmission.
The utility model provides an ARM core board with an EtherCAT protocol interface, which is characterized in that real-time monitoring data of an equipment operation environment are acquired through a data acquisition interface, the real-time monitoring data are analyzed through a main control chip to obtain real-time analysis data, and the real-time analysis data are sent to a slave station controller; the slave station controller sends real-time analysis data to the master station industrial equipment, receives an operation instruction sent by the master station industrial equipment and sends the operation instruction to the master control chip; and the master control chip sends a control signal to the slave station controller after receiving the operation instruction, and the slave station controller sends the control signal to the slave station industrial equipment. According to the utility model, the master station industrial equipment can rapidly acquire the change of the running state of the equipment through the master control chip and the slave station controller, control information is sent to the slave station industrial equipment in time, the running mode of the slave station industrial equipment is adjusted, and the condition of abnormal running of the equipment is avoided; the transmission delay existing in the communication between the master station industrial equipment and the slave station industrial equipment is greatly reduced, the EtherCAT full duplex characteristic is fully utilized, the communication real-time performance is improved, the communication stability, the communication reliability and the effective data utilization rate are also obviously improved, and the complexity of the ARM core board in the industrial control is reduced. The static memory is used for storing the data, so that a data base is provided for subsequent data analysis and industrial equipment management optimization, and historical data can be prevented from being deleted by mistake when a system fails.
While the utility model has been described with reference to specific preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the utility model as defined in the following claims.
Claims (10)
1. The utility model provides an ARM core plate with etherCAT agreement interface, is applied to in the industrial equipment control system, its characterized in that includes: the system comprises a data acquisition interface, a master control chip, a static memory and a slave station controller; the master control chip is connected with the data acquisition interface, the slave station controller and the static memory;
the data acquisition interface is used for acquiring real-time monitoring data and sending the real-time monitoring data to the main control chip;
the master control chip is used for receiving the real-time monitoring data sent by the data acquisition interface, sending real-time analysis data to the slave station controller according to the real-time monitoring data, receiving an operation instruction returned by the slave station controller, sending a control signal to the slave station controller according to the operation instruction, and writing or reading storage data in the static memory;
the slave station controller is used for receiving the real-time analysis data sent by the master control chip, sending the real-time analysis data to the master station industrial equipment, receiving the operation instruction sent by the master station industrial equipment, sending the operation instruction to the master control chip, receiving the control signal sent by the master control chip and sending the control signal to the slave station industrial equipment;
the static memory is used for storing the stored data.
2. The ARM core board with the EtherCAT protocol interface of claim 1, further comprising an address decoder, wherein the address decoder is connected to the main control chip and the static memory;
the address decoder is used for receiving the address information sent by the main control chip, decoding the address information to obtain storage unit information, sending the storage unit information to the main control chip, and performing enable control on the static memory;
the main control chip is further configured to send address information to the address decoder, receive storage unit information sent by the address decoder, and write or read storage data in the static memory according to the storage unit information.
3. The ARM core board with EtherCAT protocol interface of claim 1, wherein the slave station controller comprises a plurality of ethernet ports and a plurality of PHY chips.
4. The ARM core board with EtherCAT protocol interface of claim 1, wherein the slave station controller comprises an HBI interface.
5. The ARM core board with the EtherCAT protocol interface of claim 1, wherein the data acquisition interface comprises a temperature and humidity sensor and a digital-to-analog conversion circuit.
6. The ARM core board with EtherCAT protocol interface of claim 1, further comprising a download circuit; the download circuit is connected with the main control chip;
the download circuit is used for updating the control program of the main control chip.
7. The ARM core board with EtherCAT protocol interface of claim 1, further comprising a reset circuit; the reset circuit is connected with the main control chip;
the reset circuit is used for restarting the main control chip.
8. The ARM core board with EtherCAT protocol interface of claim 1, further comprising a status indication circuit; the state indicating circuit is connected with the main control chip;
the state indicating circuit is used for displaying the working state of the main control chip.
9. The ARM core board with EtherCAT protocol interface of claim 1, wherein the master chip comprises an FSMC interface.
10. The ARM core board with EtherCAT protocol interface of claim 1, wherein the master control chip comprises a hash processing module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220708871.9U CN216979623U (en) | 2022-03-28 | 2022-03-28 | ARM core board with EtherCAT protocol interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220708871.9U CN216979623U (en) | 2022-03-28 | 2022-03-28 | ARM core board with EtherCAT protocol interface |
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| Publication Number | Publication Date |
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| CN216979623U true CN216979623U (en) | 2022-07-15 |
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| CN202220708871.9U Active CN216979623U (en) | 2022-03-28 | 2022-03-28 | ARM core board with EtherCAT protocol interface |
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