CN216956867U - Computer mainboard based on X100 nest of plates soars - Google Patents

Abstract

The utility model relates to the technical field of computer interface expansion, in particular to a computer mainboard based on a Feiteng X100 nest plate, wherein a domestic CPU, the Feiteng X100 nest plate and a CPLD chip are arranged on the mainboard; the Feiteng x100 set of sheets are connected with the domestic CPU through PCIE; the CPLD chip is connected with four interfaces of QSPI, GPIO, UART1 and UART0 on the domestic CPU. The utility model carries out interface expansion based on the Feiteng X100 chip, can meet the requirements of clock differential signal drive, serial ports, display interfaces, USB interfaces, PCIe expansion, SATA interfaces, sequential control and the like on a single chip because of having rich IO expansion functions, and can realize real-time temperature monitoring and intelligent fan speed regulation management. Meanwhile, the X100 scheme can reduce the use of non-domestic chips to the maximum extent on the premise of meeting the functional design, and the problems that the imported chips cannot be independently controlled in the key technology, the purchasing production period has uncertainty, and later-stage leaks cannot be predicted and avoided are solved.

Description

Computer mainboard based on X100 nest of plates soars

Technical Field

The utility model relates to the technical field of computer interface expansion, in particular to a computer mainboard based on Feiteng X100 nest plates.

Background

Due to the complex use scene, the general purpose computer needs to have rich functional interfaces. The previous generation of domestic computer designs have adopted a variety of imported chips to extend the peripheral interface. However, since the imported chip cannot be controlled independently in the key technology, the purchasing production period has uncertainty, and the late-stage leak cannot be predicted and avoided, the home-made replacement of the interface chip is imminent.

The utility model discloses a but prior art application number is CN 201910736403.5's utility model discloses a Local Bus interface extension device of PowerPC under pluggable expansion card structure relates to interface extension technical field, include: the system comprises a mainboard, a data processing unit and a data processing unit, wherein the mainboard is provided with a Local Bus master device interface, a logic processing unit, a plurality of Local Bus slave device interfaces, a first Local Bus slave device interface and a plurality of buffers; at least 2 expansion cards, wherein each expansion card corresponds to different buffers one by one; each expansion card is connected with an address Bus, a data Bus, a read enabling pin and a write enabling pin of a Local Bus main device interface through a corresponding cache; the logic processing unit is respectively connected with each expansion card and the buffer enabling pin corresponding to the expansion card. The utility model expands the number of Local Bus interfaces of the mainboard, and meets the use requirement on the basis of reducing the cost.

The prior art only expands the interface number of the mainboard and does not solve the problems that an imported chip cannot be independently controlled in a key technology, a purchasing production cycle has uncertainty and the like.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a computer mainboard based on Feiteng X100 nest plates, so as to solve the problems in the background technology.

In consideration of the characteristics of the Feiteng D2000/8 processor, the design scheme of the matching IO chip manufactured in China is actively researched and compared. Through market research, the newly-developed Feiteng X100 chip has abundant IO and widens the function, can satisfy demands such as clock differential signal drive, serial ports, display interface, USB interface, PCIe expansion, SATA interface, time sequence control on single chip to can realize real-time monitoring temperature, carry out fan intelligent speed governing management.

The adoption of the X100 scheme can reduce the use of non-domestic chips to the maximum extent on the premise of meeting the functional design.

In order to achieve the purpose, the utility model provides the following technical scheme: a computer mainboard based on Feiteng X100 nest plate is provided with a domestic CPU, a Feiteng X100 nest plate and a CPLD chip;

the Feiteng x100 set of chips is connected with a domestic CPU through PCIE;

and the CPLD is connected with four interfaces of QSPI, GPIO, UART1 and UART0 on the domestic CPU.

Preferably, the domestic CPU is externally provided with a plurality of PCIE3.0 interfaces, 2 gigabit ethernet controllers, 1 Flash controller, 1 SPI interface, 1 LPC interface, 4 UARTs, 4I 2C, 32 GPIO interfaces, 1 SD interface, 1 HDAudio interface, and 3 CAN interfaces.

Preferably, the mainboard extension is based on a Feiteng X100 set of slices, and the Feiteng X100 set of slices integrates 1 low-power GPU; integrating a 1-path VideoDecoder; integrating a 3-way displayport1.4 display interface; integrating 1 path of HDAudio and 3 paths of I2S interfaces; the 1-way 64-bit DDR4/LPDDR4 integrated display controller; integrating a PCIE3.0 Upstream interface of 16 Lanes on a 1-path and a PCIE3.0 Downstream interface on an 8-path; integrating 4 paths of SATA3.0 interfaces; integrating 8 independent USB 3.1 Gen 2 interfaces; integrating 2-path SD/SDIO/eMMC controllers; integrating 4 UARTs, 1 LPC Master, 64 GPIOs, 8 MIOs, 1 QSPI, 2 general SPI masters and 1 RTC; integrating 18 paths of differential clock driving interfaces and 2 paths of single-end clock driving interfaces; and integrating the control function of the whole machine.

Preferably, 2 gigabit ethernet controllers in the CPU peripheral all support gigabit and hundred megabytes simultaneously; the Flash controller supports 4 chip options, and the single chip supporting capacity is 512 MB.

Preferably, 4 UARTs are UART0, UART1, UART2 and UART3 respectively, UART0 is 9 line serial ports, UART1 is 3 line debugging serial ports, UART2 and UART3 are general serial ports.

Preferably, the control functions of the whole machine comprise power-on and power-off control, reset control and low power consumption control.

Compared with the prior art, the utility model has the beneficial effects that:

1. the utility model is based on the Feiteng X100 chip, has rich IO widening functions, can meet the requirements of clock differential signal drive, serial ports, display interfaces, USB interfaces, PCIe expansion, SATA interfaces, time sequence control and the like on a single chip, and can realize real-time temperature monitoring and intelligent fan speed regulation management.

Drawings

FIG. 1 is a schematic diagram of a motherboard structure according to the present invention;

FIG. 2 is a block diagram of the main board of the present invention;

FIG. 3 is a block diagram of a Feiteng X100 chip module design according to the present invention;

FIG. 4 is a diagram of the distribution of the motherboard clock signals according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-2, an embodiment of the present invention is shown: a computer mainboard based on Feiteng X100 nest plate is provided with a CPU, a Feiteng X100 nest plate and a CPLD chip; a plurality of PCIE slots are arranged outside the CPU; the Feiteng X100 set of sheets is electrically connected with one PCIE slot on the CPU; the CPLD chip is connected with four interfaces of QSPI (serial interface), GPIO (general purpose input/output), UART1 (universal asynchronous receiver transmitter) and UART0 on the CPU.

The CPU model is TengRui D2000/8, 8 high-performance cores with 64 bits are integrated, the dominant frequency is 2.0-2.6 GHz, and the commercial-grade working temperature range is 0-85 ℃; the industrial-grade working temperature range is-40 to 105 ℃. Meanwhile, a password acceleration engine is arranged in the system, and an integrated system level security mechanism can meet the sexual requirements in a complex application scene and has the characteristics of flexible configuration, low power consumption, rich interfaces and the like.

Wherein 4L 2 caches are arranged in the CPU, and each Cache stores 2MB and 8MB in total; 8L 3 caches, each of which stores 0.5MB and 4MB in total; the memory controller comprises 2 memory controllers, supports two DDR access channels, each channel comprises 64 data bits and 8 ECC check bits, supports UDIMM/SODIMM/RDIMM/LRDIMM, and can close one of the two memory controllers when in use.

The domestic CPU is externally provided with a plurality of PCIE3.0 interfaces, the PCIE interfaces are divided into two paths of PEU0 and PEU1, and each path of PEU supports the PCIe3.0 specification; the 2 kilomega Ethernet controllers support kilomega and hundred mega self-adaptation, and the physical interface supports MII and RGMII specifications; 1 Flash controller and 1 Flash controller of QSPI interface support 4 chip selections, and the maximum supporting capacity of a single chip is 512 MB; 1 SPI (serial peripheral) interface; 1 LPC (linear predictive coding) interface and 1 LPC interface, which are compatible with an Intel Low Pin Count protocol and can be connected with peripheral chips such as SuperIO and the like; 4 UARTs, 4I 2C (synchronous serial bus), 32 GPIO interfaces, 1 SD interface, 1 HDAudio (high fidelity audio) interface and 3 CAN (controller area network) interfaces, and are compatible with CAN2.0 standard protocols.

The main board shown in fig. 3-4 is based on a FT X100 nest plate, and the indexes are as follows:

a) 1 low-power GPU is integrated, the dominant frequency reaches 800MHz, the single-precision floating point peak value computing capacity is 400GFLOPS, the pixel filling rate is 6.4GPixel/S, and the texture filling rate is 12.8 GTextreme/S;

b) the integrated 1-path VideoDecoder supports a 4K @30fps decoding rate and mainstream encoding formats such as H.264/265, MPEG4, MPEG2 and JPEG;

c) the 3-way display Port1.4 display interface is integrated, wherein two ways support 3840x2160@60Hz, and the 1 way supports 1920x1080@60 Hz;

d) 1-path HDAudio and 3-path I2S interfaces are integrated to support high-definition audio playing;

e) the integrated 1-path 64-bit DDR4/LPDDR4 display controller supports the display memory capacity to be 8GB, the highest rate is 3200MT/s, and the peak bandwidth is 25.6 GB/s;

f) the integrated 1-path 16Lane PCIe3.0 Upstream interface and 8-path PCIe3.0 Downstream interface comprise 2 multiplied by 2Lane and 6 multiplied by 1 Lane;

g) integrating 4 paths of SATA3.0 interfaces;

h) integrating 8 independent USB 3.1 Gen 2 interfaces;

i) the integrated 2-path SD/SDIO/eMMC controller supports SD3.0, SDIO3.0 and Emmcc 5.0 protocol specifications;

j) integrating 4 UARTs, 1 LPC Master, 64 GPIOs, 8 MIOs (which can be configured into UART, I2C and PWM three modes), 1 QSPI, 2 general SPI masters and 1 RTC;

k) the integrated 18-path differential clock driving interface and 2-path single-end clock driving interface meet the reference clock requirements of high-speed serial interface equipment such as PCIe, USB and SATA.

l) integrating the control functions of the whole machine, including power-on and power-off control, reset control, low-power consumption control and the like.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "connected," and the like are to be construed broadly, such as "connected," which may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

It will be evident to those skilled in the art that the utility model is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the utility model being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (6)

1. A computer mainboard based on Feiteng X100 nest plate is characterized in that a domestic CPU, a Feiteng X100 nest plate and a CPLD chip are installed on the mainboard;

the Feiteng x100 set of sheets is connected with the domestic CPU through PCIE;

and the CPLD is connected with four interfaces of QSPI, GPIO, UART1 and UART0 on the domestic CPU.

2. The computer motherboard of claim 1, wherein the domestic CPU is externally provided with a plurality of PCIE3.0 interfaces, 2 gigabit ethernet controllers, 1 Flash controller, 1 SPI interface, 1 LPC interface, 4 UARTs, 4I 2C, 32 GPIO interfaces, 1 SD interface, 1 HDAudio interface, and 3 CAN interfaces.

3. The computer motherboard of claim 1, wherein the motherboard extension is based on a Feiteng X100 nest of slices, the Feiteng X100 nest of slices integrating 1 low power GPU; integrating a 1-path VideoDecoder; integrating a 3-way displayport1.4 display interface; integrating 1 path of HDAudio and 3 paths of I2S interfaces; the 1-way 64-bit DDR4/LPDDR4 integrated display controller; integrating a PCIE3.0 Upstream interface of 16 Lanes on a 1-path and a PCIE3.0 Downstream interface on an 8-path; integrating 4 paths of SATA3.0 interfaces; integrating 8 independent USB 3.1 Gen 2 interfaces; integrating 2-path SD/SDIO/eMMC controllers; integrating 4 UARTs, 1 LPC Master, 64 GPIOs, 8 MIOs, 1 QSPI, 2 general SPI masters and 1 RTC; integrating 18 paths of differential clock driving interfaces and 2 paths of single-end clock driving interfaces; and integrating the control function of the whole machine.

4. The computer motherboard of claim 2 wherein 2 gigabit ethernet controllers in the CPU peripheral each support both gigabytes and hundred megabytes simultaneously; the Flash controller supports 4 chip options, and the single chip supporting capacity is 512 MB.

5. The computer motherboard of claim 2, wherein the 4 UARTs are UART0, UART1, UART2 and UART3, respectively, the UART0 is a 9-wire serial port, the UART1 is a 3-wire debug serial port, and the UART2 and UART3 are universal serial ports.

6. The computer main board according to claim 3, wherein the overall control function includes power-on and power-off control, reset control, and low power consumption control.

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