CN216871954U

CN216871954U - System-in-package structure and electronic equipment

Info

Publication number: CN216871954U
Application number: CN202123195434.6U
Authority: CN
Inventors: 谢浩
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2021-12-17
Filing date: 2021-12-17
Publication date: 2022-07-01
Anticipated expiration: 2031-12-17

Abstract

The present disclosure relates to packaging, and particularly to a system-in-package structure and an electronic device. The system-in-package structure comprises an MCU bare chip and a memory bare chip, wherein the memory bare chip is arranged above the MCU bare chip, the MCU bare chip and the memory bare chip are arranged above a substrate in a packaging mode, the MCU bare chip and the memory bare chip are connected through at least three power binding lines, and the distance between the power binding lines is smaller than 100um, so that the self-inductance between the power binding lines is increased, the mutual inductance is large, the loop impedance is reduced, and the problem of voltage sag is solved.

Description

System-in-package structure and electronic equipment

Technical Field

The present application relates to the field of packaging, and in particular, to a system in package structure and an electronic device.

Background

At present, with the heat of a fire in a wearable market, a consumer has higher requirements for high resolution and high refresh rate of wearable equipment, especially for a smart watch and a bracelet, under the condition that the internal space of the wearable equipment is limited, a main control needs to seal memories such as a memory and a flash, and higher requirements are also provided for the communication rate of the main control and the memories, so that the supply voltage drop of the memories becomes more and more serious, and the communication error rate is increased.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a system-in-package structure and electronic equipment aiming at the problem of supply voltage drop of a memory in system-in-package.

A first aspect of embodiments of the present application provides a system-in-package structure, including an MCU die and a memory die, the memory die being disposed above the MCU die, the MCU die and the memory die being disposed above a substrate;

the MCU bare chip and the memory bare chip are connected through at least three first power binding lines;

the distance between the first power binding lines is less than or equal to 100 um.

In a possible implementation form, the distance between the first power binding lines is larger than or equal to 50um according to the first aspect.

In a possible implementation form according to the first aspect, the first power binding lines are arranged in parallel.

According to the first aspect, in one possible implementation, the heights of the first power binding lines are uniform; the routing arc height of the first power supply binding line is equal, and is more than or equal to 70um and less than or equal to 200 um.

According to the first aspect, in a possible implementation, the first power supply binding line comprises a binding line for the first common ground terminal and a binding line for the first operating voltage;

at least two binding lines of the first common ground terminal are provided;

at least two binding lines of the first working voltage are provided;

the binding lines of the first common ground terminal are parallel to each other; binding lines of the first working voltage are parallel to each other; the binding line of the first common ground terminal and the binding line of the first operating voltage are parallel to each other.

According to the first aspect, in a possible implementation manner, the substrate includes a routing layer of a common ground terminal and a routing layer of a working voltage, which are arranged in an upper layer and a lower layer;

the width of the routing layer of the common grounding end is equal to that of the routing layer of the working voltage; the width is 254 mm;

the routing layer of the common grounding end and the routing layer of the working voltage are equal in length; the lengths of the routing layer of the common grounding end and the routing layer of the working voltage are 1 mm;

the thickness of the routing layer of the common grounding end is equal to that of the routing layer of the working voltage; the thickness of the routing layer of the common grounding end and the routing layer of the working voltage is 50 um;

the distance between the routing layer of the common ground and the routing layer of the working voltage is less than or equal to 100 um.

According to the first aspect, in one possible implementation, a distance between a routing layer of the common ground and a routing layer of the operating voltage is greater than or equal to 20um and less than or equal to 50 um.

According to the first aspect, in a possible implementation manner, the display device further includes a first capacitor, and the first capacitor is disposed on the substrate;

the substrate is connected with the MCU bare chip through at least three second power binding lines; the second power supply binding line comprises a binding line of a second common ground terminal and a binding line of a second working voltage;

the first capacitor is connected with a bonding pad on the MCU bare chip through a second power supply binding line;

one end of the first capacitor is connected with the binding line of the second common grounding end, and the other end of the first capacitor is connected with the binding line of the second working voltage;

the bonding pads on the MCU bare chip comprise bonding wires of a second common grounding end and bonding pads corresponding to the bonding wires of the second working voltage.

According to the first aspect, in one possible implementation, the distance between the second power binding lines is less than or equal to 100 um; the distance between the second power binding lines is greater than or equal to 50 um;

the second power binding lines are arranged in parallel; the heights of the second power binding lines are consistent; the routing arc height of the second power supply binding line is equal, and is more than or equal to 70um and less than or equal to 200 um.

According to the first aspect, in one possible implementation, the first capacitance is 100pF to 1 uF; the self-resonant frequency of the first capacitance is greater than the communication speed of the memory die.

In a possible implementation according to the first aspect, the first capacitance is 100 nF.

According to the first aspect, in one possible implementation manner, the substrate is a BGA substrate, and a solder ball is disposed on a lower surface of the BGA substrate;

the substrate is arranged on the upper surface of the FPC or the PCB, a second capacitor is arranged on the upper surface of the FPC or the PCB and is connected with the solder balls of the BGA substrate, and the second capacitor is 1uF to 10 uF; the first capacitance is smaller than the second capacitance.

According to the first aspect, in one possible implementation, the substrate is a QFN substrate.

According to the first aspect, in one possible implementation, the memory die is a Flash die or a PSRAM die.

According to the first aspect, in a possible implementation manner, the memory further includes a resin material, and the resin material covers the memory die and the MCU die.

A second aspect of embodiments of the present application provides an electronic device, comprising the system-in-package structure of any one of the first aspects and a housing, the system-in-package structure being disposed within the housing, the housing being provided with a screen.

Compared with the prior art, the beneficial effects of the embodiment of the application lie in that: for a system-in-package, a Micro Controller Unit (MCU) die and a memory die are connected by at least three first power binding lines, and the distance between the first power binding lines is less than or equal to 100um, so that the loop impedance is small to improve the problem of voltage drop.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic diagram illustrating a module composition of a smart watch according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a peak current waveform of a PSRAM operating at 50MHz according to an embodiment of the present disclosure;

fig. 3 is a circuit diagram of a CMOS device according to an embodiment of the present application;

fig. 4 is a schematic diagram of supply voltage VDD dip and overshoot waveforms at a PSRAM end according to an embodiment of the present application;

fig. 5 is a waveform diagram of the supply voltage VDD at the PSRAM end under an ideal condition according to the embodiment of the present application;

fig. 6 is a schematic structural diagram of an SIP package according to an embodiment of the present disclosure;

fig. 7 is a schematic view illustrating a specific structure of a BGA substrate according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a VDD binding line and a VSS binding line being adjacent to each other according to an embodiment of the present application;

fig. 9 is a schematic diagram of a package structure according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a current loop provided in accordance with an embodiment of the present application;

FIG. 11 is a schematic diagram of yet another current loop provided by an embodiment of the present application;

FIG. 12 is a schematic diagram of yet another current loop provided in an embodiment of the present application;

fig. 13 is a schematic diagram of another current loop provided in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, some embodiments of the present application will be described in detail by way of example with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

Fig. 1 is a schematic diagram of a module composition of a smart watch including a Flash memory (Flash) module, a memory module, a main control module, and a screen. The main control module is connected with the Flash module and the memory module, and directly controls the display of the screen. The main control module is, for example, an MCU, wherein data related to configuration and firmware are stored in the Flash module, and data displayed in real time is cached in the memory module, so that the highest resolution and refresh rate that the main control can support are limited by the communication speed of the main control module and the memory module. For example, when the memory module is a Pseudo Static Random Access Memory (PSRAM), the PSRAM generally requires a working voltage of 1.8V, the working voltage range is 1.62-1.98V, and the highest communication speed is 200 MHz. When the power consumption of the memory module is too high, at the moment of reading and writing of the memory module, the high-frequency peak current pumped by the memory module can cause the working voltage of the memory module to drop or overshoot, so that the working voltage of the memory module exceeds the working voltage range, and therefore, the communication accuracy is reduced due to the voltage drop or overshoot, and error codes are caused.

Fig. 2 illustrates a schematic diagram of the peak current waveform of the PSRAM operating at 50MHz, and it can be seen that the memory draws a change in the current waveform from the operating voltage VDD during communication. The minimum value of the current was 50uA and the maximum value of the current was 117 mA. Taking a time length of 30ns as an example for analysis, when the memory is in communication, the peak current reaches 117mA, the time width of the peak is within 4ns, and in the time length of 30ns, the average value of the current is 65mA, and 3mA can be understood as the average current in the whole communication period. Along with the rise of the communication speed, the magnitude of the peak current can be increased, and the parasitic inductance on the wiring can cause obvious voltage drop, so that the power supply voltage of the memory cannot be ensured.

FIG. 3 of the present embodiment is used for analyzing the cause of voltage drop during memory communication, and the reason is shown in FIG. 3The Input voltage of a Complementary Metal Oxide Semiconductor (CMOS) device is shown to have a voltage dip when the IO (Input/Output) is high or low, and when the Input voltage of the CMOS device is switched from 0 to 1, for example, when the Input is switched from low Vss to high Vdd, the upper pipe PMOS is turned on, and the PMOS draws current from the supply voltage Vdd to drive the parasitic capacitor Cl. Due to the fact that parasitic parameters such as resistance, inductance and capacitance exist in the bare chip and the wiring in the package, the working voltage of the bare chip drops. Similarly, when the input voltage of the CMOS device is switched from 1 to 0, the capacitor

The stored charges can flow back from the lower tube NMOS, and in the process of flowing back of the charges, the parasitic inductance is encountered

Resulting in Vss rising and hence an overshoot in Vdd. Fig. 4 shows a schematic diagram of waveforms of the operating voltage VDD dip and overshoot at the PSRAM terminal, and fig. 5 shows a schematic diagram of a waveform of the operating voltage VDD at the PSRAM terminal under an ideal condition, wherein the horizontal axis represents time and the vertical axis represents voltage magnitude.

The embodiment of the application provides a package-level solution, solves the problem of voltage drop In System-In-package (SIP), and can support a higher communication rate. SIP packaging is a packaging scheme that integrates multiple functional wafers, including functional wafers such as processors and memories, into one package according to factors such as application scenarios and the number of layers of a packaging substrate, thereby achieving a substantially complete function. The system-in-package structure of the memory die and the MCU die is illustrated, and fig. 6 is an example of the system-in-package structure. The system-in-package structure shown in fig. 6 comprises an MCU die 63 and a memory die 64, wherein the MCU die 63 and the memory die 64 are bare die. The memory die 64 is disposed above the MCU die 63, the MCU die 63 and the memory die 64 are disposed in an encapsulated manner, and the MCU die 63 and the memory die 64 are disposed above the substrate 62 in an encapsulated manner, for example, by coating the MCU die 63 and the memory die 64 with a resin material, the MCU die 63 and the memory die 64 are disposed in the package.

The MCU die 63 and the memory die 64 are connected by at least three first power bonding (binding) lines, for example, 4 first power bonding lines in fig. 6, the MCU die 63 and the memory die 64 are connected by first

power bonding lines

661, 662, 663, and 664, and the distance between the four power bonding lines is less than or equal to 100 um. The number of the first power binding lines is at least 3, and the number of the first power binding lines can be 4, 5 or more when the cost and the space permit. The greater the number of first power binding lines the better, e.g. both positive and negative power supply voltages can correspond to at least two first power binding lines, reducing self-inductance by increasing the number of first power binding lines between the memory die and the MCU die, where cost and space allow. For example, binding lines corresponding to two operating voltages VDD and binding lines corresponding to three common ground terminals GND may be used as the first power supply binding lines. In this embodiment, at least three first power bonding lines are disposed between the MCU die and the memory die and the distance between the first power bonding lines is set to be less than or equal to 100um, so that Equivalent Resistance (ESR) and Equivalent Inductance (ESL) can be reduced, mutual Inductance is increased, and voltage sag is improved by reducing the impedance of the loop as a whole.

Based on the disclosure of the above embodiments, in this embodiment, the distance between the first power binding lines is greater than or equal to 50 um. Setting the distance between the first power binding lines to be less than or equal to 100um can increase mutual inductance, thereby improving voltage sag by reducing the impedance of the loop as a whole. However, if the distance between the first power binding lines is too small, contact between a plurality of the first power binding lines may be caused to cause a short circuit, and thus, in order to improve voltage sag and secure reliability of the system-in-package structure, the distance between the first power binding lines may be set to be less than or equal to 100um and greater than or equal to 50 um.

Based on the disclosure of the above embodiments, in this embodiment, the first power binding lines are arranged in parallel. Referring to fig. 6, the first

power binding lines

661, 662, 663, 664 are parallel to each other. Parallel to each other and the distance between the first power binding line is less than or equal to 100um between the first power binding line, can increase the two mutual inductances to thereby reduce the inductance reactance of return circuit and wholly reduce the impedance in return circuit, thereby realize further improvement voltage drop's purpose.

Based on the disclosure of the above embodiments, in the present embodiment, the heights of the first power binding lines are uniform. Referring to fig. 6, the first

power binding lines

661, 662, 663, 664 have the same height. Specifically, the routing arc heights of the first power

supply binding lines

661, 662, 663 and 664 are the same, so that the mutual inductance is larger when the distance between the first power supply binding lines is smaller than or equal to 100um at the same height, and the inductance of the loop is reduced, so that the impedance of the loop is integrally reduced, and the purpose of improving voltage drop is realized. In addition, in order to reduce the self-inductance and increase the mutual inductance, the length of the binding wire may be reduced.

Based on the disclosure of the above embodiments, in this embodiment, the first power supply binding line includes a binding line of a first common ground terminal Vss (also denoted as Vss) and a binding line of a first operating voltage VDD, where the binding line of the common ground terminal is used for connecting a voltage of the common ground terminal, which can be generally understood as being used for connecting a low potential point in the power supply, and the binding line of the operating voltage is used for connecting an operating voltage, which can be generally understood as being used for connecting a high potential point in the power supply. Specifically, at least two binding lines of the first common ground terminal are provided, and at least two binding lines of the first operating voltage are provided. Referring to fig. 6, the first power supply binding line 661 and the first power supply binding line 662 are binding lines corresponding to Vss, and the first power supply binding line 663 and the first power supply binding line 664 are binding lines corresponding to VDD. The

binding lines

661, 662 of the first common ground terminal are parallel to each other, the

binding lines

663, 664 of the first operating voltage are parallel to each other, and the

binding lines

661, 662 of the first common ground terminal and the

binding lines

663, 664 of the first operating voltage are parallel to each other. The parallelism between the first power binding lines can reduce the inductive reactance of the loop between VDD and VSS, thereby improving the voltage drop. When the first power binding lines are parallel and the distance between the first power binding lines is smaller than or equal to 100um, the mutual inductance between the first power binding lines and the second power binding lines is increased, so that the inductive reactance of the VDD and VSS loops is reduced, the impedance of the loops is integrally reduced, and the purpose of improving voltage drop is achieved.

Based on the disclosure of the above embodiments, in this embodiment, the memory die may be a Flash die or a PSRAM die, and the memory die is taken as the PSRAM die in this embodiment as an example. The MCU die and the PSRAM die package are disposed above the substrate, and as shown in fig. 6, the PSRAM die 64 and the MCU die 63 are fixed on a Printed Circuit Board (PCB) 61 through a Ball Grid Array (BGA) package. In addition, the MCU die and the PSRAM die may be BGA packages, or may be Quad Flat No-leads (QFN) packages.

Based on the disclosure of the above embodiments, in this embodiment, the substrate is a BGA substrate. The system-in-package structure further comprises a BGA substrate 62, a PSRAM bare chip 64 is arranged above the MCU bare chip 63, and the PSRAM bare chip and the MCU bare chip are connected through a first power binding line. The MCU bare chip is connected with the PCB through the BGA substrate. In the present embodiment, the self-inductance is reduced by increasing the number of first power binding lines between the memory die and the MCU die, and by reducing the distance between the first power binding lines.

In this embodiment, VSS or VSS represents the common ground voltage GND. The mutual inductance of the VDD and VSS can be increased by making the binding lines as close to each other as possible in parallel, thereby reducing the impedance of the loop as a whole. Specifically, referring to fig. 6, 4 first

power binding lines

661, 662, 663, and 664 are disposed between the PSRAM die and the MCU die, where the first power binding line 661 and the first power binding line 662 are VSS-corresponding binding lines, and the first power binding line 663 and the binding line 664 are VDD-corresponding binding lines. The PSRAM die is provided with at least 4

pads

651, 652, 653, and 654, where the pad 651 and the pad 652 are VSS-corresponding pads, and the pad 653 and the pad 654 are VDD-corresponding pads. The MCU die is provided with at least 8

pads

671, 672, 673, 674, 681, 682, 683 and 684, wherein the

pads

671, 672, 673 and 674 are connected with the

pads

651, 652, 653, 654 of the PSRAM die through first

power bonding lines

661, 662, 663, 664, respectively. The first

power binding lines

661, 662, 663, 664 used to connect the PSRAM die and the MCU die are parallel to each other. The MCU die is connected to the BGA substrate via second power-supply-binding

lines

691, 692, 693, 694, and specifically,

pads

681, 682, 683, 684 of the MCU are connected to

pads

6101, 6102, 6103, 6104 of the BGA substrate via the second power-supply-binding

lines

691, 692, 693, 694, respectively. In this embodiment, similar to the first power binding lines, the distance between the second power binding lines is less than or equal to 100um to increase mutual inductance so as to improve voltage sag, and the distance between the second power binding lines is greater than or equal to 50um, so that the reliability of the system-in-package structure can be ensured while improving voltage sag.

Based on the disclosure of the above embodiments, in the present embodiment, the second power-binding

lines

691, 692, 693, 694 are disposed in parallel and the heights of the second power-binding lines are uniform to increase mutual inductance to improve the voltage drop phenomenon.

The bonding pad 681 and the bonding pad 682 of the MCU die are bonding pads corresponding to VDD, and the bonding pad 683 and the bonding pad 684 of the MCU die are bonding pads corresponding to VSS. Accordingly, the pads 6101 and 6102 of the BGA substrate are pads for VDD, and the

pads

6103 and 6104 of the BGA substrate are pads for VSS.

In this embodiment, the substrate is connected with the MCU bare chip through at least three second power bonding lines, the number of the second power bonding lines is increased to reduce Equivalent Resistance (ESR) and Equivalent Inductance (ESL), and in addition, the parallel between the second power bonding lines can reduce the Inductance of the loop between VDD and VSS, thereby improving voltage sag. The second power source binding lines are parallel, the distance between the second power source binding lines is smaller than or equal to 100um, so that mutual inductance of the second power source binding lines and the second power source binding lines is increased, the inductive reactance of VDD and VSS loops can be further reduced, the impedance of the loops is integrally reduced, and the purpose of improving voltage drop is achieved.

Based on the disclosure of the above embodiment, in this embodiment, the first capacitor 611 may be encapsulated in the package structure, the first capacitor 611 has a smaller capacity, the first capacitor 611 is disposed on the BGA substrate, the first capacitor 611 is disposed between the pad corresponding to VDD and the pad corresponding to VSS of the BGA substrate, the first capacitor 611 is connected to the pad corresponding to VDD and the pad corresponding to VSS of the BGA substrate, one end of the first capacitor is connected to the binding line 692 of the second common ground terminal, and the other end of the first capacitor is connected to the binding line 693 of the second operating voltage. The first capacitance 611 is connected to

pads

682, 683 on the MCU die via second

power binding lines

692, 693, respectively. The second power supply binding line includes a binding line for a second common ground terminal and a binding line for a second operating voltage. Specifically, the second power

supply bonding lines

691 and 692 are bonding lines corresponding to the second operating voltage VDD, and the second power

supply bonding lines

693 and 694 are bonding lines corresponding to the bonding line VSS of the second common ground terminal. The bonding pads on the MCU bare chip comprise bonding wires of a second common grounding end and bonding pads corresponding to the bonding wires of the second working voltage. In general, the electromotive force of the binding line of the second common ground terminal is substantially equal to the electromotive force of the binding line of the first common ground terminal, and the electromotive force of the binding line of the second operating voltage is substantially equal to the electromotive force of the binding line of the first operating voltage. The first capacitor 611 has a small capacitance of 100pF to 1uF, for example 100 nF. The system-in-package structure shown in fig. 6 includes two

capacitors

611 and 612, wherein a smaller first capacitor 611 is disposed inside the package, a larger second capacitor 612 is disposed outside the package, for example, the second capacitor can be set to 4.7uF, the second capacitor 612 is used to filter low-frequency current, and the first capacitor 611 is used to filter high-frequency spike current when the memory die is read or written. The Self-Resonant Frequency of the first capacitor is greater than the communication speed of the memory die, and for the first capacitor in this embodiment, the Self-Resonant Frequency (SRF) of the first capacitor is greater than the communication bandwidth of the PSRAM, that is, the SRF of the smaller capacitor is greater than the communication speed of the PSRAM, for example, the current PSRAM model supports a communication speed of up to 200MHz, the SRF of the first capacitor may be set to be greater than or equal to 200MHz, which may ensure that the first capacitor may be capacitive at high Frequency, so that the droop capacitance caused by the PSRAM die and the MCU die during high-speed communication may be further improved. After the first capacitor 611 is arranged in the packaging structure, the memory die can draw current from the first capacitor in the packaging structure nearby during reading and writing, so that the load of a power supply is reduced, and voltage drop is improved.

Solder balls

6132 and 6131 are disposed under the BGA substrate of the package structure shown in fig. 6, the substrate is disposed on a Flexible Printed Circuit (FPC) or an upper surface of a PCB, and the substrate is disposed on the upper surface of the FPC for illustration in this embodiment. The BGA substrate is electrically connected with the FPC through the solder balls. The solder ball 6131 may be an electrical connection point corresponding to VDD, the solder ball 6132 may be an electrical connection point corresponding to VSS, a second capacitor 612 may be disposed on the FPC, two ends of the second capacitor 612 are respectively connected to the solder ball 6132 and the solder ball 6131 below the BGA substrate, the second capacitor may be set to 1uF to 10uF, and in this embodiment, the first capacitor is smaller than the second capacitor.

Based on the disclosure of the above embodiments, the present embodiment proposes a system-in-package structure for increasing mutual inductance, and if the substrate is a BGA substrate, for example, for the BGA substrate shown in fig. 6, reference may be made to the specific structure of BGA substrate 72 shown in fig. 7. The BGA substrate comprises two routing layers, wherein the two routing layers are a routing layer 702 of a common grounding end and a routing layer 701 of a working voltage, which are arranged at the upper layer and the lower layer, in the embodiment, the routing layer of the working voltage is also called as a VDD routing layer, and the routing layer of the common grounding end is also called as a VSS routing layer. The memory die 74 is disposed on the BGA substrate 72 and electrically connected by a second power bonding line. For the two-layer routing layer of a BGA substrate, power supply 70 is connected to the two-layer routing layer to provide power to the two-layer routing layer, with the direction of current flow in the two-layer routing layer being as shown in FIG. 7, with current flowing from the VDD routing layer to the memory die 74 and back to the VSS routing layer 702. In this embodiment, the VDD routing layer and the VSS routing layer are disposed at two layers adjacent to each other up and down and mutual inductance can be improved by reducing the distance h between the two layers. Specifically, the distance between the routing layer of the common ground and the routing layer of the operating voltage is less than or equal to 100um, so that mutual inductance can be improved, and voltage drop can be improved. Furthermore, the distance between the routing layer of the common ground terminal and the routing layer of the working voltage is smaller than or equal to 50um, so that mutual inductance can be further improved, and voltage drop is improved. The closer the distance between the VDD routing layer and the VSS routing layer, i.e. the smaller h, the greater the mutual inductance M between the VDD routing layer and the VSS routing layer. The inductive reactance of the loop of the VDD routing layer and the VSS routing layer is equal to the self-inductance minus 2 times of the mutual inductance, and therefore, the loop inductive reactance can be obviously reduced by increasing the mutual inductance.

Based on the disclosure of the above embodiments, in this embodiment, the width d1 of the VDD routing layer is equal to the width d2 of the VSS routing layer, and mutual inductance is the largest when the widths of the VDD routing layer and the VSS routing layer are the same, for example, the widths of the VDD routing layer and the VSS routing layer may be 10mil, i.e. about 254mm, and when the width is larger, the package is larger, which is not favorable for integration into a small electronic device, and therefore, the width setting to about 254mm may facilitate miniaturization of the substrate and thus the package may be used for a small electronic device. The impedance R of a loop of the VDD routing layer and the VSS routing layer is ESR + Lvdd + Lvss-2M, Lvdd is the inductance of the VDD routing layer, Lvss is the inductance of the VSS routing layer, and the impedance of the loop can be reduced by increasing the mutual inductance M. The smaller the length of the VDD routing layer and the VSS routing layer, the better. The smaller the length, the smaller the inductance and the smaller the loop impedance. In addition, when the lengths of the VDD routing layer and the VSS routing layer are equal, the total inductive reactance of the loop is relatively minimal, and for example, the lengths of the VDD routing layer and the VSS routing layer can be set to 1 mm. The thickness of the VDD routing layer and the VSS routing layer can be several ounces, for example, 1 ounce, about 35um, and the thickness depends on the process implementation, and the thickness of the VDD routing layer and the VSS routing layer is equal, which is beneficial for the process implementation, for example, both can be set to 50 um. The VDD wiring layer and the VSS wiring layer are as thick as possible, the larger the thickness of the VDD wiring layer and the VSS wiring layer is, the smaller the self-inductance is, the smaller the loop impedance is, but the larger the thickness is, the higher the cost is, and when the thickness is 50um, the minimum total inductive reactance of the loop can be ensured, and the cost can also be controlled. When the length of the VDD routing layer and the VSS routing layer is 1mm and the thickness is 50um, the loop impedance can be small and thus the voltage droop is also small.

Fig. 8 illustrates a scheme of increasing mutual inductance between the binding lines, where the first power binding line corresponding to VDD and the first power binding line corresponding to VSS are adjacent to each other. The distance H1 from the highest point of the first power supply binding line corresponding to VDD to the pad corresponding to VDD is equal to the distance H1 'from the highest point of the first power supply binding line corresponding to VSS to the pad corresponding to VSS, that is, the routing arc height H1 of the first power supply binding line is equal to H1', and specifically, the routing arc height is greater than or equal to 50um so as to facilitate the process implementation. The higher the routing arc height, the longer the overall length of the binding wire, and thus the greater the inductance of the binding wire, e.g., the routing arc height may be greater than or equal to 70 um. But the wire bond arc is too high, which may increase cost and package size, and thus, the wire bond arc is less than or equal to 200 um. Similarly, the routing arc height H1 of one end of the first power binding line is H1 ', the routing arc height H2 of the other end of the first power binding line is H2', and H1 is H1 'or H2 is H2'. The bonding wires of VDD and VSS are controlled to have the same bonding arc height, so that the mutual inductance is the largest when the bonding wires are at the same height and the distance between the bonding wires is the shortest. In order to reduce self-inductance and increase mutual inductance, the length of the binding lines can be reduced, the routing arc height can be controlled, and in addition, the distance d between the binding lines can be reduced. In this embodiment, the setting of the routing arc height of the first power supply binding line can be applied to the second power supply binding line, for example, the heights of the second power supply binding lines are consistent; the routing arc height of the second power supply routing line is equal, the routing arc height is larger than or equal to 70um and smaller than or equal to 200um, and voltage drop can be further improved.

Fig. 9 is a schematic diagram of a package structure of this embodiment, wherein distances between binding lines corresponding to VDD and VSS are equal, where the binding lines corresponding to VDD and VSS may represent a first power binding line or a second power binding line. In this embodiment, the binding lines corresponding to VDD and VSS are parallel as much as possible. Fig. 9 (a) shows a package structure in which a binding line 801 corresponding to VDD is not parallel to a binding line 802 corresponding to VSS, in which the binding line 801 corresponding to VDD is connected to a pad 804 corresponding to VDD, and the binding line 802 corresponding to VSS is connected to a pad 803 corresponding to VSS. For the scheme provided by the embodiment of the application, the binding lines corresponding to VDD and VSS are parallel as much as possible, and the distance between the two binding lines is equal as much as possible, for example, the distance between the binding lines corresponding to VDD and VSS is less than or equal to 100 um. Fig. 9 (b) shows that the distance between the VDD-corresponding binding line 801 'and the VSS-corresponding binding line 802' is 100um or less, in which the VDD-corresponding binding line 801 'is connected to the VDD-corresponding pad 804' and the VSS-corresponding binding line 802 'is connected to the VSS-corresponding pad 803'. The positional relationship shown in fig. 9 (b) is merely illustrative, and for QFN packages, the binding line for VSS may be connected to the middle large al-based thermal pad, and the binding line for VDD may be connected to the PIN (PIN) beside the al-based thermal pad. In fig. 9 (b), the heights of the portions of the bonding wires higher than the pads are the same, the bonding wire corresponding to VDD and the bonding wire corresponding to VSS are in a parallel positional relationship as much as possible, and the distance between the bonding wires is set to be short, so that mutual inductance can be increased to reduce the inductive reactance of the loop.

The circuit structure shown in fig. 10 is a schematic diagram of a loop impedance, and the instantaneous current during the memory die communication needs to be provided by the second capacitor on the PCB, where the loop impedance includes the impedance contributed by the PCB, the package substrate, and the binding line from the bare die to the package substrate. L _ PCB represents the parasitic inductance of the PCB trace required for the second capacitor outside the package, or the parasitic inductance of the FPC trace. L _ sub represents the parasitic inductance on the package substrate. In this embodiment, the package substrate may be a BGA substrate or a QFN substrate. L _ MCU2sub represents the parasitic inductance of the bonding line from the MCU to the BGA substrate. In this embodiment, the MCU bare chip may also be a Bluetooth (BLE) bare chip. L _ MCU2Memory represents the parasitic inductance of the binding line between the MCU die and the Memory die. VDD _ Memory represents the operating voltage of the Memory die within the package, VSS _ Memory represents the voltage of the common ground of the Memory die within the package, and VSS represents the voltage of the common ground outside the package, e.g., the voltage of the common ground on a PCB. The voltage of the low dropout regulator (LDO) may be 1.8V, and Cap1 represents a second capacitor on the PCB, which may be, for example, 1uF to 10 uF. Drawing current while the memory die is operating requires the largest current loop, as indicated by the arrows in fig. 10, to maximize the loop impedance.

Based on the content of the foregoing embodiments, in this embodiment, if the binding lines corresponding to VDD and VSS are parallel to increase mutual inductance, or the distance between the binding lines corresponding to VDD and VSS is set to be less than or equal to 100 um. The inductive reactance of the loop is reduced relative to the current path of fig. 10.

Fig. 11 is a schematic diagram illustrating loop impedance of a scheme of increasing the number of bonding wires, and the overall loop impedance is reduced by increasing mutual inductance between the first power bonding wires corresponding to VDD and VSS between bare die without additionally adding other devices, for example, setting the number of the first power bonding wires to be greater than 3. Specifically, referring to fig. 11, the loop impedance rhuman of the device is 2 × L _ PCB +2 × L _ sub +2 × L _ MCU2Memory-M0-M1-M2-M3, where M0 is mutual inductance between the bonding lines for connecting the Memory and the MCU, M3 is mutual inductance between the bonding lines for connecting the BGA substrate and the MCU, M2 is mutual inductance between the VDD routing layer and the VSS routing layer in the BGA substrate, and M1 is mutual inductance between the bonding lines for connecting the PCB and the BGA substrate.

Fig. 12 illustrates a schematic diagram of reducing the loop impedance of the loop impedance path by providing the first capacitor Cap2 in the package, where the first capacitor Cap2 may have any value from 1nF to 0.1uF, the peak current of the memory device may be obtained by the first capacitor in the package without being obtained through the capacitor on the PCB, and the loop impedance thereof does not include the mutual inductance of the bonding line connecting the PCB and the substrate, the mutual inductance between the VDD routing layer and the VSS routing layer in the BGA substrate, or the parasitic inductance of the routing of the PCB and the parasitic inductance on the package substrate required by the large capacitor outside the package. Its loop impedance Rhuan is 2 × L _ MCU2Memory-M0(M0 is not shown in fig. 12). The first capacitor is arranged in the package, so that the high-frequency spike current during reading and writing of the memory can be obtained from the first capacitor inside the package, and therefore, the current loop is reduced, the total impedance of the loop is also reduced, and the current loop can be referred to as an arrow in fig. 12.

With reference to fig. 13, the loop impedance diagram shown in fig. 13 is obtained by correspondingly increasing the number of the first power binding lines and the distance between the first power binding lines is less than or equal to 100um, and a first capacitor is disposed in the package. The flow direction of the high frequency spike current, which is only present inside the package, i.e. only between the memory die and the MCU die, is indicated by the small arrow on the right in fig. 13, which can be understood as a small current loop. The low frequency current passes from the large current loop, which can be referred to as the large arrow on the left in fig. 13. As can be seen from fig. 13, the loop impedance is significantly reduced.

The scheme provided by the embodiment solves the problem that the voltage drop is serious when the power supply of the storage device end in the SIP package is carried out, and can support higher communication speed, thereby supporting the electronic equipment with a screen with higher resolution and high refresh rate.

The electronic device provided by this embodiment includes any one of the system-in-package structures in the foregoing embodiments, and further includes a housing, where the housing is further provided with a screen, and a structure diagram of the electronic device may be as shown in fig. 1. The specific implementation manner and the beneficial effects of the system-in-package structure provided by the embodiment of the present application are described in the above embodiments, and are not described herein again.

It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A system-in-package structure comprising an MCU die and a memory die, the memory die disposed above the MCU die, the MCU die and the memory die package disposed above a substrate;

2. The system-in-package structure of claim 1, wherein a distance between the first power binding lines is greater than or equal to 50 um.

3. The system-in-package structure of claim 1, wherein the first power binding lines are disposed in parallel.

4. The system-in-package structure of claim 1, wherein the first power binding lines are uniform in height; the routing arc height of the first power supply binding line is equal, and is more than or equal to 70um and less than or equal to 200 um.

5. The system-in-package structure according to any one of claims 1 to 4, wherein the first power binding line comprises a binding line for a first common ground terminal and a binding line for a first operating voltage;

at least two binding lines of the first common ground terminal are provided;

at least two binding lines of the first working voltage are provided;

the binding lines of the first common ground terminal are parallel to each other; the binding lines of the first working voltage are parallel to each other; the binding line of the first common ground terminal and the binding line of the first operating voltage are parallel to each other.

6. The system-in-package structure according to claim 5, wherein the substrate comprises a common ground routing layer and an operating voltage routing layer disposed on an upper layer and a lower layer;

and the distance between the routing layer of the common grounding end and the routing layer of the working voltage is less than or equal to 100 um.

7. The system-in-package structure of claim 6, wherein a distance between a routing layer of the common ground and a routing layer of the operating voltage is greater than or equal to 20um and less than or equal to 50 um.

8. The system-in-package structure according to claim 5, further comprising a first capacitor disposed on the substrate;

the first capacitor is connected with a bonding pad on the MCU bare chip through the second power binding line;

one end of the first capacitor is connected with the binding line of the second common ground terminal, and the other end of the first capacitor is connected with the binding line of the second working voltage;

and the bonding pads on the MCU bare chip comprise bonding pads corresponding to the bonding wire of the second common grounding end and the bonding wire of the second working voltage.

9. The system-in-package structure of claim 8, wherein the distance between the second power binding lines is less than or equal to 100 um; the distance between the second power binding lines is greater than or equal to 50 um;

10. The system-in-package structure according to claim 8, wherein the first capacitance is 100pF to 1 uF; the self-resonant frequency of the first capacitance is greater than a communication speed of the memory die.

11. The system-in-package structure according to claim 8, wherein the first capacitance is 100 nF.

12. The system-in-package structure according to claim 8, wherein the substrate is a BGA substrate, and a lower surface of the BGA substrate is provided with solder balls;

the substrate is arranged on the upper surface of an FPC (flexible printed circuit) or a PCB (printed circuit board), a second capacitor is arranged on the upper surface of the FPC or the PCB, the second capacitor is connected with the solder balls of the BGA substrate, and the second capacitor ranges from 1uF to 10 uF; the first capacitance is less than the second capacitance.

13. The system-in-package structure according to any one of claims 1 to 4, wherein the substrate is a QFN substrate.

14. The system-in-package structure according to any one of claims 1 to 4, wherein the memory die is a Flash die or a PSRAM die.

15. The system-in-package structure according to any one of claims 1 to 4, further comprising a resin material encapsulating the memory die and the MCU die.

16. An electronic device, comprising the system-in-package structure of any one of claims 1 to 15 and a housing, the system-in-package structure being disposed within the housing, the housing being provided with a screen.