CN216870803U - Pseudo-random noise radar integrated chip - Google Patents
Pseudo-random noise radar integrated chip Download PDFInfo
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- CN216870803U CN216870803U CN202123288521.6U CN202123288521U CN216870803U CN 216870803 U CN216870803 U CN 216870803U CN 202123288521 U CN202123288521 U CN 202123288521U CN 216870803 U CN216870803 U CN 216870803U
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- 238000006243 chemical reaction Methods 0.000 claims description 8
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
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Abstract
The utility model relates to the field of radar system chips, in particular to a pseudo-random noise radar integrated chip, which is used for a radar system for detecting an emergency rescue site target and comprises a signal receiving and transmitting circuit module arranged on the radar system chip, wherein the signal receiving and transmitting circuit module comprises: the device comprises a transmitting link and a receiving link, wherein the transmitting link is arranged on a single chip and used for signal output and the receiving link is used for processing an echo signal and transmitting the echo signal to a baseband, and the transmitting link comprises: the phase-locked loop I, the pseudo-random binary sequence generator, the binary phase shift keying modulator, the power amplifier and the transmitting antenna; the receiving chain comprises: a receiving antenna, a low noise amplifier, a phase-locked loop II and an I/Q mixer. The radar target detection system is simple in structure, scientific and reasonable in design, capable of avoiding influence of part processes, voltage and temperature on signals in the detection process, and suitable for application of emergency rescue site target detection radar systems such as security and the like.
Description
Technical Field
The utility model relates to the field of radar system chips, in particular to a pseudo-random noise radar integrated chip which can be applied to a radar system for detecting an object in an emergency rescue site.
Background
The radar system is widely applied to the fields of security and protection and the like, and compared with the traditional optical monitoring equipment, the radar system can perform real-time imaging in severe weather such as night, foggy days and rainy days, and the detection accuracy is higher. In short range automotive or industrial radar applications, high target resolution radar is of paramount importance, and resolution is in turn directly related to the modulation bandwidth of the radar system. The frequency modulated continuous wave radar technology widely used in current radar sensors relies on a large tuning range of a voltage controlled oscillator, and the voltage controlled oscillator is affected by process, temperature and voltage changes, and this type of radar also degrades continuously with the increase of the operation time. This technique is therefore not suitable for security applications requiring high resolution and high elasticity.
Disclosure of Invention
Therefore, the pseudo-random noise radar integrated chip provided by the utility model has high integration level, uses the pseudo-random sequence generated by the pseudo-random binary sequence generator as the excitation of the transmitting antenna, effectively avoids the influence of the process, voltage and temperature of parts on signals in the detection process, and is suitable for application of an emergency rescue site target detection radar system for security protection and the like.
According to the design scheme provided by the utility model, the pseudo-random noise radar integrated chip is used for a radar system for detecting the target in an emergency rescue site, and comprises a signal receiving and transmitting circuit module arranged on the radar system chip, wherein the signal receiving and transmitting circuit module comprises: the device comprises a transmitting link and a receiving link, wherein the transmitting link is arranged on a single chip and used for signal output and the receiving link is used for processing an echo signal and transmitting the echo signal to a baseband, and the transmitting link comprises: the phase-locked loop I is used for generating a clock signal of a transmission link, the phase-locked loop I is connected with the phase-locked loop I and used for generating a pseudo-random binary sequence generator which is used as a broadband excitation pseudo-random binary sequence, the phase-shift keying binary modulator is connected with the pseudo-random binary sequence generator and used for modulating the pseudo-random binary sequence, the phase-shift keying binary modulator is connected with the pseudo-random binary sequence generator and used for amplifying the modulated sequence signal, and the transmitting antenna is connected with the power amplifier and used for transmitting the amplified signal; the receiving chain comprises: the receiving antenna is used for receiving a target signal, the low-noise amplifier is connected with the receiving antenna and used for amplifying the received target signal, the second phase-locked loop is used for generating a carrier signal of a receiving link, and the I/Q mixer is connected with the second phase-locked loop and the low-noise amplifier and used for combining the carrier signal and performing frequency conversion processing on an output signal of the low-noise amplifier.
As the pseudo random noise radar integrated chip of the present invention, further, the receiving link includes: the low-noise amplifier comprises two frequency mixing branches connected with the low-noise amplifier and two carrier driving branches connected with a phase-locked loop II, wherein carrier signals output by the phase-locked loop II are divided into two local oscillator signals by the two carrier driving branches, one local oscillator signal drives an I path of an I/Q mixer, the other local oscillator signal drives a Q path of the I/Q mixer after being subjected to transposition processing, and the output of the low-noise amplifier is subjected to frequency conversion processing by the I/Q mixer and then serves as an input signal of a radar system baseband processing module.
As the pseudo-random noise radar integrated chip, the receiving link also comprises a duplexer connected with the two outputs of the phase-locked loop and used for isolating the transmitting link and the receiving link, and the duplexer receives the carrier signals output by the two outputs of the phase-locked loop and respectively feeds the carrier signals into the binary phase shift keying modulator of the transmitting link and the I/Q mixer in the receiving link.
The utility model has the beneficial effects that:
the utility model has simple structure and scientific and reasonable design, the transmitting link and the receiving link are integrated on a single chip, thereby realizing the reduction of the cost, the volume, the power consumption and the like of a radar system, the ultra-wide band pseudo-random binary sequence is adopted as the excitation, so that the radar chip has no influence caused by the process, the temperature and the voltage change of a voltage-controlled oscillator, and can be used for different sensing applications which need high reliability and high resolution, the receiving link adopts an I/Q two-path mixer, the image rejection performance of intermediate frequency signals can be improved, the problems that the frequency modulation continuous wave radar which is widely used in the current radar sensor excessively depends on the voltage-controlled oscillator and the like are solved, the dispatching and the commanding of the emergency rescue field work are met, and the utility model has better application prospect.
Description of the drawings:
FIG. 1 is a schematic diagram of a circuit module for transmitting and receiving signals of an embodiment of a PRAM integrated chip.
In the figure, reference numeral 1 denotes a transmitting antenna, reference numeral 2 denotes a receiving antenna, reference numeral 3 denotes a power amplifier, reference numeral 4 denotes a low noise amplifier, reference numeral 5 denotes an I/Q mixer, and reference numeral 6 denotes a duplexer.
The specific implementation mode is as follows:
the present invention will be described in further detail below with reference to the accompanying drawings and technical solutions, and embodiments of the present invention will be described in detail by way of preferred examples, but the embodiments of the present invention are not limited thereto.
The widely used frequency modulation continuous wave radar technology in the radar sensor depends on a larger tuning range of a voltage-controlled oscillator, the voltage-controlled oscillator can be influenced by the process, the temperature and the voltage change, the radar of the type can be degraded along with the increase of the operation time, and the radar is not suitable for a radar system for detecting the target in an emergency rescue site. To this end, an embodiment of the present invention provides a pseudo-random noise radar integrated chip, which is used for a radar system for detecting an object in an emergency rescue scene, and includes a transceiver circuit module disposed on the radar system chip, where the transceiver circuit module includes: the device comprises a transmitting link and a receiving link, wherein the transmitting link is arranged on a single chip and used for signal output and the receiving link is used for processing an echo signal and transmitting the echo signal to a baseband, and the transmitting link comprises: the system comprises a phase-locked loop I, a pseudo-random binary sequence generator, a binary phase shift keying modulator, a power amplifier 3 and a transmitting antenna 1, wherein the phase-locked loop I is used for generating a transmitting link clock signal, the pseudo-random binary sequence generator is connected with the phase-locked loop I and is used for generating a broadband excitation pseudo-random binary sequence, the binary phase shift keying modulator is connected with the pseudo-random binary sequence generator and is used for modulating the pseudo-random binary sequence, the power amplifier 3 is connected with the binary phase shift keying modulator and is used for amplifying the modulated sequence signal, and the transmitting antenna 1 is connected with the power amplifier and is used for transmitting the amplified signal; the receiving chain comprises: the receiving antenna 2 is used for receiving a target signal, the low noise amplifier 4 is connected with the receiving antenna and used for amplifying the received target signal, the phase-locked loop II is used for generating a carrier signal of a receiving link, and the I/Q mixer 5 is connected with the phase-locked loop II and the low noise amplifier and used for combining the carrier signal and carrying out frequency conversion processing on an output signal of the low noise amplifier. The transmitting link and the receiving link are integrated on a single chip, so that the cost, the volume, the power consumption and the like of a radar system are reduced, an ultra-wide band pseudo-random binary sequence is used as excitation, the influence caused by the process of a voltage-controlled oscillator, the temperature and the voltage change does not exist in the radar chip, the radar chip can be used for different sensing applications needing high reliability and high resolution, the receiving link adopts an I/Q two-path mixer, the image rejection performance of intermediate frequency signals can be improved, and the radar chip is convenient for practical scene application.
As the pseudo random noise radar integrated chip in the embodiment of the present invention, further, the receiving link includes: the two carrier driving branches are connected with the low noise amplifier 4, carrier signals output by the phase-locked loop two are divided into two local oscillator signals by the two carrier driving branches, one local oscillator signal drives the I path of the I/Q mixer 5, the other local oscillator signal drives the Q path of the I/Q mixer 5 after being processed by phase shifting, and the output of the low noise amplifier 4 is subjected to frequency conversion processing by the I/Q mixer 5 and then is used as an input signal of a radar system baseband processing module. Furthermore, the receiving chain also comprises a duplexer 6 connected with the two outputs of the phase-locked loop for isolating the transmitting chain and the receiving chain, and the duplexer 6 receives the carrier signal of the two outputs of the phase-locked loop and feeds the carrier signal to the binary phase shift keying modulator of the transmitting chain and the I/Q mixer in the receiving chain respectively.
Referring to fig. 1, in the transmission chain, after a phase-locked loop generates a clock signal, a pseudo-random binary sequence is generated by a pseudo-random binary sequence generator, and the pseudo-random binary sequence can be used as the wideband excitation. Pseudo-random binary sequence modulation inHeart frequency off c On the carrier signal. Wherein the center frequency isf c Is generated by another phase locked loop. The pseudo-random binary sequence is modulated via a binary phase shift keying modulator and fed to a power amplifier 3 and is transmitted 1, most preferably by a transmitting antenna. The pseudo-random binary sequence has good autocorrelation performance and can be used as broadband excitation.
In a receiving chain, a receiving antenna 2 receives a signal reflected by a target, the signal is amplified by a low noise amplifier 4 and enters an I/Q mixer 5 for frequency conversion to intermediate frequency, and then the intermediate frequency is handed over to a baseband for signal processing. The phase locked loop two generates a carrier signal which is fed via a duplexer 6 to the binary phase shift keying modulator of the transmit chain and to the I/Q mixer 5 of the receive chain, respectively. The duplexer 6 can isolate the transmitting link from the receiving link, ensure the receiving and transmitting work simultaneously and avoid the mutual interference of two paths of signals.
In the transmit chain, a phase-locked loop outputs a signal off m (ii) a The pseudo-random binary sequence generator input signal isf m (ii) a The output binary sequence ism(t) (ii) a The binary phase shift keying modulator input signal ism(t)And the center frequency of the two outputs of the phase-locked loop isf c The output of which is fed into the power amplifier 3; the input signal of the power amplifier 3 iss TX (t)And finally transmits the signal to a target via a transmitting antenna 1s TX (t)After being transmitted by the transmitting antenna 1 and reaching the target object, a part of the transmitted signal is reflected back and received by the receiving antenna 2.
In the receiving chain, the receiving antenna 2 receives the signal reflected by the target object ass RX (t)The signal is amplified by a low noise amplifier 4 and then divided into two paths, which are fed into an I/Q two-path mixer 5 respectively. The second output center frequency of the phase-locked loop isf c After the carrier signal enters a receiving link, a duplexer 6 is connected with a binary phase shift keying modulator to modulate a pseudo-random binary sequence, the other path is divided into two paths, and one path is directly used as local oscillator signal excitation driveAnd one path of the I-path mixer is used as a local oscillation signal to excite and drive the Q-path mixer after being shifted by 90 degrees. The I/Q mixer 5 implements a frequency conversion function, and down-converts the signal transmitted from the low noise amplifier 4 into an intermediate frequency signal, which can be used for subsequent baseband signal processing in the radar system. Two paths of I/Q mixers are adopted in a receiving link, so that the image rejection performance of the intermediate frequency signal can be improved, and the subsequent baseband signal processing is facilitated.
In the embodiment of the scheme, the pseudo-random binary sequence is used as excitation, is not influenced by temperature, process and voltage change, and can be widely applied to radar sensing application requiring high reliability and high resolution.
The term "and/or" herein means that three relationships may exist. For example, a and/or B may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used in the description and in the claims, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not necessarily denote a limitation of quantity. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Exemplary embodiments of the present invention have been described in detail with reference to the preferred embodiments, however, it will be understood by those skilled in the art that various changes and modifications may be made to the specific embodiments described above and various combinations of the technical features and structures proposed by the present invention may be made without departing from the concept of the present invention, and the scope of the present invention is defined by the appended claims. The foregoing description of specific exemplary embodiments of the utility model is not intended to limit the utility model to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the utility model and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the utility model and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the utility model be defined by the claims and their equivalents.
Claims (3)
1. A pseudo-random noise radar integrated chip for a radar system for emergency rescue site target detection comprises a transceiving signal circuit module arranged on the radar system chip, and is characterized in that the transceiving signal circuit module comprises: the device comprises a transmitting link and a receiving link, wherein the transmitting link is arranged on a single chip and used for signal output and the receiving link is used for processing an echo signal and transmitting the echo signal to a baseband, and the transmitting link comprises: the system comprises a phase-locked loop I, a pseudo-random binary sequence generator, a binary phase shift keying modulator, a power amplifier and a transmitting antenna, wherein the phase-locked loop I is used for generating a transmitting link clock signal, the pseudo-random binary sequence generator is connected with the phase-locked loop I and is used for generating a broadband excitation pseudo-random binary sequence, the binary phase shift keying modulator is connected with the pseudo-random binary sequence generator and is used for modulating the pseudo-random binary sequence, the power amplifier is connected with the binary phase shift keying modulator and is used for amplifying the modulated sequence signal, and the transmitting antenna is connected with the power amplifier and is used for transmitting the amplified signal; the receiving chain comprises: the receiving antenna is used for receiving a target signal, the low-noise amplifier is connected with the receiving antenna and used for amplifying the received target signal, the second phase-locked loop is used for generating a carrier signal of a receiving link, and the I/Q mixer is connected with the second phase-locked loop and the low-noise amplifier and used for combining the carrier signal and performing frequency conversion processing on an output signal of the low-noise amplifier.
2. The pn radar integrated chip of claim 1, wherein the receive chain comprises: the low-noise amplifier comprises two frequency mixing branches connected with the low-noise amplifier and two carrier driving branches connected with a phase-locked loop II, wherein carrier signals output by the phase-locked loop II are divided into two local oscillator signals by the two carrier driving branches, one local oscillator signal drives an I path of an I/Q mixer, the other local oscillator signal drives a Q path of the I/Q mixer after being subjected to transposition processing, and the output of the low-noise amplifier is subjected to frequency conversion processing by the I/Q mixer and then serves as an input signal of a radar system baseband processing module.
3. The pseudonoise radar integrated chip of claim 1 or 2, wherein the receive chain further comprises a diplexer connected to the two outputs of the phase locked loop for isolating the transmit chain from the receive chain, the diplexer receiving the carrier signal from the two outputs of the phase locked loop and feeding the carrier signal to the binary phase shift keying modulator of the transmit chain and to the I/Q mixer of the receive chain, respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123288521.6U CN216870803U (en) | 2021-12-25 | 2021-12-25 | Pseudo-random noise radar integrated chip |
| PCT/CN2022/110890 WO2023115970A1 (en) | 2021-12-25 | 2022-08-08 | Pseudo-random noise radar integrated chip |
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| CN202123288521.6U CN216870803U (en) | 2021-12-25 | 2021-12-25 | Pseudo-random noise radar integrated chip |
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| WO2023115970A1 (en) * | 2021-12-25 | 2023-06-29 | 河南森源鸿马电动汽车有限公司 | Pseudo-random noise radar integrated chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7460055B2 (en) * | 2006-06-02 | 2008-12-02 | Panasonic Corporation | Radar apparatus |
| CN201259551Y (en) * | 2008-08-28 | 2009-06-17 | 阮树成 | Millimeter wave random bi-phase code phase and amplitude modulated multi-channel anti-collision radar for automobile |
| CN102162848B (en) * | 2010-12-07 | 2013-01-23 | 北京理工大学 | Automobile active anti-collision radar based on pseudorandom code and linear frequency modulated continuous wave |
| CN105549000A (en) * | 2015-12-07 | 2016-05-04 | 中国电子科技集团公司第五十研究所 | Usage method of harmonic radar with positioning function |
| WO2021168866A1 (en) * | 2020-02-29 | 2021-09-02 | 华为技术有限公司 | Anti-interference distance measuring device and method |
| CN213602633U (en) * | 2020-10-31 | 2021-07-02 | 河南森源鸿马电动汽车有限公司 | Radar integrated chip |
| CN216870803U (en) * | 2021-12-25 | 2022-07-01 | 河南森源鸿马电动汽车有限公司 | Pseudo-random noise radar integrated chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023115970A1 (en) * | 2021-12-25 | 2023-06-29 | 河南森源鸿马电动汽车有限公司 | Pseudo-random noise radar integrated chip |
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Denomination of utility model: Pseudo random noise radar integrated chip Granted publication date: 20220701 Pledgee: Zhengzhou Rural Commercial Bank Co.,Ltd. Pledgor: HENAN MA CHE-HUNG INDUSTRIAL Co.,Ltd. Registration number: Y2024980039888 |