CN216870739U - Chip testing flat cable and chip testing equipment - Google Patents
Chip testing flat cable and chip testing equipment Download PDFInfo
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- CN216870739U CN216870739U CN202220179694.XU CN202220179694U CN216870739U CN 216870739 U CN216870739 U CN 216870739U CN 202220179694 U CN202220179694 U CN 202220179694U CN 216870739 U CN216870739 U CN 216870739U
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Abstract
The application belongs to the technical field of chip testing, and provides a chip testing flat cable which comprises two PCB boards, wherein each PCB board comprises a plurality of signal transmission bonding pads, a plurality of grounding bonding pads and a plurality of pin arranging holes; a plurality of signal transmission lines respectively connected between the two PCB boards; each signal transmission line comprises a lead, an insulating layer sleeved outside the lead, a metal shielding layer sleeved outside the insulating layer and a wire sheath sleeved outside the metal shielding layer; the wires of the signal transmission lines are connected to the signal transmission bonding pads on the PCB, and the metal shielding layers of the signal transmission lines are connected to the grounding bonding pads on the PCB. The application also provides a chip testing device. The chip testing flat cable and the chip testing equipment solve the problem of signal interference between flat cables, and improve the accuracy of chip testing.
Description
Technical Field
The application relates to the technical field of chip testing, and particularly provides a chip testing flat cable and chip testing equipment.
Background
With the continuous development of the integrated circuit industry, the impact proportion of the FPGA (Field Programmable Gate Array) integrated circuit device (chip) in each industry is increasing. From the whole manufacturing process, the testing of the FPGA integrated circuit specifically includes design verification at a design stage, process detection at a wafer manufacturing stage, wafer testing before packaging, and finished product testing after packaging, and runs through the whole process of design, manufacturing, packaging, and application, thereby playing an important role in ensuring chip performance and improving operation efficiency of an industrial chain.
The wafer test (Chip bonding, also known as middle test) of the front section of the FPGA is used for testing a wafer after the completion of the substitute work, and aims to pick out a bad bare wafer (Die) before scribing and packaging so as to reduce the cost of packaging and Chip finished product test, and meanwhile, the qualification rate of a Die on the wafer, the exact position of a unqualified Die, the qualification rate of various types and the like are counted, so that the wafer manufacturing yield can be directly reflected, and the wafer manufacturing capability can be checked. The middle Test is to Test the chip (Die) after connecting a tester (Automatic Test Equipment, ATE), a Test load board (LoadBoard), and a probe card (ProbeCard), and the Test result is greatly affected by the environment.
The Final Test (Final Test) is to perform tests on electrical performance, functions and the like of a packaged single chip, and aims to screen defective products which do not meet the requirements of customers after packaging. The equipment and the jig related to the finished product test comprise a testing machine (ATE), a test load board (LoadBoard), a testing machine platform (handler) and the like.
For the accuracy of the test result, the requirements of the middle test and the finished product test on the tested hardware and environment are very strict, and for some products, the existing test connection environment cannot meet the test scheme conditions required by customers, for example, in the connection aspect of a tester and a pin card, the mutual interference among flat cables exists.
SUMMERY OF THE UTILITY MODEL
In view of this, the application provides a chip test winding displacement and chip test equipment, can solve the problem that the winding displacement that exists in the chip test process interferes with each other, promotes the accuracy of chip test.
A first aspect of the present application provides a chip test cable, including:
the PCB comprises two PCB boards, a plurality of grounding pads and a plurality of pin arranging holes, wherein each PCB board comprises a plurality of signal transmission pads, a plurality of grounding pads and a plurality of pin arranging holes;
the signal transmission lines are respectively connected between the two PCB boards; each signal transmission line comprises a lead, an insulating layer sleeved outside the lead, a metal shielding layer sleeved outside the insulating layer and a wire sheath sleeved outside the metal shielding layer;
the conducting wire of the signal transmission line is connected to the signal transmission pad on the PCB board, and the metal shielding layer of the signal transmission line is connected to the grounding pad on the PCB board.
In some embodiments, a female socket plug-in is further welded on each PCB, a plurality of pin headers are arranged on the female socket plug-in, and the pin headers are respectively inserted into the corresponding pin header holes.
In some embodiments, the number of the pin holes is M, the number of the signal transmission pads and the number of the ground pads are both N, and M is 2N;
the pin holes comprise N first pin holes electrically connected to the signal transmission bonding pad and N second pin holes electrically connected to the grounding bonding pad.
In some embodiments, the N first row of pinholes are arranged in a row, and the N second row of pinholes are arranged in a row and correspond to the N first row of pinholes respectively and are arranged at intervals.
In some embodiments, N signal transmission pads are arranged in a row, and N ground pads are arranged in a row and respectively correspond to and are spaced apart from N signal transmission pads.
In some embodiments, a protruding portion is arranged on one side of the PCB, and a fool-proof mark is arranged on the protruding portion.
In some embodiments, the chip test cable further comprises a winding wire wrapping the plurality of signal transmission lines.
In some embodiments, the wire is a stranded wire.
In some embodiments, the metallic shielding layer is a metallic mesh braid.
A second aspect of the present application provides a chip testing apparatus, which includes a testing device and the chip testing cable according to any one of the embodiments of the first aspect.
The chip testing flat cable comprises two PCBs (printed circuit boards) and a plurality of signal transmission lines, wherein the signal transmission lines are internally provided with wires and metal shielding layers insulated from the wires, the wires are connected with signal transmission pads on the PCBs, and the metal shielding layers are connected with grounding pads on the PCBs, so that the metal shielding layers can transmit external interference signals to corresponding grounding pads, the signal transmission lines can transmit correct electric signals to the signal transmission pads and further transmit the electric signals to corresponding flat pins, therefore, the chip testing flat cable solves the problem of mutual interference among the flat cables in chip testing, and the accuracy, stability and testing efficiency of the chip testing are improved. Meanwhile, the cost of the chip testing flat cable is low, the use is flexible, and the universality is high.
The chip testing equipment can connect the testing device and the probe card/testing load board by using the chip testing flat cable, so that the testing device is electrically connected with the chip to be tested, and the testing device is further used for completing the detection of the chip to be tested. Because the chip test flat cable can solve the problem of flat cable interference, the chip test equipment improves the accuracy of test results, reduces the cost and improves the test stability.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a chip test cable according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural view of a PCB board in the chip test cable shown in FIG. 1;
FIG. 3 is a side view of a signal transmission line in the chip test cable shown in FIG. 1;
fig. 4 is a schematic cross-sectional view of the signal transmission line shown in fig. 3.
The designations in the figures mean:
100. testing the flat cable by the chip;
10. a PCB board; 11. a signal transmission pad; 12. a ground pad; 13. arranging pin holes; 131. a first row of pinholes; 132. a second row of pinholes; 14. a boss portion; 15. a fool-proof mark;
20. a signal transmission line; 21. a wire; 22. an insulating layer; 23. a metal shielding layer; 24. and a wire sheath.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings, which are examples. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In order to explain the technical solutions described in the present application, the following description is made with reference to specific drawings and examples.
Embodiments of a first aspect of the present application provide a chip testing cable, which is used in a chip testing process. In the present embodiment, the chip test cable can be used for intermediate test or finished product test, but is not limited thereto.
Referring to fig. 1 and 2, the chip test cable 100 includes two PCB (printed Circuit board) boards 10 and a plurality of signal transmission lines 20 connected between the two PCB boards 10. Fig. 1 shows only two signal transmission lines 20, and the other signal transmission lines 20 are omitted.
Each PCB board 10 includes a plurality of signal transmission pads 11, a plurality of ground pads 12, and a plurality of pin holes 13. A plurality of signal transmission lines 20 are respectively connected between the two PCB boards 10.
Referring to fig. 3 and 4, each signal transmission line 20 includes a conductive wire 21, an insulating layer 22 disposed outside the conductive wire 21, a metal shielding layer 23 disposed outside the insulating layer 22, and a wire sheath 24 disposed outside the metal shielding layer 23.
The signal transmission line 20 is a shielding line having a shielding function, and transmits an electrical signal through the wire 21, and is resistant to electromagnetic interference by the metal shielding layer 23, and the insulating layer 22 plays an insulating protection role between the wire 21 and the metal shielding layer 23. The metal shielding layer 23 needs to be grounded, and an external interference signal can be guided to the ground by the metal shielding layer 23. Therefore, the signal transmission line 20 can utilize the reflection, absorption and skin effect of the metal shielding layer 23 to achieve the function of preventing electromagnetic interference and electromagnetic radiation.
Since each signal transmission line 20 is connected between two PCB boards 10, the wire 21 of each signal transmission line 20 is connected to the signal transmission pad 11 on the PCB board 10 and is electrically connected to the pin header in the corresponding pin header hole 13 through the internal routing of the PCB board 10 to transmit the correct electrical signal; the metal shield layer 23 of the signal transmission line 20 is connected to the ground pad 12 on the PCB board 10 to function as a ground.
The chip testing cable 100 is used according to the following principle:
when the chip is tested, one PCB board 10 is electrically connected to a testing device, and the other PCB board 10 is electrically connected to a probe card for middle test or a bullhorn seat on a test load board for finished product test, so that the testing device is connected to the chip to be tested, and the chip to be tested is tested by using the testing device. Because the wire 21 of the signal transmission line 20 is connected to the signal transmission pad 11 on the PCB 10, the metal shielding layer 23 of the signal transmission line 20 is connected to the ground pad 12 on the PCB, the signal transmission line 20 can be connected to the pin in the corresponding pin row 13 through the internal trace of the PCB 10, and the corresponding metal shielding layer 23 transmits the external interference signal to the corresponding ground pad 12, so as to achieve the purpose of signal stabilization.
The chip testing flat cable 100 comprises two PCBs 10 and a plurality of signal transmission lines 20, wherein the signal transmission lines 20 are provided with wires 21 and metal shielding layers 23 insulated from the wires 21, the wires 21 are connected with signal transmission pads 11 on the PCBs 10, and the metal shielding layers 23 are connected with grounding pads 12 on the PCBs 10, so that the metal shielding layers 23 can transmit external interference signals to the corresponding grounding pads 12, and the signal transmission lines 20 can transmit correct electric signals to the signal transmission pads 11 and further to corresponding pins, therefore, the chip testing flat cable 100 solves the problem of mutual interference among flat cables in chip testing, and improves accuracy, stability and testing efficiency of chip testing. Meanwhile, the chip testing flat cable 100 has the advantages of simple structure, low cost, flexible use, strong compatibility and simple user operation.
In some embodiments, each PCB 10 is further welded with a female socket connector (not shown), and the female socket connector is provided with a plurality of pin headers, and the pin headers are respectively inserted into the corresponding pin header holes 13. By providing the socket connector, the chip test harness 100 can be stably connected to a test apparatus, a probe card or a test load board through the socket connector.
In some embodiments, the number of pin headers 13 is M, the number of signal transmission pads 11 and the number of ground pads 12 are both N, and M is 2N. It is understood that M, N are all positive integers. For example, the number of pin headers 13 is 64, and the number of signal transmission pads 11 and ground pads 12 is 32; for another example, the number of pin headers 13 is 40, and the number of signal transmission pads 11 and ground pads 12 is 20, but not limited thereto.
In some embodiments, the plurality of pin holes 13 includes N first pin holes 131 electrically connected to the signal transmission pads 11 and N second pin holes 132 electrically connected to the ground pads 12. Thus, the number of the first row of pinholes 131 and the number of the second row of pinholes 132 are also N, the row pins in the N first row of pinholes 131 are electrically connected with the N signal transmission pads 11 in a one-to-one correspondence manner, and the row pins in the N second row of pinholes 132 are electrically connected with the N ground pads 12 in a one-to-one correspondence manner.
In some embodiments, the N first rows of pinholes 131 are arranged in a row, the N second rows of pinholes 132 are arranged in a row and respectively correspond to the N first rows of pinholes 131 and are arranged at intervals, that is, the row of pinholes 13 are arranged in two rows, so that the row of pinholes 13 can meet the requirement of testing, and the row of pinholes is conveniently connected.
In some embodiments, the N signal transmission pads 11 are arranged in a row, the N ground pads 12 are arranged in a row and correspond to the N signal transmission pads 11 respectively and are spaced apart from each other, so that two rows of adjacent pads are disposed on the PCB 10, one row of pads is the signal transmission pads 11, and the other row of pads is the ground pads 12, so as to facilitate the soldering of the metal shielding layer 23 of the signal transmission line 20 to the ground pads 12, and the wires 21 are soldered to the signal transmission pads 11, the chip test flat cable 100 is simple in structure and reasonable in layout.
In some embodiments, a protruding portion 14 is disposed on one side of the PCB board 10, and a fool-proof mark 15 is disposed on the protruding portion 14. For example, the fool-proof mark 15 is an arrow, but is not limited thereto. In this embodiment, the ground pad 12, the signal transmission pad 11, the first row of pin holes 131, and the second row of pin holes 132 are sequentially disposed on the PCB 10, that is, the second row of pin holes 132 is close to the edge of the PCB 10, and the protruding portion 14 is disposed on a side of the second row of pin holes 132 away from the first row of pin holes 131.
Through adopting above-mentioned technical scheme, through setting up bellying 14 and preventing slow-witted sign 15, can prevent that the chip test winding displacement 100 that the preparation was accomplished from inserting with ox horn seat and turning over, prevent installation direction mistake promptly, promoted the accuracy and the efficiency of software testing.
It is to be understood that the arrangement order of the ground pads 12, the signal transmission pads 11, the first row of pin holes 131, and the second row of pin holes 132 is not limited thereto, and for example, the ground pads 12 are disposed between the signal transmission pads 11 and the first row of pin holes 131.
In some embodiments, the chip test cable 100 further includes a winding wire (not shown) wrapping the plurality of signal transmission lines 20. It can be understood that the lengths of the plurality of signal transmission lines 20 are consistent, so as to avoid the problem of poor signal transmission consistency; the winding wire can be wound on the plurality of signal transmission lines 20 to relatively fix the plurality of signal transmission lines 20.
Optionally, the wire 21 is a stranded wire, that is, the wire 21 includes a plurality of stranded metal wires, and an electric wave radiated from each metal wire during transmission is cancelled by an electric wave emitted from another metal wire, so as to effectively reduce the degree of signal interference. Thus, the signal transmission line 20 can combine the balance principle of the twisted wire and the shielding effect of the metal shielding layer 23, and has better electromagnetic compatibility.
Optionally, the metal shielding layer 23 is a metal mesh braid. The metal shielding layer 23 wraps the outside of the lead 21, and has a good electromagnetic shielding effect. Further, the material of the metal mesh braid may be, but is not limited to, red copper or tin-plated copper.
In an embodiment, taking the 64PIN chip test strip 100 as an example, the length of the signal transmission line 20 is 0.8m, and the manufacturing process of the chip test strip 100 is as follows:
firstly, tin is coated on the metal shielding layers 23 and the conducting wires 21 at two ends of the signal transmission line 20; then, the soldered wires 21 are soldered one by one to the signal transmission pads 11 of the PCB board 10, and the metal shield layers 23 are soldered to the corresponding ground pads 12. It can be understood that both ends of the signal transmission line 20 are connected to the two PCB boards 10, respectively.
Then, the female socket plug-in is welded on the PCB 10, the pin headers on the female socket plug-in are inserted into the corresponding pin header holes 13 one by one, the female socket plug-in is fixed by heating the molten glue, and the plurality of signal transmission lines 20 are fixed by using the winding lines and the rolling strips, thereby completing the manufacturing process of the chip testing cable 100.
A second aspect of the present application provides a chip testing apparatus, which includes a testing device and a chip testing cable 100. The testing device can be a chip tester, a chip testing platform and the like.
Taking the middle test as an example, two ends of the chip testing cable 100 are respectively connected to the middle test device and the probe card; taking the finished product test as an example, two ends of the chip testing flat cable 100 are respectively connected to the finished product testing device and the fillet seat on the testing load board.
The chip testing equipment can connect the testing device and the probe card/test load board by using the chip testing flat cable 100, so that the testing device is electrically connected with the chip to be tested, and the testing device is further used for completing the detection of the chip to be tested. Because the chip test flat cable 100 can solve the problem of flat cable interference, the chip test equipment improves the accuracy of test results, reduces the cost and improves the test stability.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A chip test cable, comprising:
the PCB comprises two PCB boards, a plurality of grounding pads and a plurality of pin arranging holes, wherein each PCB board comprises a plurality of signal transmission pads, a plurality of grounding pads and a plurality of pin arranging holes;
the signal transmission lines are respectively connected between the two PCB boards; each signal transmission line comprises a lead, an insulating layer sleeved outside the lead, a metal shielding layer sleeved outside the insulating layer and a wire sheath sleeved outside the metal shielding layer;
the conducting wire of the signal transmission line is connected to the signal transmission pad on the PCB board, and the metal shielding layer of the signal transmission line is connected to the grounding pad on the PCB board.
2. The chip testing cable according to claim 1, wherein a female socket plug-in is further welded on each PCB, and a plurality of pins are disposed on the female socket plug-in and are respectively inserted into the corresponding pin holes.
3. The chip testing flex cable of claim 1, wherein the number of the pin array holes is M, the number of the signal transmission pads and the number of the grounding pads are both N, and M is 2N;
the pin holes comprise N first pin holes electrically connected to the signal transmission bonding pad and N second pin holes electrically connected to the grounding bonding pad.
4. The chip testing cable according to claim 3, wherein N first rows of pin holes are arranged in a row, and N second rows of pin holes are arranged in a row and respectively correspond to and are spaced apart from the N first rows of pin holes.
5. The chip test cable according to claim 3, wherein N signal transmission pads are arranged in a row, and N ground pads are arranged in a row and respectively correspond to and are spaced apart from N signal transmission pads.
6. The chip testing cable according to any one of claims 1-5, wherein a raised portion is provided on one side of the PCB, and a fool-proof mark is provided on the raised portion.
7. The chip test flex cable of any one of claims 1-5, wherein the chip test flex cable further comprises a wrapping wire wrapping a plurality of the signal transmission lines.
8. The chip test ribbon cable of any one of claims 1-5 wherein the wires are stranded wires.
9. The chip test ribbon cable of any one of claims 1-5, wherein the metallic shielding layer is a metallic mesh braid.
10. A chip testing apparatus comprising a testing device and a chip testing cable according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220179694.XU CN216870739U (en) | 2022-01-20 | 2022-01-20 | Chip testing flat cable and chip testing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220179694.XU CN216870739U (en) | 2022-01-20 | 2022-01-20 | Chip testing flat cable and chip testing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216870739U true CN216870739U (en) | 2022-07-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220179694.XU Active CN216870739U (en) | 2022-01-20 | 2022-01-20 | Chip testing flat cable and chip testing equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216870739U (en) |
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2022
- 2022-01-20 CN CN202220179694.XU patent/CN216870739U/en active Active
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