CN216793269U

CN216793269U - Display panel and display device

Info

Publication number: CN216793269U
Application number: CN202022387138.5U
Authority: CN
Inventors: 袁永; 李杰良
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2022-06-21
Anticipated expiration: 2030-10-23

Abstract

The embodiment of the utility model discloses a display panel and a display device, wherein the display panel comprises a pixel circuit and a light-emitting element; the pixel circuit comprises a driving module, a data writing module, a light-emitting control module and a bias module; the driving module is used for providing driving current for the light-emitting element and comprises a driving transistor; the data writing module is connected with the source electrode of the driving transistor and used for selectively providing a data signal for the driving module; the light-emitting control module is used for selectively allowing the light-emitting element to enter a light-emitting stage; the control end of the light-emitting control module is connected to the control signal line and used for receiving a light-emitting control signal, and the bias module is connected between the drain electrode of the driving transistor and the light-emitting control signal line; the working process of the pixel circuit comprises a bias stage, and in the bias stage, the bias module adjusts the drain electrode potential of the driving transistor according to the light-emitting control signal. The utility model is beneficial to adjusting the threshold voltage offset of the driving transistor.

Description

Display panel and display device

Technical Field

Embodiments of the present invention relate to display technologies, and in particular, to a display panel and a display device.

Background

In a display panel, a pixel circuit provides a driving current required for displaying for a light emitting element of the display panel and controls whether the light emitting element enters a light emitting stage, which is an indispensable element in most self-luminous display panels.

However, in the conventional display panel, as the use time increases, the internal characteristics of the driving transistor in the pixel circuit are changed slowly, so that the threshold voltage of the driving transistor is shifted, thereby affecting the overall characteristics of the driving transistor and further affecting the display uniformity.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a display panel, a driving method thereof and a display device, which aim to solve the problem of threshold voltage drift of the conventional driving transistor.

An embodiment of the present invention provides a display panel, including:

a pixel circuit and a light emitting element;

the pixel circuit comprises a driving module, a data writing module, a light-emitting control module and a bias module;

the driving module comprises a driving transistor;

the data writing module is connected to the source electrode of the driving transistor; wherein,

the control end of the light-emitting control module is connected to a light-emitting control signal line and used for receiving a light-emitting control signal, and the bias module is connected between the drain electrode of the driving transistor and the light-emitting control signal line;

the working process of the pixel circuit comprises a bias stage, and in the bias stage, the bias module adjusts the drain electrode potential of the driving transistor according to the light-emitting control signal.

Based on the same utility model concept, the embodiment of the utility model also provides a display device, which comprises the display panel.

In an embodiment of the present invention, the pixel circuit includes a bias module, and the bias module is connected between the light emission control signal line and the drain of the driving transistor to adjust a drain potential of the driving transistor, so as to improve a potential difference between a gate potential of the driving transistor and the drain potential of the driving transistor. The known pixel circuit comprises at least one non-bias phase, when the driving current is generated in the driving transistor, the gate potential of the driving transistor may be larger than the drain potential of the driving transistor, which causes the I-V curve of the driving transistor to shift, and causes the threshold voltage of the driving transistor to shift. In the biasing stage, the offset phenomenon of an I-V curve of the driving transistor in the non-biasing stage can be balanced by adjusting the grid potential and the drain potential of the driving transistor, the threshold voltage drift phenomenon of the driving transistor is weakened, and the display uniformity of the display panel is ensured.

Drawings

To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description, although being some specific embodiments of the present invention, can be extended and extended to other structures and drawings by those skilled in the art according to the basic concepts of the device structure, the driving method and the manufacturing method disclosed and suggested by the various embodiments of the present invention, without making sure that these should be within the scope of the claims of the present invention.

Fig. 1 is a schematic diagram of a pixel circuit of a first display panel according to an embodiment of the utility model;

FIG. 2 is a schematic diagram of a pixel circuit of a second display panel according to an embodiment of the utility model;

FIG. 3 is a schematic diagram of a pixel circuit of a third display panel according to an embodiment of the utility model;

FIG. 4 is a schematic diagram of a first timing sequence of operation of the pixel circuit;

FIG. 5 is a diagram illustrating a second timing of operation of the pixel circuit;

FIG. 6 is a diagram illustrating a third timing of operation of the pixel circuit;

FIG. 7 is a schematic diagram of a fourth timing of operation of the pixel circuit;

FIG. 8 is a schematic diagram of a pixel circuit of a fourth display panel according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a fifth operation timing sequence of the pixel circuit;

FIG. 10 is a diagram illustrating a sixth timing of operation of the pixel circuit;

FIG. 11 is a schematic diagram of a pixel circuit of a fifth display panel according to an embodiment of the utility model;

FIG. 12 is a schematic diagram of a pixel circuit of a sixth display panel according to an embodiment of the utility model;

FIG. 13 is a schematic diagram of a pixel circuit of a seventh display panel according to an embodiment of the utility model;

fig. 14 is a partial cross-sectional view of a pixel circuit according to an embodiment of the utility model;

fig. 15 is a schematic diagram of a top-down structure of a pixel circuit according to an embodiment of the utility model;

fig. 16 is a schematic diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described through embodiments with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the basic idea disclosed and suggested by the embodiments of the present invention, are within the scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic diagram of a pixel circuit of a first display panel according to an embodiment of the present invention. The display panel provided by the embodiment comprises: a pixel circuit 10 and a light emitting element 20; the pixel circuit 10 includes a driving module 11, a light-emitting control module 12, a bias module 13, and a data writing module 14; the driving module 11 is used for providing a driving current for the light emitting element 20, and the driving module 11 includes a driving transistor T0; the lighting control module 12 is used for selectively allowing the lighting element 20 to enter a lighting phase; the data writing module 14 is connected to the source of the driving transistor T0, and is configured to selectively provide a data signal Vdata for the driving module 11; the control terminal of the light-emitting control module 12 is connected to the light-emitting control signal line for receiving the light-emitting control signal EM, wherein the bias module 13 is connected between the drain of the driving transistor T0 and the light-emitting control signal line, the working process of the pixel circuit 10 includes a bias phase, and in the bias phase, the bias module 13 is configured to adjust the drain potential of the driving transistor T0 according to the light-emitting control signal EM.

In this embodiment, the pixel circuit 10 includes a driving module 11, an output end, i.e., a drain, of the driving module 11 is electrically connected to the light emitting element 20, the driving module 11 includes a driving transistor T0, the driving module 11 provides a driving current for the light emitting element 20 after the driving transistor T0 is turned on, and the on/off of the driving transistor T0 controls the magnitude of the driving current provided to the light emitting element 20. The source of the driving transistor T0 is electrically connected to the input terminal of the driving module 11, and the drain of the driving transistor T0 is electrically connected to the output terminal of the driving module 11. In other embodiments, the drain of the driving transistor is electrically connected to the input terminal of the driving module, and the source of the driving transistor is electrically connected to the output terminal of the driving module.

The pixel circuit 10 includes a data writing module 14, a source of the data writing module 14 is connected to a data signal terminal for receiving a data signal Vdata, a drain of the data writing module 14 is connected to a source of the driving transistor T0, a control terminal of the data writing module 14 is connected to a first scanning signal line for receiving a first scanning signal S1, and the first scanning signal S1 controls on and off of the data writing module 14; optionally, the data writing module includes a second transistor T2, a source of the second transistor T2 is connected to the data signal terminal, a drain of the second transistor T2 is connected to the source of the driving transistor T0, and a gate of the second transistor T2 is connected to the first scan signal line.

The pixel circuit 10 includes a light-emitting control module 12, a control end of the light-emitting control module 12 is connected to a light-emitting control signal line EM, when the light-emitting control signal line EM outputs an effective pulse, the light-emitting control module 12 is turned on, the light-emitting element 20 is driven to enter a light-emitting stage, and then a driving current flows into the light-emitting element 20; when the emission control signal line EM outputs the ineffective pulse, the emission control module 12 is turned off, and the path through which the driving current flows into the light emitting element 20 is disconnected.

The pixel circuit 10 includes a bias block 13, and the bias block 13 is connected between the drain of the driving transistor T0 and the emission control signal line EM. The bias block 13 is used to pull down or raise the potential of the drain of the driving transistor T0. Taking the driving transistor T0 as PMOS as an example, the emission control signal line EM receives a high level signal, and the bias block 13 raises the drain voltage of the driving transistor T0. In other embodiments, the driving transistor may be selected to be an NMOS, the emission control signal line EM receives a low level signal, and the bias module 13 pulls down the drain voltage of the driving transistor T0. The following embodiments are described by taking the driving transistor as a PMOS as an example.

In a non-bias stage such as a light-emitting stage of a pixel circuit, the gate potential of a driving transistor may be larger than the drain potential of the driving transistor, and long-term arrangement of the pixel circuit causes the polarization of ions in the driving transistor, so that a built-in electric field is formed in the driving transistor, and an Id-Vg curve deviates, so that the threshold voltage of the driving transistor is continuously increased, thereby affecting the driving current flowing into a light-emitting element and further affecting the display uniformity. In this embodiment, in the working process of the pixel circuit 10, the drain voltage of the driving transistor T0 is adjusted by the bias module 13, so that the degree of polarization of the internal ions of the driving transistor T0 can be weakened, and the threshold voltage drift of the driving transistor T0 can be compensated.

The working process of the selectable pixel circuit further comprises at least one non-bias stage; in the bias stage, the gate voltage of the driving transistor is Vg1, the source voltage is Vs1, and the drain voltage is Vd 1; in the non-bias stage, the gate voltage of the driving transistor is Vg2, the source voltage is Vs2, and the drain voltage is Vd 2; wherein,

|Vg1-Vd1|＜|Vg2-Vd2|

in this case, by reducing the potential difference between the gate potential of the driving transistor T0 and the drain potential of the driving transistor T0, the phenomenon of the threshold voltage shift caused by the potential difference between the gate potential and the drain potential of the driving transistor T0 in the non-bias stage can be alleviated.

Additionally, in some embodiments of the present embodiment,

(Vg1-Vs1) × (Vg2-Vs2) <0, or,

(Vg1-Vd1)×(Vg2-Vd2)＜0。

in the working process of the pixel circuit, if the grid voltage and the drain voltage of the driving transistor satisfy (Vg1-Vd1) × (Vg2-Vd2) < 0. In the non-bias stage, the gate voltage of the driving transistor in the pixel circuit is greater than the drain voltage of the driving transistor, namely Vg2> Vd2, and Vg2-Vd2> 0. In the offset phase, a data signal is written into the drain of the driving transistor, so that the gate voltage of the driving transistor is smaller than the drain voltage of the driving transistor, namely Vg1< Vd1, and Vg1-Vd1< 0. Then (Vg1-Vd1) × (Vg2-Vd2) < 0.

In other embodiments, during operation of the selectable pixel circuit, if the source and drain of the driving transistor are interchanged, the gate voltage and the source voltage of the driving transistor satisfy (Vg1-Vs1) × (Vg2-Vs2) < 0. In the non-bias stage, the gate voltage of the driving transistor in the pixel circuit is greater than the source voltage of the driving transistor, namely Vg2> Vs2, and Vg2-Vs2> 0. In the bias phase, a data signal is written into the source electrode of the driving transistor, so that the gate voltage of the driving transistor is smaller than the source electrode voltage of the driving transistor, namely Vg1< Vs1, and Vg1-Vs1< 0. Then (Vg1-Vs1) × (Vg2-Vs2) < 0.

In addition, optionally, in this embodiment, because the time of the non-bias phase, such as the light-emitting phase of the display panel, is relatively long, the threshold voltage offset of the non-bias phase is to be fully balanced in the bias phase, and it is avoided that the bias phase takes too long, Vd1-Vg 1> Vg2-Vd2>0 may be set, so that Vd1-Vg1 of the bias phase is large enough, the bias phase can achieve the desired bias effect in as soon as possible, in other embodiments, if the source and the drain of the driving transistor are switched, Vs1-Vg 1> Vg2-Vs2>0 may also be set, depending on the specific circuit situation.

Optionally, in other embodiments of this embodiment, the time length of the bias phase is t1, and the time length of the non-bias phase is t2, wherein,

(| -Vg 1-Vs1 | -Vg 2-Vs2 |) × (t1-t2) <0, or,

(∣Vg1-Vd1∣﹣∣Vg2-Vd2∣)×(t1-t2)＜0。

in this embodiment, in the offset phase, the drain voltage of the driving transistor is made larger than the gate voltage of the driving transistor, i.e., Vg1-Vd1< 0. In the non-bias stage, the gate voltage of the driving transistor is greater than the drain voltage of the driving transistor, namely Vg2-Vd2> 0. In the process of biasing the driving transistor, if the bias voltage is large, the bias time can be reduced appropriately, and if the bias voltage is small, the bias time can be extended appropriately.

Based on this, if | Vg1-Vd1 | -Vg 2-Vd2 | >0 indicates that the offset voltage is larger, the duration of the offset stage can be reduced appropriately, i.e. t1< t2, so as to reduce the deviation of the threshold voltage in the offset stage and the non-offset stage. If | Vg1-Vd1 | -Vg 2-Vd2 | <0, which indicates that the offset voltage is smaller, the duration of the offset phase can be extended appropriately, i.e., t1> t2, so as to reduce the deviation of the threshold voltage in the offset phase and the non-offset phase.

In other embodiments, if the source and drain of the driving transistor are interchanged, the gate and drain of the driving transistor in the biased and non-biased periods satisfy (| Vg1-Vs1 | -Vg 2-Vs2 |) × (t1-t2) <0, which can reduce the threshold voltage deviation in the non-biased period.

It should be noted that the biased phase and the unbiased phase in the above embodiments, especially with respect to the comparison of the time lengths, generally refer to a continuous and uninterrupted biased phase and a comparison between a continuous and uninterrupted unbiased phase.

The optional unbiased phase is a light emitting phase of the display panel. Illustratively, in a light emitting period, the source voltage of the driving transistor T0 is 4.6V, the gate voltage is 3V, the drain voltage is 1V, the gate voltage of the driving transistor is greater than the drain voltage of the driving transistor, and by the biasing period, the driving transistor is biased, and the threshold voltage shift of the driving transistor in the light emitting period can be compensated.

In this embodiment, the transistor in the light-emitting control module 12 and the driving transistor T0 are the same type of transistor, and as if they are PMOS transistors, in the bias stage, the light-emitting control signal line receives a high-level signal, and under the action of the bias module 13, the high-level signal raises the voltage of the drain of the driving transistor T0; alternatively, the transistor in the light emission control module 12 and the driving transistor T0 are both NMOS transistors; in the bias stage, the light-emitting control signal line receives a low-level signal, and the low-level signal pulls down the voltage at the drain of the driving transistor T0 under the action of the bias module. Under the action of the bias module 13, the adjustment of the drain potential of the driving transistor T0 by the emission control signal EM is realized.

Optionally, as shown in fig. 1, the pixel circuit 10 further includes a compensation module 15, where the compensation module 15 is connected between the gate of the driving transistor T0 and the drain of the driving transistor T0, and is used for compensating the threshold voltage of the driving transistor T0; the control terminal of the compensation module 15 is connected to the second scan signal line for receiving the second scan signal S2, and the second scan signal S2 controls the compensation module 15 to be turned on or off; wherein the compensation module 15 remains switched off during the biasing phase. Since the offset phase is used to adjust the potential difference between the gate potential and the drain potential of the driving transistor T0, and the compensation module 15 is connected between the gate and the drain of the driving transistor T0, if the compensation module 15 is turned on, the gate potential and the drain potential are substantially equal, and therefore, the compensation module 15 is kept turned off during the offset phase. Further optionally, the compensation module 15 includes a third transistor T3, a source of the third transistor T3 is connected to the drain of the driving transistor T0, a drain of the third transistor T3 is connected to the gate of the driving transistor T0, and a gate of the third transistor T3 is connected to the second scan signal line, and is configured to receive the second scan signal S2.

Optionally, referring to fig. 2 and fig. 3, fig. 2 is a schematic diagram of a pixel circuit of a second display panel provided in an embodiment of the present invention, and fig. 3 is a schematic diagram of a pixel circuit of a third display panel provided in an embodiment of the present invention, in this embodiment, optionally, the pixel circuit 10 further includes a reset module 16; optionally, as shown in fig. 2, the reset module 16 is connected between the reset signal terminal and the drain of the driving transistor T0, and is configured to provide a reset signal Vref for the gate of the driving transistor T0; alternatively, as shown in fig. 3, the reset module 16 is connected between the reset signal terminal and the gate of the driving transistor T0, and is configured to provide the reset signal Vref to the gate of the driving transistor T0.

Taking the pixel circuit shown in fig. 2 as an example, referring to fig. 4 to 6, fig. 4 is a schematic diagram of a first operation timing of the pixel circuit, fig. 5 is a schematic diagram of a second operation timing of the pixel circuit, and fig. 6 is a schematic diagram of a third operation timing of the pixel circuit, it should be noted that terms such as "first" and the like appearing herein and in the following text are only named for distinguishing different schematic diagrams, and are not to be understood as having a sorting relationship between the schematic diagrams. In addition, here, optionally, the third transistor T3 and the fifth transistor T5 are NMOS transistors, the other transistors are PMOS transistors, and the NMOS transistors may be oxide semiconductor transistors.

As shown in fig. 4-6, the working process of the pixel circuit in one frame of time of the selectable display panel includes a pre-stage and a light-emitting stage; the pre-stage of the pixel circuit comprises a bias stage in at least one frame time.

In this embodiment, optionally, the pre-stage includes a bias stage and an intermediate stage; in the biasing phase, the compensation module 15 is switched off; in the intermediate phase, the compensation module 15 is switched on; the biasing phase may be performed before the intermediate phase, as shown in fig. 4, or after the intermediate phase, as shown in fig. 5, and the intermediate phase may also be located in between any two adjacent biasing phases, as shown in fig. 6, when the pre-set phase comprises at least 2 biasing phases. As will be described in further detail below.

Optionally, in this embodiment, one data writing period of the display panel includes S frames of refreshing pictures, including a data writing frame and a holding frame, where S > 0; wherein the data writing frame comprises a data writing stage; the retention frame does not include a data write phase.

Optionally, in this embodiment, with reference to fig. 2 and fig. 4, the data writing frame includes an offset phase; the intermediate stage comprises a reset stage and a data write-in stage in sequence; in the reset phase, the reset module 16 and the compensation module 15 are turned on, and the gate of the driving transistor T0 receives a reset signal to be reset; in the data writing phase, the data writing module 14, the driving module 11 and the compensation module 15 are all turned on, and the data signal is written into the gate of the driving transistor T0. Since the data writing frame includes the data writing phase and the gate of the driving transistor T0 needs to be reset before the data writing phase, the previous phase of the data writing frame needs to include the reset phase and the data writing phase, and the compensation module can be kept off during other time of the previous phase, at this time, the drain potential of the driving transistor T0 is raised under the control of the emission control signal EM and the bias module 13.

Optionally, in the case that the data writing frame includes a bias phase, a reset phase may be further included before the bias phase, and then the bias phase is entered. Since the purpose of the bias phase is to adjust the potential difference between the gate and the drain of the driving transistor T0, the reset phase is performed before the bias phase, for example, the driving transistor is a PMOS transistor, and the gate of the driving transistor can be reset by providing a low-level signal in the reset phase; then, thereafter, in the bias phase, the compensation block is turned off, and the drain potential of the driving transistor is raised under the action of the emission control signal EM and the bias block 15. The process realizes two-aspect adjustment of the grid potential and the drain potential of the driving transistor, thereby improving the bias effect.

Referring to fig. 7, fig. 7 is a schematic diagram of a fourth operation timing sequence of the pixel circuit, wherein the holding frame includes a bias phase, the intermediate phase includes a reset phase, in the reset phase, the reset module 16 and the compensation module 15 are turned on, and the gate of the driving transistor T0 receives the reset signal Vref for resetting. The retention frame does not contain a data writing phase, and therefore, if the leading phase of the retention frame includes a bias phase, in conjunction with the pixel circuit in fig. 2, if the retention frame also includes a reset phase, the intermediate phase includes the reset phase, optionally, the reset phase is performed before the bias phase, or may be performed after the bias phase, and when the leading phase includes at least 2 bias phases, the reset phase may also be performed between any two adjacent intermediate phases. Optionally, the reset phase is performed before the bias phase, and since the purpose of the bias phase is to adjust the potential difference between the gate and the drain of the driving transistor T0, the reset phase is performed before the bias phase, for example, if the driving transistor is a PMOS transistor, the gate of the driving transistor may be provided with a low-level signal to perform reset in the reset phase; then, thereafter, in the bias phase, the compensation block is turned off, and the drain potential of the driving transistor is raised under the action of the emission control signal EM and the bias block 15. The process realizes two-aspect adjustment of the grid potential and the drain potential of the driving transistor, thereby improving the bias effect.

Optionally, one data writing period of the display panel includes S frames of refreshing pictures, including a data writing frame and a holding frame, where S > 0; wherein the data writing frame comprises a data writing stage; the retention frame does not include a data write phase.

Taking the pixel circuit shown in fig. 3 as an example, referring to fig. 8, fig. 8 is a schematic diagram of a pixel circuit of a fourth display panel according to an embodiment of the present invention, where, optionally, the third transistor T3 and the fifth transistor T5 are NMOS transistors, the other transistors are PMOS transistors, and the NMOS transistors may be oxide semiconductor transistors.

Optionally, as shown in fig. 8, in the embodiment, the data writing frame includes a bias phase, the intermediate phase includes a data writing phase, in the data writing phase, the data writing module 14, the driving module 11, and the compensation module 15 are all turned on, and the data signal Vdata is written into the gate of the driving transistor T0. In the pixel circuit shown in fig. 3, the reset block 16 is connected to the gate of the driving transistor, so that the compensation block 15 does not need to be turned on during the reset phase, and therefore, the emission control signal EM and the bias block 13 can also control the drain potential of the driving transistor T0 during the reset phase, that is, during the reset phase, the bias phase can also be performed, and therefore, in this embodiment, the intermediate phase may only include the data writing phase. As mentioned before, if the pre-phase also comprises a reset phase, the bias phase overlaps with at least part of the time period of the reset phase.

Optionally, in this embodiment, the time length of the intermediate stage is shorter than that of the bias stage, because as described in the foregoing embodiment, the intermediate stage mainly includes the reset stage or the data write stage, and the reset stage and the data write stage are both used to write the relevant signal into the node, and it is not necessary to take too long time. Thus, the time length of the intermediate phase may be shorter than the time length of the bias phase.

In addition, optionally, in this embodiment, the pre-stage includes N offset stages, where N is greater than or equal to 1; fig. 6 and 8 show the case where the offset phase includes 2 offset phases, and in other embodiments, there may be 3 or more than 3 offset phases. As shown in fig. 6 and 8, the bias phase includes a first bias phase and a second bias phase; the pre-stage includes a first bias stage, an intermediate stage, and a second bias stage in sequence. Alternatively, the time length of the intermediate stage is shorter than the time lengths of the first bias stage and the second bias stage, respectively, and as the intermediate stage aims to write a signal at the corresponding node and the bias stage aims to cancel the threshold voltage shift of the non-bias stage driving transistor, as described above, generally, the time length of the intermediate stage may be set shorter than the time lengths of the first bias stage and the second bias stage, respectively, so as to sufficiently achieve the bias effect.

In addition, in some embodiments, the time length of the first bias stage and the second bias stage is optionally equal, in other embodiments, the time length of at least one of the first bias stage and the second bias stage is optionally longer than that of the other one, in this case, the bias stage with the longer time length is optionally a main bias stage, and the other bias stages are optionally auxiliary bias stages, wherein the main bias stage is a main bias stage, but in order to prevent the bias effect of the main bias stage from being insufficient, the auxiliary bias stage may be performed to supplement the bias effect. In some cases, optionally, the first bias phase has a longer time duration than the second bias phase, and in other cases, optionally, the first bias phase has a shorter time duration than the second bias phase.

For the case that the pre-stage includes N offset stages, where N is greater than or equal to 1, optionally, the time lengths of any two offset stages in the pre-stage may not be equal, for example, the time length of the first offset stage is greater than the time lengths of the other offset stages, it can be understood that the first offset stage is a main offset stage and mainly takes charge of canceling the threshold voltage deviation of the non-offset stage, but in order to prevent the incomplete offset effect of the first offset stage, other complementary offset stages may be set to sufficiently complement the offset effect. In addition, the time length of the offset stage in the front stage can be reduced in sequence, so that the situation that the offset effect of the previous offset stage is insufficient can be supplemented by the later offset stage. Based on the same concept, it can also be set reversely, for example, the time length of the last bias stage is longer than that of the other bias stages, and particularly, in the front stage, the time lengths of the bias stages are sequentially increased, and the bias effect can be gradually realized by the bias stages with gradually increasing time lengths one by one. In addition, by combining the above concepts, the time length of one middle bias stage may be longer than that of the first bias stage and also longer than that of the second bias stage, that is, the final bias stage is used as a supplement, and the middle bias stage is the main bias stage.

Both the foregoing embodiments and fig. 4 to 8 show the case where the pre-stage includes the intermediate stage, but in other embodiments of the present embodiment, the pre-stage may not include the intermediate stage.

Referring to fig. 9 in conjunction with the pixel circuit in fig. 3, fig. 9 is a schematic diagram of a fifth operation timing sequence of the pixel circuit, and fig. 9 is a schematic diagram of an operation timing sequence of a holding frame, wherein the holding frame includes a bias phase, wherein the pre-phase further includes a reset phase, and in the reset phase, the gate of the driving transistor T0 receives a reset signal Vref to reset; wherein the reset phase overlaps with at least a portion of the time period of the bias phase. In the retention frame, a data writing phase is not required, and in the pixel circuit shown in fig. 3, since the reset module 16 is connected to the gate of the driving transistor T0, the compensation module 15 is not required to be turned on in the reset phase, so that the reset phase and the bias phase can be performed simultaneously for at least a part of the time period, and thus, by adjusting the gate potential of the driving transistor T0 on the one hand and the drain potential of the driving transistor T0 on the other hand, simultaneous adjustment of the gate potential and the drain potential is realized, which is favorable for improving the potential difference between the gate potential and the drain potential and improving the bias effect.

In addition, referring to fig. 10 in conjunction with the pixel circuit in fig. 3, fig. 10 is a schematic diagram of a sixth operation timing sequence of the pixel circuit, and fig. 10 shows an operation timing sequence of a hold frame, where the hold frame includes a bias phase, and a preceding phase of the hold frame is the bias phase. Since the holding frame does not include the data writing phase, if the holding frame does not set the reset phase, the compensation module 15 does not need to be turned on in the holding frame, and the emission control signal EM and the bias module 13 can both control the drain potential of the driving transistor T0 at the entire time of the pre-stage, so the pre-stage is the bias stage.

In the present embodiment, as shown in fig. 1 to fig. 3, the light emission control module 12 includes a first light emission control module 12a and a second light emission control module 12 b; the first lighting control module 12a is connected between the first power signal terminal and the source of the driving transistor T0, and is configured to selectively provide the first power signal PVDD to the driving module 11; the second light emission control module 12b is connected between the drain of the driving transistor T0 and the light emitting element 20, for selectively allowing the driving current to flow into the light emitting element 20.

Optionally, the first light emitting control module 12a includes a fourth transistor T4, a source of the fourth transistor T4 is connected to the first power signal terminal, a drain of the fourth transistor T4 is connected to the source of the driving transistor T0, and a gate of the fourth transistor T4 is connected to the light emitting control signal terminal. The second light emission control module 12b includes a first transistor T1, wherein a source of the first transistor T1 is connected to a drain of the driving transistor T0, a drain is connected to the light emitting element 20, and a gate is connected to a light emission control signal terminal.

Alternatively, in this embodiment, as shown in fig. 1 to fig. 3, the control end of the first light-emitting control module 12a and the control end of the second light-emitting control module 12b may be connected to the same light-emitting control signal line. This is suitable for the case where the first light-emitting control module 12a and the second light-emitting control module 12b can be turned on and off at the same time.

In addition, optionally, in this embodiment, referring to fig. 11, fig. 11 is a schematic diagram of a pixel circuit of a fifth display panel provided in the embodiment of the present invention, where a control end of the first lighting control module 12a is connected to the first lighting control signal line, and is configured to receive the first lighting control signal EM 1; the control end of the second light emission control module 12b is connected to the second light emission control signal line, and is configured to receive a second light emission control signal EM 2; the bias module 13 may be connected to the first light emission control signal line, and may also be connected to the second light emission control signal line; when the bias module 13 is connected to the second light emitting control signal line, since the first light emitting control module 12a is connected between the first power signal terminal and the source of the driving transistor T0 and the second light emitting control module 12b is connected between the drain of the driving transistor T0 and the light emitting element 20, generally, the drain of the driving transistor T0 is sufficiently prevented from being disconnected from the light emitting element 20 to ensure that the light emitting element 20 does not emit light in the non-light emitting stage. In the non-emission phase, the second emission control module 12b is kept off, and if the first transistor T1 is a PMOS transistor, the second emission control signal EM2 is kept as a high-level signal in the pre-phase, so that the bias phase is set to be connected to the second emission control signal line, which can ensure that the time length of the bias phase in the pre-phase is long, thereby contributing to the improvement of the bias effect.

As shown in fig. 11, in this embodiment, optionally, the bias module 13 includes a first capacitor C1, a first plate of the first capacitor C1 is connected to the drain of the driving transistor T0, and a second plate of the first capacitor C1 is connected to the light-emitting control signal line; in the bias phase, the light emission control signal EM2 on the light emission control signal line raises or pulls down the voltage of the drain of the driving transistor T0 under the action of the first capacitor C1. Since the capacitor has the function of charging and discharging, the voltage of the drain of the driving transistor T0 can be controlled by the emission control signal EM2 by providing the capacitor, and at the same time, the capacitor does not need to be controlled by applying an additional signal, so that the operation of the circuit can be simplified by providing the bias module 13 as the first capacitor C1.

In addition, optionally, in this embodiment, the pixel circuit further includes a second capacitor C2, the second capacitor C2 includes a third plate connected to the first power signal terminal, the second capacitor C2 includes a fourth plate connected to the gate of the driving transistor T0, and the second capacitor C2 is configured to store the data signal Vdata transmitted to the gate of the driving transistor T0; in this embodiment, the capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2, or equal to the capacitance of the second capacitor C2. In some embodiments, the capacitance of the first capacitor C1 is smaller than the capacitance of the second capacitor C2, and since the second capacitor functions to store the data signal Vdata written into the gate of the driving transistor T0, and the data signal Vdata written into the gate of the driving transistor T0 is one of the determining factors for determining the driving current generated in the driving transistor T0 during the light-emitting period, it is necessary to fully store the signal of the driving transistor T0 during the data writing period through a capacitor with strong storage capacity; the bias stage is now to adjust the potential difference between the gate potential and the drain potential of the driving transistor T0, so that the storage capacity of the second capacitor is required to be larger than that of the first capacitor from the viewpoint of accurately storing data, and therefore, the capacitance value of the first capacitor C1 is set to be smaller than that of the second capacitor C2 in this embodiment.

Further, optionally, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 satisfy: C2X 1/8 is not less than C1 is not less than C2X 1/4. The utility model discloses people discover, when C2 is multiplied by 1/8 is not less than C1 is not less than C2 is multiplied by 1/4, the capacitance value of first electric capacity C1 can satisfy the demand in biasing stage, and can avoid because of first electric capacity C1's capacitance value is too big, and lead to pixel circuit's load to increase, influence the signal transmission's of luminous control signal line problem.

Referring to fig. 12, fig. 12 is a schematic diagram of a pixel circuit of a sixth display panel according to an embodiment of the present invention, and optionally, in this embodiment, the bias module further includes a gate module 18, where the gate module 18 is connected between the light-emitting control signal line and the first capacitor C1, and is used for selectively allowing the light-emitting control signal EM to control a potential of the drain of the driving transistor T0; the gating module 18 includes a first bias transistor T8, a source of the first bias transistor T8 is connected to the light emission control signal line, and a drain of the first bias transistor T0 is connected to the first capacitor C1; the gate of the first bias transistor T8 is connected to the first bias signal line for receiving the first bias signal ST 1. Since only the first capacitor C1 is included between the light emission control signal line and the drain of the driving transistor T0, there may be a situation where the entering and ending of the bias phase cannot be controlled at any time, as long as the compensation module 15 is turned off in the pre-stage, i.e., enters the bias phase, and in some cases, the gating module 18 is provided to better control the beginning and ending of the bias phase, so that the beginning and ending of the bias phase can be controlled by the first bias signal ST 1.

Referring to fig. 13, fig. 13 is a schematic diagram of a pixel circuit of a seventh display panel according to an embodiment of the present invention, and optionally, in this embodiment, the bias module 13 further includes a second bias transistor T9, a source of the second bias transistor T9 is connected to the light emission control signal line, a drain of the second bias transistor T9 is connected to the drain of the driving transistor T0, a gate of the second bias transistor T9 is connected to the second bias control signal line, and is configured to receive the second bias control signal ST2, during the bias phase, the second bias transistor T9 is turned on, and the light emission control signal EM is transmitted to the drain of the driving transistor T0. In this case, by providing the second bias transistor T9, the second bias transistor T9 can be turned on at the beginning of the bias phase and the second bias transistor T9 can be turned off at the end of the bias phase, thereby achieving control of the start time and the end time of the bias phase.

Optionally, as shown in fig. 1 to 3 and fig. 11 to 13, in this embodiment, the pixel circuit further includes an initialization module 17, where the initialization module 17 is connected between the initialization signal terminal and the light emitting element 20, and is configured to selectively provide an initialization signal Vini to the light emitting element 20; the control terminal of the initialization module 17 is connected to the fourth scan signal line, and is configured to receive the fourth scan signal S4.

Optionally, the initialization block 17 includes a seventh transistor T7, a source of the seventh transistor T7 is connected to the initialization signal terminal, a drain of the seventh transistor T7 is connected to the light emitting element 20, and a gate of the seventh transistor T7 is connected to the fourth scan signal line.

When the initialization module 17 is turned on, the pixel circuit 10 enters the initialization phase, in this embodiment, optionally, the time of the bias phase and the time of the initialization phase do not overlap, and in some embodiments, the time of the bias phase and the time of the initialization phase may partially overlap, and since the display panel is required to not emit light in the bias phase, but a certain leakage current may exist in the transistor, if the light emitting element 20 does not receive the initialization signal Vini, the light emitting element 20 may have a risk of being stolen during the bias phase, and during the bias phase, the light emitting element 20 is initialized, which may further ensure that the light emitting element does not emit light. Further, the initialization phase end time may be earlier than the offset phase, the same as the offset phase, or later than the offset phase, which may be the same. The design can be flexibly carried out according to specific circuit conditions.

Alternatively, in this embodiment, it may be configured that the first bias control signal ST1 and the fourth scan signal S4 are the same signal; alternatively, the second bias control signal ST2 is the same signal as the fourth scan signal S4; in this embodiment, the fourth scan signal S4 controls the start and the end of the initialization phase, as mentioned above, in the offset phase, whether the initialization phase is performed or not may be performed, that is, the fourth scan signal S4 is multiplexed as the first offset control signal SL1 or the second offset control signal SL2, so that it is avoided that too many driving signals are introduced into the display panel, which may cause a larger workload of the display panel and a larger frame of the display panel.

In the present application, some of the optional T0, T1, T2, T3, T4, T5, and T6 may be PMOS using polysilicon as an active layer, and some may be NMOS using an oxide semiconductor as an active layer. For example, T3 and T5 are NMOS transistors, and the other transistors are PMOS transistors. It is understood that the active pulse of the scan signal of the NMOS transistor is at a high level and the active pulse of the scan signal of the PMOS transistor is at a low level. It should be noted that the pixel circuits shown in fig. 1 to 13 are only an example, and the structure of the pixel circuit in the embodiment of the present invention is not limited thereto.

Optionally, the width-to-length ratio of the channel region of the NMOS transistor is greater than the width-to-length ratio of the channel region of the PMOS transistor, and therefore in the present application, if the NMOS transistor mainly functions as a switching transistor, a fast response capability is required, and a transistor with a large width-to-length ratio has a shorter channel region length, which is beneficial to improving the response capability of the transistor.

In addition, in the present application, the four scan signals S1, S2, S3, and S4 may be different signals, and in some specific cases, if the timing sequence satisfies a certain condition, at least two of the four signals S1, S2, S3, and S4 may also be the same signal, for example, when T5 and T7 are the same type of transistor, for example, if both T5 and T7 are PMOS or NMOS, S3 and S4 may be the same signal. For another example, when T3 and T7 are the same type of transistors, such as both PMOS and both NMOS, S2 and S4 can be the same signal, which depends on the specific circuit structure and timing, and this embodiment is not limited thereto.

Referring to fig. 14 and fig. 15, fig. 14 is a schematic partial cross-sectional view of a pixel circuit provided in an embodiment of the present invention, and fig. 15 is a schematic top-view structural view of a pixel circuit provided in an embodiment of the present invention, where the pixel circuit includes two types of transistors: a transistor Tm and a transistor Tn, wherein a gate of the transistor Tm is located on the first metal layer M1, a source and a drain of the transistor Tm are both located on the fourth metal layer M4, the transistor Tm includes a first active layer w1, and is located between the first metal layer M1 and the substrate base plate; the transistor Tn comprises a first gate and a second gate, wherein the first gate is located on the second metal layer M2, the second gate is located on the third metal layer M3, the transistor Tn comprises a second active layer w2 and is located between the second metal layer M2 and the third metal layer M3, and the source and the drain of the transistor Tn are located on the fourth metal layer M4. The transistor Tm may be a low-temperature polysilicon transistor, and the transistor Tn may be an oxide semiconductor transistor.

The pixel circuit comprises a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 comprises a first polar plate C11 and a second polar plate C12, the second capacitor C2 comprises a third polar plate C23 and a fourth polar plate C24, and the first polar plate and the second polar plate are positioned on any two of six film layers of a first active layer w1, a first metal layer M1, a second metal layer M2, a second active layer w2, a third metal layer M3 and a fourth metal layer; the third plate and the fourth plate are located in any two of the six film layers of the first active layer w1, the first metal layer M1, the second metal layer M2, the second active layer w2, the third metal layer M3 and the fourth metal layer M4.

In some cases, the first plate and the third plate are located in the same layer, and the second plate and the fourth plate are located in the same layer, in which case, the area of the first plate is smaller than that of the third plate, and the area of the second plate is smaller than that of the fourth plate, so as to achieve the purpose that the capacitance value of the first capacitor C1 is smaller than that of the second capacitor C2.

In some cases, the first plate and the third plate are located in the same layer, and the second plate and the fourth plate are located in different layers, optionally, the distance between the first plate and the second plate is greater than the distance between the third plate and the fourth plate, so that the capacitance value of the first capacitor C1 is smaller than that of the second capacitor C2; in this case, optionally, the first plate and the third plate are located on the first metal layer M1, the fourth plate is located on the second metal layer M2, and the second metal layer is located on the second active layer, or the third metal layer M3, or the fourth metal layer M4.

In some cases, the first electrode plate, the second electrode plate, the third electrode plate and the fourth electrode plate are located in different film layers, and the specific location thereof may be located in any one of the six film layers of the first active layer w1, the first metal layer M1, the second metal layer M2, the second active layer w2, the third metal layer M3 and the fourth metal layer M4, which are within the protection scope of this case.

Optionally, a first insulating layer is included between the first plate and the second plate, and a second insulating layer is included between the third plate and the fourth plate, wherein a dielectric constant of the first insulating layer is smaller than a dielectric constant of the second insulating layer, so that a capacitance value of the first capacitor C1 is smaller than a capacitance value of the second capacitor C2. In addition, optionally, when the driving transistor is a PMOS transistor, the transistor Tm may be a driving transistor, and at this time, the hydrogen content of the second insulating layer is greater than that of the first insulating layer, because in this embodiment, the second capacitor C2 is a storage capacitor in the pixel circuit, and the second capacitor C2 generally overlaps with the driving transistor in the direction perpendicular to the surface of the display panel, and the driving transistor is in a top-gate structure, so that the second capacitor C2 is generally located on the side of the first active layer w1 facing away from the substrate, in particular, the third plate C23 of the second capacitor C2 may be multiplexed with the gate of the transistor Tm, and the fourth plate may be located on the second metal layer M2 and overlaps with the gate of the transistor Tm. At this time, the driving transistor is a PMOS transistor, and optionally a low temperature polysilicon transistor, and an active layer of the low temperature polysilicon transistor needs to be hydrogenated, so that a hydrogen content of a film layer around the low temperature polysilicon transistor is higher, and therefore, in this embodiment, a hydrogen content of the second insulating layer is greater than a hydrogen content of the first insulating layer.

Optionally, the oxygen content in the first insulating layer is greater than that in the second insulating layer, and since the first capacitor C1 is smaller than the second capacitor C2, in some cases, the thickness of the first insulating layer is greater than that of the second insulating layer, at least one of the first plate and the second plate of the first capacitor C2 is closer to the active layer of the transistor Tn, i.e., the active layer of the oxide semiconductor transistor, than the third plate and the fourth plate, while in order to ensure the normal function of the oxide semiconductor transistor, the hydrogen content in the film around the oxide semiconductor active layer is smaller, and the oxygen content is relatively higher, so in this case, the oxygen content in the first insulating layer is greater than that in the second insulating layer.

In an embodiment of the present invention, the pixel circuit includes a bias module connected between the light emission control signal line and the drain of the driving transistor to adjust a drain potential of the driving transistor, so as to improve a potential difference between a gate potential of the driving transistor and the drain potential of the driving transistor. The pixel circuit comprises at least one non-bias stage, when the driving current is generated in the driving transistor, the gate potential of the driving transistor is possibly larger than the drain potential of the driving transistor, so that the I-V curve of the driving transistor is shifted, and the threshold voltage of the driving transistor is shifted. In the biasing stage, the offset phenomenon of an I-V curve of the driving transistor in the non-biasing stage can be balanced by adjusting the grid potential and the drain potential of the driving transistor, the threshold voltage drift phenomenon of the driving transistor is weakened, and the display uniformity of the display panel is ensured.

Based on the same utility model concept, the embodiment of the utility model also provides a display device, which comprises the display panel as described in any of the above embodiments. The display panel can be selected to be an organic light emitting display panel or a micro LED display panel.

Referring to fig. 16, fig. 16 is a schematic diagram of a display device according to an embodiment of the present invention, wherein the display device can be applied to an electronic device 200 such as a smart phone and a tablet computer. It can be understood that the above embodiments only provide some examples of the pixel circuit structure and the driving method of the pixel circuit, and the display panel further includes other structures, which are not described in detail herein.

It is to be noted that the foregoing description is only exemplary of the utility model and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, comprising:

a pixel circuit and a light emitting element;

the driving module comprises a driving transistor;

2. The display panel according to claim 1,

the pixel circuit further comprises a compensation module;

the compensation module is connected between the grid electrode of the driving transistor and the drain electrode of the driving transistor and is used for compensating the threshold voltage of the driving transistor; wherein,

during the bias phase, the compensation module remains off.

3. The display panel according to claim 1,

the pixel circuit further comprises a reset module;

the reset module is connected between a reset signal end and the drain electrode of the driving transistor and used for providing a reset signal for the grid electrode of the driving transistor.

4. The display panel according to claim 1,

the pixel circuit further comprises a reset module;

the reset module is connected between a reset signal end and the grid of the driving transistor and used for providing a reset signal for the grid of the driving transistor.

5. The display panel according to claim 1,

the light-emitting control module comprises a first light-emitting control module and a second light-emitting control module;

the first light-emitting control module is connected between a first power signal end and the source electrode of the driving transistor and used for selectively providing a first power signal for the driving module;

the second light emitting control module is connected between the drain of the driving transistor and the light emitting element, and is used for selectively allowing the driving current to flow into the light emitting element.

6. The display panel according to claim 5,

the control end of the first light-emitting control module and the control end of the second light-emitting control module are connected to the same light-emitting control signal line.

7. The display panel according to claim 5,

the control end of the first light-emitting control module is connected to the first light-emitting control signal line and used for receiving a first light-emitting control signal;

the control end of the second light-emitting control module is connected to a second light-emitting control signal line and used for receiving a second light-emitting control signal;

the bias module is connected to the second light emission control signal line.

8. The display panel according to claim 1,

the bias module comprises a first capacitor, a first plate of the first capacitor is connected to the drain electrode of the driving transistor, and a second plate of the first capacitor is connected to the light-emitting control signal line;

in the bias stage, under the action of the first capacitor, the light-emitting control signal on the light-emitting control signal line raises or pulls down the voltage of the drain electrode of the driving transistor.

9. The display panel according to claim 8,

the pixel circuit further comprises a second capacitor, wherein the second capacitor comprises a third polar plate connected to a first power supply signal end, and the second capacitor comprises a fourth polar plate connected to the grid electrode of the driving transistor and used for storing a data signal transmitted to the grid electrode of the driving transistor; wherein,

the capacitance value of the first capacitor is smaller than that of the second capacitor.

10. The display panel according to claim 9,

the capacitance value of the first capacitor is C1, the capacitance value of the second capacitor is C2, wherein,

C2×1/8≤C1≤C2×1/4。

11. the display panel according to claim 8,

the bias module further comprises a gating module, wherein the gating module is connected between the light-emitting control signal line and the first capacitor and used for selectively allowing the light-emitting control signal to control the potential of the drain electrode of the driving transistor; wherein,

the gating module comprises a first bias transistor, the source electrode of the first bias transistor is connected to the light-emitting control signal line, and the drain electrode of the first bias transistor is connected to the first capacitor;

the gate of the first bias transistor is connected to a first bias signal line for receiving a first bias control signal.

12. The display panel according to claim 1,

the bias module comprises a second bias transistor, the source electrode of the second bias transistor is connected to the light-emitting control signal line, the drain electrode of the second bias transistor is connected to the drain electrode of the driving transistor, and the grid electrode of the second bias transistor is connected to a second bias control signal line and used for receiving a second bias control signal;

in the bias stage, the second bias transistor is turned on, and the light emission control signal is transmitted to the drain of the driving transistor.

13. The display panel according to claim 11 or 12,

the pixel circuit further comprises an initialization module;

the initialization module is connected between an initialization signal end and the light-emitting element and used for selectively providing an initialization signal for the light-emitting element; wherein,

the control end of the initialization module is connected to the fourth scanning signal line and used for receiving a fourth scanning signal; wherein,

the first bias control signal and the fourth scanning signal are the same signal; or,

the second bias control signal is the same signal as the fourth scan signal.

14. A display device characterized by comprising the display panel according to any one of claims 1 to 13.