CN216817787U

CN216817787U - Display panel and display device

Info

Publication number: CN216817787U
Application number: CN202022297255.2U
Authority: CN
Inventors: 赖青俊; 朱绎桦; 安平
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-10-15
Filing date: 2020-10-15
Publication date: 2022-06-24
Anticipated expiration: 2030-10-15

Abstract

The embodiment of the utility model discloses a display panel and a display device, wherein the display panel comprises: a pixel circuit and a light-emitting element; the pixel circuit comprises a light-emitting control module, a driving module and a compensation module; the light-emitting control module comprises a first light-emitting control module, and the first light-emitting control module is used for selectively providing a first power supply signal for the driving module; the driving module is used for providing driving current for the light-emitting element and comprises a driving transistor; the compensation module is used for compensating the threshold voltage of the driving transistor; the working process of the pixel circuit comprises a light-emitting stage and a bias stage, wherein in the bias stage, the first light-emitting control module and the driving module are started, the compensation module is turned off, the driving transistor and the light-emitting element are disconnected, and a first power supply signal is written into the drain electrode of the driving transistor by the source electrode of the driving transistor and is used for adjusting the bias state of the driving transistor. The embodiment of the utility model weakens the threshold voltage drift of the driving transistor.

Description

Display panel and display device

Technical Field

The embodiment of the utility model relates to the technical field of display, in particular to a display panel and a display device.

Background

In a display panel, a pixel circuit provides a driving current required for displaying for a light emitting element of the display panel and controls whether the light emitting element enters a light emitting stage, which is an indispensable element in most self-luminous display panels.

However, in the conventional display panel, as the use time increases, the internal characteristics of the driving transistor in the pixel circuit are changed slowly, so that the threshold voltage of the driving transistor is shifted, thereby affecting the overall characteristics of the driving transistor and further affecting the display uniformity.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present invention provide a display panel and a display device to improve the problem of threshold voltage drift of the conventional driving transistor.

An aspect of an embodiment of the present invention provides a display panel, including:

a pixel circuit and a light emitting element;

the pixel circuit comprises a light-emitting control module, a driving module and a compensation module;

the light-emitting control module comprises a first light-emitting control module which is connected between a first power signal end and a source electrode of the driving transistor, and the first power signal end provides the first power signal;

the driving module comprises a driving transistor;

the compensation module is connected between the grid electrode of the driving transistor and the drain electrode of the driving transistor;

the pixel circuit includes a light emission phase and a bias phase, wherein,

in the light-emitting stage, the first light-emitting control module is started, and the driving transistor is conducted with the light-emitting element;

in the bias stage, the first light emitting control module and the driving module are turned on, the compensation module is turned off, the driving transistor and the light emitting element are disconnected, and the first power supply signal is written into the drain electrode of the driving transistor.

Another aspect of an embodiment of the present invention provides a display panel, including:

a pixel circuit and a light emitting element;

the light-emitting control module comprises a first light-emitting control module which is used for selectively providing a first power supply signal for the driving module;

the driving module is used for providing driving current for the light-emitting element and comprises a driving transistor;

the compensation module is used for compensating the threshold voltage of the driving transistor;

the operation of the pixel circuit comprises a light emission phase and a bias phase, wherein,

in the bias stage, the first light emitting control module and the driving module are turned on, the compensation module is turned off, the driving transistor and the light emitting element are disconnected, and the first power signal is written into the drain of the driving transistor and used for adjusting the bias state of the driving transistor.

Based on the same utility model concept, the embodiment of the utility model also provides a display device, which comprises the display panel.

In the embodiment of the utility model, the working process of the pixel circuit comprises a bias stage, in the bias stage, the first light-emitting control module and the driving module are started, the compensation module is turned off, and the first power supply signal is written into the drain electrode of the driving transistor through the started first light-emitting control module and the started driving module so as to adjust the potential of the drain electrode of the driving transistor and improve the potential difference between the grid potential of the driving transistor and the drain electrode potential of the driving transistor. The known pixel circuit comprises at least one non-bias phase, when the driving current is generated in the driving transistor, the gate potential of the driving transistor may be larger than the drain potential of the driving transistor, which causes the I-V curve of the driving transistor to shift, and causes the threshold voltage of the driving transistor to shift. In the biasing stage, the offset phenomenon of an I-V curve of the driving transistor in the non-biasing stage can be balanced by adjusting the grid potential and the drain potential of the driving transistor, the threshold voltage drift phenomenon of the driving transistor is weakened, and the display uniformity of the display panel is ensured.

Drawings

To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description, although being some specific embodiments of the present invention, can be extended and extended to other structures and drawings by those skilled in the art according to the basic concepts of the device structure, the driving method and the manufacturing method disclosed and suggested by the various embodiments of the present invention, without making sure that these should be within the scope of the claims of the present invention.

Fig. 1 is a schematic diagram of a pixel circuit of a first display panel according to an embodiment of the utility model;

FIG. 2 is a schematic diagram of the drive transistor Id-Vg curve drift;

FIG. 3 is a schematic diagram of a pixel circuit of a second display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a pixel circuit of a third display panel according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a pixel circuit of a fourth display panel according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a pixel circuit of a fifth display panel according to an embodiment of the utility model;

FIG. 7 is a schematic diagram of a pixel circuit of a sixth display panel according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a first timing sequence of operation of the pixel circuit;

FIG. 9 is a diagram illustrating a second timing of operation of the pixel circuit;

FIG. 10 is a diagram illustrating a third timing of operation of the pixel circuit;

FIG. 11 is a schematic diagram of a fourth timing sequence for operation of the pixel circuit;

FIG. 12 is a diagram illustrating a fifth operation timing sequence of the pixel circuit;

FIG. 13 is a diagram illustrating a sixth timing of operation of the pixel circuit;

FIG. 14 is a diagram illustrating a seventh timing sequence of the pixel circuit;

FIG. 15 is a diagram illustrating an eighth timing sequence of operation of the pixel circuit;

fig. 16 is a diagram showing a ninth operation timing of the pixel circuit;

fig. 17 is a diagram showing a tenth operation timing of the pixel circuit;

fig. 18 is a diagram showing an eleventh operation timing of the pixel circuit;

FIG. 19 is a diagram illustrating a twelfth operational timing sequence of the pixel circuit;

fig. 20 is a schematic diagram of a thirteenth operation timing sequence of the pixel circuit;

FIG. 21 is a diagram showing a fourteenth operation timing of the pixel circuit;

fig. 22 is a schematic diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described through embodiments with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the basic idea disclosed and suggested by the embodiments of the present invention, are within the scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic diagram of a pixel circuit of a first display panel according to an embodiment of the present invention. The display panel provided by the embodiment comprises: a pixel circuit 10 and a light emitting element 20; the pixel circuit 10 includes a light emission control module, a driving module 12, and a compensation module 13; the lighting control module comprises a first lighting control module 11, wherein the first lighting control module 11 is configured to selectively provide a first power signal PVDD to the driving module 12; the driving module 12 is used for providing a driving current for the light emitting element 20, and the driving module 12 includes a driving transistor T0; the compensation module 13 is used for compensating the threshold voltage of the driving transistor T0; the working process of the pixel circuit 10 includes a light-emitting phase and a bias phase, wherein in the light-emitting phase, the first light-emitting control module 11 is turned on, and the driving transistor T0 is conducted with the light-emitting element 20; in the bias phase, the first light emitting control module 11 and the driving module 12 are turned on, the compensation module 13 is turned off, the driving transistor T0 and the light emitting element 20 are disconnected, and the first power signal PVDD is written from the source of the driving transistor T0 to the drain of the driving transistor T0 for adjusting the bias state of the driving transistor T0.

It should be noted that fig. 1 only schematically illustrates the key structures in the above embodiment, and does not include all the structures operated by the circuit, and the complete circuit structure is gradually shown in the following with the description of the present embodiment.

Note that the terms "first display panel" and "first operation timing" are used herein only for distinguishing different schematic diagrams, and should not be construed as a certain ordering relationship between the schematic diagrams.

In this embodiment, the pixel circuit 10 includes a first light emitting control module 11, an input terminal of the first light emitting control module 11 receives the first power signal PVDD, a control terminal of the first light emitting control module 11 receives the first light emitting control signal EM1, and an output terminal of the first light emitting control module 11 is electrically connected to an input terminal of the driving module 12. The first lighting control signal EM1 received by the pixel circuit 10 is a pulse signal, and an active pulse of the first lighting control signal EM1 controls the conduction of the transmission path between the input terminal and the output terminal of the first lighting control module 11 to provide the first power supply signal PVDD to the driving module 12; the inactive pulse of the first lighting control signal EM1 controls the transmission path of the input and output terminals of the first lighting control module 11 to be turned off. Thus, the first lighting control module 11 selectively provides the first power signal PVDD to the driving module 12 under the control of the first lighting control signal EM 1.

In this embodiment, the first lighting control module 11 is connected between a first power signal terminal and a source of the driving transistor T0, where the first power signal terminal is used to provide a first power signal PVDD; the compensation module 13 is connected between the gate of the driving transistor T0 and the drain of the driving transistor T0.

The pixel circuit 10 includes a driving module 12, an output terminal of the driving module 12 is electrically connected to the light emitting device 20, the driving module 12 includes a driving transistor T0, and the driving module 12 provides a driving current for the light emitting device 20 after the driving transistor T0 is turned on. The source of the driving transistor T0 is electrically connected to the input terminal of the driving module 12, and the drain of the driving transistor T0 is electrically connected to the output terminal of the driving module 12. In other embodiments, the drain of the driving transistor is electrically connected to the input terminal of the driving module, and the source of the driving transistor is electrically connected to the output terminal of the driving module.

The pixel circuit 10 includes a compensation module 13, and the compensation module 13 is used for compensating the threshold voltage of the driving transistor T0. A first pole of the compensation module 13 is electrically connected to the output end of the driving module 12, a control end of the compensation module 13 receives the scan signal S3, and a second pole of the compensation module 13 is electrically connected to the control end of the driving module 12. The scanning signal S3 received by the pixel circuit 10 is a pulse signal, and the effective pulse of the scanning signal S3 controls the conduction of the transmission paths of the first and second poles of the compensation module 13 to adjust the voltage between the control terminal and the output terminal of the driving module 12; the inactive pulse of the scan signal S3 controls the transmission path of the first and second poles of the compensation module 13 to be turned off. Therefore, the scan signal S3 controls the compensation module 13 to turn on, which can be used to compensate the threshold voltage of the driving transistor T0.

The working process of the pixel circuit 10 includes a light-emitting phase, in which the first light-emitting control signal EM1 outputs an active pulse signal to turn on the first light-emitting control module 11, and the driving transistor T0 is turned on with the light-emitting element 20, so that a driving current flows into the light-emitting element 20 to cause it to emit light. In a non-bias stage such as a light-emitting stage of a pixel circuit, a gate potential of a driving transistor of the pixel circuit may be greater than a drain potential of the driving transistor, and long-term arrangement of the pixel circuit may cause ion polarization in the driving transistor, so that a built-in electric field is formed in the driving transistor, which causes a threshold voltage of the driving transistor to be continuously increased, referring to fig. 2, fig. 2 is a schematic diagram of Id-Vg curve drift of the driving transistor, as shown in fig. 2, an Id-Vg curve is shifted, and a threshold voltage is shifted, so that stability of the driving transistor is affected, and display uniformity is affected.

Referring to fig. 3, fig. 3 is a schematic diagram of a pixel circuit of a second display panel according to an embodiment of the present invention, in the embodiment, an offset phase is added in an operation process of the pixel circuit 10, in the offset phase, the first light-emitting control module 11 and the driving module 12 are turned on, and the compensation module 13 is turned off, so that the first power signal PVDD is written into the drain of the driving transistor T0 through the first light-emitting control module 11 via the source of the driving transistor T0 to increase the drain potential of the driving transistor T0, and a potential difference between the gate potential and the drain potential of the driving transistor T0 is adjusted to implement voltage offset between the gate and the drain of the driving transistor T0, so as to weaken a degree of polarization of ions inside the driving transistor T0, further weaken a threshold voltage drift of the driving transistor T0, and improve display uniformity.

In the embodiment of the present invention, the working process of the pixel circuit includes a light emitting phase and a bias phase, as shown in fig. 3, in the bias phase, the first light emitting control module and the driving module are turned on, the compensation module is turned off, and the driving transistor and the light emitting element are disconnected from each other, so that the first power signal is written into the source of the driving transistor through the turned-on first light emitting control module and is written into the drain of the driving transistor from the source of the driving transistor to adjust the potential of the drain of the driving transistor, and thus the threshold voltage of the driving transistor is reduced by biasing the gate and drain voltages of the driving transistor. In a bias stage such as a light-emitting stage of a pixel circuit, there may be a case where a gate potential of a driving transistor is greater than a drain potential of the driving transistor, resulting in a threshold voltage shift of the driving transistor. The voltage between the grid electrode and the drain electrode of the bias driving transistor in the bias stage can balance the drift of the threshold voltage of the driving transistor in the light-emitting stage, improve the offset phenomenon of the Id-Vg curve and ensure the display uniformity of the display panel.

The optional light emission control module further includes a second light emission control module 14, the second light emission control module 14 being configured to selectively allow the driving current to flow into the light emitting element 20; in the bias phase, the second lighting control module 14 is turned off; in the lighting phase, the second lighting control module 14 is turned on.

In this embodiment, an input terminal of the second light-emitting control module 14 is connected to the output terminal of the driving module 12, an output terminal of the second light-emitting control module 14 is connected to the light-emitting element 20, and a control terminal of the second light-emitting control module 14 receives the second light-emitting control signal EM 2. The second emission control signal EM2 is a pulse signal, and the effective pulse output by the second emission control signal EM2 controls the conduction of the transmission path between the input terminal and the output terminal of the second emission control module 14, so as to allow the driving current to flow into the light emitting element 20; the inactive pulse output by the second emission control signal EM2 controls the transmission path of the input and output terminals of the second emission control module 14 to be turned off.

In the bias phase, the first power signal PVDD needs to be written into the drain of the driving transistor T0 to bias the gate voltage and the drain voltage of the driving transistor, so in the bias phase, the second light emission control module 14 is turned off to avoid the influence of the first power signal PVDD on the display effect of the display panel due to the driving of the light emitting element 20 by the second light emission control module 14. In the light emitting stage, the light emitting element 20 needs to emit light, and the second light emitting control module 14 is turned on to allow the driving current to flow into the light emitting element 20 to enable the light emitting element to emit light, thereby ensuring the normal light emission of the display panel.

The optional first lighting control module 11 includes a first transistor T1, a source of the first transistor T1 is configured to receive the first power signal PVDD, and a drain of the first transistor T1 is connected to a source of the driving transistor T0; the compensation module 13 includes a second transistor T2, a source of the second transistor T2 is connected to the drain of the driving transistor T0, and a drain of the second transistor T2 is connected to the gate of the driving transistor T0; the second light emission control module 14 includes a third transistor T3, a source of the third transistor T3 is connected to the drain of the driving transistor T0, and a drain of the third transistor T3 is connected to the light emitting element 20. A gate of the first transistor T1 receives the first light emission control signal EM1, and a gate of the third transistor T3 receives the second light emission control signal EM 2. The gate of the second transistor T2 receives the scan signal S3.

The control end of the optional first lighting control module 11 is connected to the first lighting control signal line EM1, and is configured to receive the first lighting control signal EM 1; the control end of the second light emission control module 14 is connected to the second light emission control signal line EM2, and is configured to receive the second light emission control signal EM 2. Here, EM1 represents the first light emission control signal line and the first light emission control signal transmitted therein, and EM2 represents the second light emission control signal line and the second light emission control signal transmitted therein.

In general, the width of the first emission control signal line EM1 may be equal to the width of the second emission control signal line EM 2. In some embodiments, the width of the first emission control signal line EM1 may be selected to be greater than the width of the second emission control signal line EM 2. The first light-emitting control signal line EM1 outputs an effective pulse in both the bias phase and the light-emitting phase to turn on the first transistor T1, and the second light-emitting control signal line EM2 outputs an effective pulse in the light-emitting phase, so that the signal transmission operating time of the first light-emitting control signal line EM1 is longer than that of the second light-emitting control signal line EM2, and therefore the transmission impedance of the first light-emitting control signal in the first light-emitting control signal line can be reduced by increasing the width of the first light-emitting control signal line, the transmission loss of the first light-emitting control signal line EM1 is reduced, and the influence of the loss of the first light-emitting control signal line on bias or light emission over a long-time accumulation is avoided.

Optionally, in this embodiment, the pixel circuit 10 further includes a reset module 17, and the reset module 17 is configured to provide a reset signal Vref to the gate of the driving transistor T0 to reset the gate of the driving transistor T0. The control terminal of the reset module 17 is configured to receive a first scan signal S1, and the first scan signal S1 provides an effective pulse to the pixel circuit 10, so that the reset module 17 is turned on.

Optionally, the reset module 17 includes a seventh transistor T7. The source of the seventh transistor T7 receives the reset signal Vref, the drain of the seventh transistor T7 is electrically connected to the gate or drain of the driving transistor T0, and the gate of the seventh transistor T7 receives the scan signal S1.

Alternatively, as shown in fig. 3, the reset module 17 is connected between the reset signal terminal and the gate of the driving transistor T0, and when the reset module 17 is turned on, the reset signal Vref is applied to the gate of the driving transistor T0 through the reset module 17.

In addition, referring to fig. 4, fig. 4 is a schematic diagram of a pixel circuit of a third display panel according to an embodiment of the utility model, wherein the reset module 17 is connected between a reset signal terminal and a drain of the driving transistor T0, and when the reset module 17 and the compensation module 13 are turned on simultaneously, the reset signal Vref is applied to a gate of the driving transistor T0 through the reset module 17 and the compensation module 13.

Referring to fig. 5, fig. 5 is a schematic diagram of a pixel circuit of a fourth display panel according to an embodiment of the present invention, where the optional first light-emitting control module 11 includes a first sub light-emitting control module 11a and a second sub light-emitting control module 11b, and the first sub light-emitting control module 11a and the second sub light-emitting control module 11b are connected in parallel between the first power signal terminal PVDD and the driving module 12; in the bias phase, the second sub-lighting control module 11b is turned off, and the first sub-lighting control module 11a is turned on. In the bias stage, the first power signal PVDD output from the first power signal terminal is written into the drain of the driving transistor T0 through the turned-on first sub-lighting control module 11a and the driving module 12, so as to bias the driving transistor T0.

The control terminals of the optional second light-emitting control module 14 and the second sub light-emitting control module 11b are both connected to the third light-emitting control signal line EM3, and are configured to receive a third light-emitting control signal. In the bias phase, the third emission control signal EM3 outputs an inactive pulse signal to turn off both the second emission control module 14 and the second sub-emission control module 11b, so as to prevent the driving current from flowing into the light emitting device 20, and the first power signal PVDD is written into the drain of the driving transistor T0 through the turned-on first sub-emission control module 11a and the turned-on driving module 12. In the light emitting phase, the third light emitting control signal EM3 outputs an active pulse signal, so that the second light emitting control module 14 and the second sub light emitting control module 11b are both turned on, and the first power signal PVDD sequentially passes through the turned-on second sub light emitting control module 11b, the driving module 12 and the second light emitting control module 14, and generates a driving current flowing into the light emitting element 20.

The control terminal of the optional first sub-lighting control module 11a is connected to the bias control signal line ST for receiving the bias control signal. The bias control signal outputs an active pulse in the bias stage, so that the first sub light emission control module 11a is turned on, and the first power signal PVDD is allowed to be written into the drain of the driving transistor T0.

Referring to fig. 6 and 7, fig. 6 is a schematic diagram of a pixel circuit of a fifth display panel according to an embodiment of the present invention, fig. 7 is a schematic diagram of a pixel circuit of a sixth display panel according to an embodiment of the present invention, and the optional display panel further includes a reset module 17, where the reset module 17 is configured to selectively provide a reset signal to the gate of the driving transistor T0; the control end of the reset module 17 is connected to the first scanning signal line S1 for receiving the first scanning signal S1; in some alternative embodiments, as shown in fig. 6, the bias control signal ST is the same signal as the first scan signal S1.

As shown in fig. 6 and 7, the input terminal of the reset module 17 receives the reset signal Vref, the control terminal of the reset module 17 receives the first scan signal S1, and the output terminal of the reset module 17 is electrically connected to the gate or the drain of the driving transistor T0. The first scan signal S1 provides an active pulse to the pixel circuit 10, so that the reset module 17 is turned on, and the reset signal Vref is directly written into the gate of the driving transistor T0 for resetting as shown in fig. 6. Alternatively, the first scan signal S1 provides an effective pulse to the pixel circuit 10, and the scan signal S3 provides an effective pulse to the compensation module 13, so that the reset module 17 and the compensation module 13 are turned on, and the reset signal Vref is written into the gate of the driving transistor T0 through the compensation module 13 for resetting as shown in fig. 7. The reset signal Vref is usually a negative voltage signal such as-7V, and during the reset phase, the gate of the driving transistor T0 is kept at a negative voltage, which facilitates the subsequent bias adjustment and data writing.

The selectable pixel circuit 10 further includes an initialization block 15, the initialization block 15 being configured to selectively provide an initialization signal Vini to the light emitting element 20; wherein the initialization module 15 remains on for at least part of the period of the bias phase. The control end of the initialization module 15 is connected to the second scan signal line S2 for receiving a second scan signal; as shown in fig. 7, the bias control signal ST and the second scan signal S2 may be the same signal. The input terminal of the initialization module 15 receives the initialization signal Vini, the output terminal of the initialization module 15 is electrically connected to the light emitting element 20, and the control terminal of the initialization module 15 receives the scan signal S2. In the initialization phase, the scan signal S2 provides an active pulse to the pixel circuit 10 to turn on the initialization module 15, and the initialization signal Vini is written into the light emitting element 20 of the pixel circuit 10 for initialization. The initialization signal Vini is usually a negative voltage signal, and the anode of the light emitting element 20 maintains a negative initial voltage during the initialization phase.

The selectable pixel circuit 10 further includes a data write module 16, the data write module 16 being configured to write a data signal Vdata to the gate of the driving transistor T0. The data writing module 16 has an input terminal receiving the data signal Vdata, an output terminal connected to the input terminal of the driving module 12, and a control terminal receiving the scan signal S4. The scan signal S1 outputs an active pulse signal during the data writing phase, and the scan signal S3 provides the active pulse signal to the compensation module 13, so that the data signal is written into the gate of the driving transistor T0 through the turned-on data writing module 16 and the turned-on compensation module 13.

The optional initialization block 15 includes a fourth transistor T4, a source of the fourth transistor T4 is for receiving an initialization signal Vini, a drain of the fourth transistor T4 is connected to the anode of the light emitting element 20, and a gate of the fourth transistor T4 is for receiving a scan signal S2.

The optional data writing module 16 includes a fifth transistor T5, a source of the fifth transistor T5 receives the data signal, a drain of the fifth transistor T5 is connected to the source of the driving transistor T0, and a gate of the fifth transistor T5 receives the scan signal S4.

The optional second sub light-emitting control module 11b includes a sixth transistor T6, a source of the sixth transistor T6 receiving the first power supply signal PVDD, a drain of the sixth transistor T6 connected to the source of the driving transistor T0, and a gate of the sixth transistor T6 receiving the third light-emitting control signal EM 3.

The optional reset module 17 includes a seventh transistor T7. The source of the seventh transistor T7 receives the reset signal Vref, the drain of the seventh transistor T7 is electrically connected to the gate or drain of the driving transistor T0, and the gate of the seventh transistor T7 receives the scan signal S1.

The selectable pixel circuit 10 further includes a storage capacitor C1, a first plate of the storage capacitor C1 being connected to the first power supply signal terminal, and a second plate of the storage capacitor C1 being connected to the gate of the drive transistor T0.

In the biasing stage, the first transistor T1 and the driving transistor T0 are turned on, the second transistor T2 is turned off, the first power supply signal PVDD is written to the drain of the driving transistor T0, and the drain and gate voltages of the driving transistor T0 are biased.

Alternative T0, T1, T3, T4, T5 and T6 are all PMOS with polysilicon as the active layer, and T2 and T7 are NMOS with indium gallium zinc oxide as the active layer. It is understood that the active pulse of the scan signal of the NMOS transistor is at a high level and the active pulse of the scan signal of the PMOS transistor is at a low level. It should be noted that the pixel circuits shown in fig. 1 to 7 are merely examples, and the structure of the pixel circuit in the embodiment of the present invention is not limited thereto. For example, in other embodiments, the pixel circuit may also be selected to have a 6T1C structure, without including an initialization module. It can be understood that, when the structure of the pixel circuit changes, the driving timing changes according to the structural change of the pixel circuit without changing the driving principle.

In this embodiment, optionally, the width-to-length ratio of the channel region of the NMOS transistor is greater than the width-to-length ratio of the channel region of the PMOS transistor, and therefore in the present application, the NMOS transistor mainly functions as a switching transistor and needs a fast response capability, while a transistor with a large width-to-length ratio has a shorter channel region length, which is beneficial to improving the response capability of the transistor.

In addition, in the present application, the four scan signals S1, S2, S3, and S4 may be different signals, and in some specific cases, if the timing sequence satisfies a certain condition, at least two of the four signals S1, S2, S3, and S4 may also be the same signal, for example, when T4 and T7 are the same type of transistor, for example, if both T4 and T7 are PMOS or NMOS, S1 and S2 may be the same signal. The specific situation depends on the specific circuit structure and timing, and this embodiment is not particularly limited thereto.

Optionally, in this embodiment, the first power signal received by the first lighting control module in the lighting phase may be the same as or different from the first power signal received by the first lighting control module in the bias phase, and in the case that the first power signal and the first power signal are the same, only one first power signal is needed to meet the requirements of the lighting phase and the bias phase, so that the panel operating program is fully simplified. In some embodiments, at least one of the first power signal received by the first lighting control module during the lighting phase and the first power signal received by the first lighting control module during the biasing phase is greater than the other. For example, during the lighting phase, the first power signal is PVDD1, and during the bias phase, the first power signal is PVDD2, and PVDD1 may or may not be equal to PVDD 2. In some embodiments, PVDD 2> PVDD1, and PVDD2 is larger than PVDD1, PVDD2 is higher, so that the drain voltage of the driving transistor is sufficiently raised during the bias period, and the time used during the bias period can be shortened. In other embodiments, PVDD2 < PVDD1 is suitable for the situation that a larger current intensity is required and a larger PVDD voltage is required to be applied in the light emitting stage to ensure the light emitting brightness of the light emitting element. The specific design can be determined according to specific situations.

In this embodiment, the operation process of the selectable pixel circuit further includes at least one non-bias phase; in the bias stage, the gate voltage of the driving transistor is Vg1, the source voltage is Vs1, and the drain voltage is Vd 1; in the non-bias stage, the gate voltage of the driving transistor is Vg2, the source voltage is Vs2, and the drain voltage is Vd 2; wherein,

|Vg1-Vd1|＜|Vg2-Vd2|；

in this case, by reducing the potential difference between the gate potential of the driving transistor T0 and the drain potential of the driving transistor T0, the phenomenon of the shift of the threshold voltage caused by the potential difference between the gate potential and the drain potential of the driving transistor T0 in the non-bias stage can be alleviated.

Additionally, in some embodiments of the present embodiment,

(Vg1-Vs1) × (Vg2-Vs2) <0, or,

(Vg1-Vd1)×(Vg2-Vd2)＜0。

during the operation of the pixel circuit, if the first power signal PVDD is written into the drain of the driving transistor through the source of the driving transistor, the gate voltage and the drain voltage of the driving transistor satisfy (Vg1-Vd1) × (Vg2-Vd2) < 0. In the non-bias stage, the gate voltage of the driving transistor in the pixel circuit is greater than the drain voltage of the driving transistor, namely Vg2> Vd2, and Vg2-Vd2> 0. In the bias phase, the first power signal PVDD is written into the drain of the driving transistor, so that the gate voltage of the driving transistor is less than the drain voltage of the driving transistor, namely Vg1< Vd1, and Vg1-Vd1< 0. Then (Vg1-Vd1) × (Vg2-Vd2) < 0.

In other embodiments, during operation of the selectable pixel circuit, if the first power signal PVDD is written to the source of the driving transistor through the drain of the driving transistor, the gate voltage and the source voltage of the driving transistor satisfy (Vg1-Vs1) × (Vg2-Vs2) < 0. In the non-bias stage, the gate voltage of the driving transistor in the pixel circuit is greater than the source voltage of the driving transistor, namely Vg2> Vs2, and Vg2-Vs2> 0. In the bias phase, the first power supply signal PVDD is written into the source of the driving transistor, so that the gate voltage of the driving transistor is less than the source voltage of the driving transistor, namely Vg1< Vs1, and Vg1-Vs1< 0. Then (Vg1-Vs1) × (Vg2-Vs2) < 0.

In addition, optionally, in this embodiment, because the time of the non-bias phase, such as the light-emitting phase of the display panel, is relatively long, the threshold voltage offset of the non-bias phase is to be fully balanced in the bias phase, and it is avoided that the bias phase takes too long, Vd1-Vg 1> Vg2-Vd2>0 may be set, so that Vd1-Vg1 of the bias phase is large enough, the bias phase can achieve the desired bias effect in as soon as possible, in other embodiments, if the source and the drain of the driving transistor are switched, Vs1-Vg 1> Vg2-Vs2>0 may also be set, depending on the specific circuit situation.

Optionally, in other embodiments of this embodiment, the time length of the bias phase is t1, and the time length of the non-bias phase is t2, wherein,

(| -Vg 1-Vs 1-Vg 2-Vs2) × (t1-t2) <0, or,

(∣Vg1-Vd1∣﹣∣Vg2-Vd2∣)×(t1-t2)＜0。

in this embodiment, during the bias phase, the first power signal PVDD is written to the drain of the driving transistor through the source of the driving transistor, and in some embodiments, the drain voltage of the driving transistor may be made greater than the gate voltage of the driving transistor, i.e., Vg1-Vd1< 0. In the non-bias stage, the gate voltage of the driving transistor is greater than the drain voltage of the driving transistor, namely Vg2-Vd2> 0. In the process of biasing the driving transistor, if the bias voltage is large, the bias time can be reduced appropriately, and if the bias voltage is small, the bias time can be extended appropriately.

Based on this, if | Vg1-Vd 1-Vg 2-Vd2 | 0 indicates that the offset voltage is larger, the duration of the offset stage, i.e. t1< t2, can be reduced appropriately, so as to reduce the deviation of the threshold voltage in the offset stage and the non-offset stage. If | Vg1-Vd1 | -Vg 2-Vd2 | <0, which indicates that the offset voltage is smaller, the duration of the offset phase can be extended appropriately, i.e., t1> t2, so as to reduce the deviation of the threshold voltage in the offset phase and the non-offset phase.

In other embodiments, during the bias stage, the first power signal PVDD is written to the source of the driving transistor via the drain of the driving transistor, and the gate and drain of the driving transistor satisfy (| Vg1-Vs1 | -Vg 2-Vs2 |) × (t1-t2) <0 during the bias stage and the non-bias stage, so as to reduce the deviation of the threshold voltages during the bias stage and the non-bias stage.

Optionally, in this embodiment, the time of the bias phase is greater than 5 microseconds, and particularly, the time of the bias phase may be greater than 20 microseconds, and the utility model discloses a person of this application verifies that the phenomenon of alleviating the threshold voltage offset can be effectively played when the time of the bias phase is greater than 5 microseconds, especially greater than 20 microseconds. When the time of the bias phase is less than 5 μ s, the bias state of the driving transistor T0 is not sufficiently adjusted because the time of the bias phase is too short, and the effect of better alleviating the threshold voltage shift cannot be achieved.

The optional unbiased phase is a light emitting phase of the display panel. Illustratively, in a light emitting period, the source voltage of the driving transistor T0 is 4.6V, the gate voltage is 3V, the drain voltage is 1V, the gate voltage of the driving transistor is greater than the drain voltage of the driving transistor, and by the biasing period, the driving transistor is biased, and the threshold voltage shift of the driving transistor in the light emitting period can be compensated.

Within the time of one frame of picture of the selectable display panel, the working process of the pixel circuit comprises a front stage and a light-emitting stage; the pre-stage of the pixel circuit comprises a bias stage in at least one frame time.

In this embodiment, within a frame of time of the display panel, the working process of the pixel circuit includes a pre-stage and a light-emitting stage. In at least one frame of picture time, the front stage of the pixel circuit comprises a bias stage, in the bias stage, a first power supply signal is written into the drain electrode of the driving transistor through the source electrode of the driving transistor, the drain electrode potential of the driving transistor is adjusted, and the driving transistor is biased. In a non-bias stage such as a light-emitting stage, if the gate voltage of the driving transistor is greater than the drain voltage of the driving transistor, which may cause the threshold voltage of the driving transistor to increase, the pixel circuit increases a bias stage within at least one frame time, which may at least partially balance the increase of the threshold voltage of the driving transistor in the non-bias stage, thereby improving the display uniformity of the display panel.

Referring to fig. 8, fig. 8 is a schematic diagram of a first operation timing sequence of the pixel circuit, in conjunction with the pixel circuit in fig. 6, the control terminal of the optional reset module 17 is connected to the first scan signal line S1, the bias control signal ST is the same as the first scan signal S1, and here, the transistor T7 in the reset module and the transistor T1 in the first sub lighting control module are the same type of transistor, such as both NMOS transistors or PMOS transistors. The working process of the optional pixel circuit comprises a reset phase and a bias phase; the reset phase is performed simultaneously with the bias phase.

In the bias phase and the reset phase, the third light emission control signal EM3 outputs an inactive pulse so that the sixth transistor T6 and the third transistor T3 are turned off; the first scan signal S1 outputs an active pulse, so that the seventh transistor T7 is turned on, and the reset signal Vref is written to the gate of the driving transistor T0; the third scan signal S3 outputs an inactive pulse such that the second transistor T2 is turned off; the fourth scan signal S4 outputs an inactive pulse so that the fifth transistor T5 is turned off. The reset of the gate of the driving transistor T0 is achieved. Meanwhile, the first transistor T1 is turned on, and the first power signal PVDD is written to the drain of the driving transistor T0, thereby biasing the gate voltage and the drain voltage of the driving transistor T0.

The reset phase and the bias phase are performed simultaneously, on one hand, the gate voltage of the driving transistor T0 is adjusted through the reset signal, and on the other hand, the drain voltage of the driving transistor T0 is adjusted through the first power signal PVDD, so that the gate voltage and the drain voltage of the driving transistor T0 are adjusted simultaneously, and the bias effect can be improved.

Referring to fig. 9, fig. 9 is a schematic diagram of a second operation timing sequence of the pixel circuit, and in conjunction with the pixel circuit shown in fig. 7, the optional pixel circuit further includes an initialization module 15, and the initialization module 15 is kept on during at least a part of the period of the bias phase. Part of the time period of the bias phase is multiplexed as the initialization phase, the optional second scan signal S2 outputs an active pulse to turn on the fourth transistor T4, and the initialization module 15 provides the initialization signal Vini to the light emitting element 20.

The selectable bias control signal ST is the same signal as the second scan signal S2. The working process of the selectable pixel circuit comprises an initialization phase and a bias phase; the initialization phase is performed simultaneously with the biasing phase. I.e. the full time period of the bias phase is synchronized to the initialization phase.

The initialization phase is performed simultaneously with the bias phase, which can ensure that the light emitting element 20 receives the initialization signal, because the data signal is written into the drain of the driving transistor T0 in the bias phase, although T3 is turned off, the transistor may have a certain leakage current, so if the light emitting element 20 does not receive the initialization signal, the light emitting element 20 may be stolen and lighted in the bias phase, and the light emitting element 20 is initialized in the bias phase, which can ensure that the light emitting element 20 does not emit light.

In other embodiments, as shown in fig. 8, a part of the time period of the reset phase may also be selected to be multiplexed as the initialization phase. In the case that reset, bias and initialization do not interfere, the relevant practitioner can set the reset timing, bias timing and initialization timing appropriately.

Referring to fig. 10, fig. 10 is a schematic diagram of a third timing sequence of operation of a pixel circuit, in conjunction with the pixel circuit shown in fig. 3, the optional pre-stage including a reset stage and a bias stage; in the reset phase, the gate of the driving transistor receives a reset signal to reset.

In the reset phase, when the scan signal S1 outputs a high-level pulse, the seventh transistor T7 is turned on and the first transistor T1 is turned off, and the reset signal Vref is written into the gate of the driving transistor T0, so that the gate of the driving transistor T0 is reset to a negative potential less than 0V. In the bias stage, when the scan signal S1 outputs a low-level pulse, the seventh transistor T7 is turned off, the EM1 signal changes to a low level, the first transistor T1 is turned on, and at this time, the second transistor T2 remains turned off, and the first power signal PVDD is written into the drain of the driving transistor T0, so as to bias the driving transistor.

The time length of the optional bias phase is t1, and the time length of the reset phase is t3, wherein t1> t 3.

The reset phase is only used to write a reset signal to the gate of the drive transistor so that the gate of the drive transistor is reset to a negative potential less than 0V, so the reset phase duration t3 may be small. And during the bias phase, a first power supply signal is written into the drain electrode of the driving transistor, the driving transistor is biased to weaken the threshold voltage drift of the driving transistor during the light-emitting phase, and the time length of the light-emitting phase is longer, so that the time length t1 of the bias phase is longer, and the threshold voltage drift during the non-bias phase is sufficiently weakened. Based on this, t1> t3 is set.

At the end of the optional reset phase shown in fig. 10, the gate of the driving transistor is disconnected from the reset signal, and at the same time, the first lighting control module is turned on, and the pixel circuit enters the bias phase. In this embodiment, when the reset phase of the pixel circuit is finished, the first lighting control module is turned on to enter the bias phase, and there is no time interval between the reset phase and the bias phase, so as to ensure that the pre-stage of the pixel circuit is shortened as much as possible, thereby reducing the time length of one frame of picture.

Referring to fig. 11, a schematic diagram of a fourth operation timing of the pixel circuit of fig. 11, between the end of the optional reset phase and the start of the bias phase, the pre-phase further includes a first interval phase, in the first interval phase, the gate of the driving transistor is disconnected from the reset signal, and the first light-emitting control module is kept turned off. In this embodiment, in the first interval stage, the scan signal S1 jumps from high level to low level, the seventh transistor T7 is turned off, and the gate of the driving transistor is disconnected from the reset signal; and the first lighting control signal EM1 keeps the high level pulse signal and the first lighting control module keeps off, the driving transistor may have a stable period. When the first interval phase is finished, the first lighting control signal EM1 jumps to a low level pulse signal, the first lighting control module is turned on, and the pixel circuit enters the bias phase. After the reset stage, the transistor is stably driven through the first interval stage and then enters the bias stage, so that the stability of the pixel circuit can be improved.

The time length of the optional bias phase is t1, the time length of the reset phase is t3, and the time length of the first interval phase is t4, wherein t1> t4 or t3 > t 4. It is understood that the reset phase is only used for resetting the gate voltage of the driving transistor, and the first interval phase is used for stabilizing the driving transistor, so that the duration t3 of the reset phase and the duration t4 of the first interval phase may have only one reaction time length, without an excessive time, and thus t1> t4 or t3 > t4 are set.

Referring to fig. 12, fig. 12 is a schematic diagram of a fifth timing of operation of a pixel circuit with an optional reset phase at least partially overlapping with a period of a bias phase. For the pixel circuit shown in fig. 3, the reset module 17 is directly connected to the gate of the driving transistor T0, the first power signal is written into the drain of the driving transistor during the bias period, and the operations during the reset period and the bias period do not affect each other when the second transistor T2 is turned off. Based on this, the time period of the optional reset phase and the bias phase at least partially overlap.

In the reset phase, the second transistor T2 is turned off and the seventh transistor T7 is turned on, so that the reset signal Vref is written into the gate of the driving transistor T0. In the overlapping period of the bias period and the reset signal, when the second transistor T2 is kept off and the first transistor T1 is turned on, the first power signal is written into the drain of the driving transistor T0, and simultaneously the seventh transistor T7 is kept on, the reset signal Vref is continuously written into the gate of the driving transistor T0, so that the gate voltage of the driving transistor T0 can be stabilized. In the bias phase, a reset phase is performed, on one hand, the potential of the drain of the driving transistor T0 is adjusted by the first power signal, and on the other hand, the potential of the gate of the driving transistor T0 is adjusted by the reset signal, so that the gate potential and the drain potential of the driving transistor are adjusted at the same time, and the bias effect is improved.

Referring to fig. 13, fig. 13 is a diagram illustrating a sixth operation timing of the pixel circuit, where the gate of the driving transistor keeps receiving a reset signal during the optional bias phase. In the bias stage, the second transistor T2 is kept off, the first transistor T1 is turned on, and the seventh transistor T7 is kept on, so that the first power signal is written into the drain of the driving transistor T0, and meanwhile, the reset signal Vref is continuously written into the gate of the driving transistor T0, so that the gate voltage of the driving transistor T0 can be stabilized in the bias stage. In addition, the reset phase is overlapped with the bias phase, so that the duration of the pre-phase of the pixel circuit is shortened, high-frequency display can be realized, and optionally, the starting time of the reset phase is earlier than or equal to the starting time of the bias phase, and the ending time of the reset phase is later than or equal to the ending time of the bias phase.

Referring to fig. 14, fig. 14 is a schematic diagram of a seventh operation timing sequence of the pixel circuit, the selectable reset phase includes a first reset phase and a second reset phase; a first reset phase which is not overlapped with the time of the bias phase, wherein the grid electrode of the driving transistor receives a first reset signal; the gate of the drive transistor receives a second reset signal during at least part of the period of the bias phase, the bias phase at least partially overlapping with the time of the second reset phase. The first reset phase may be used to reset the gate potential of the drive transistor, which in some cases may be made lower than 0V. The second reset phase can be used for stabilizing the grid potential of the driving transistor in the bias phase, and the bias adjustment of the driving transistor is realized. A portion of the time of the selectable bias phase overlaps the time of the second reset phase, or the entire time of the selectable bias phase overlaps the time of the second reset phase.

The selectable first reset signal and the second reset signal have the same potential. Alternatively, the first reset signal and the second reset signal may be selected to have different potentials. The first reset signal needs to function to pull down the gate potential of the driving transistor so that the first reset signal is less than 0V. And the second reset signal is used for stabilizing the grid potential of the driving transistor in the biasing stage so as to improve the biasing effect. In this case, the second reset signal may be the same as or different from the first reset signal. The relevant practitioner can design the pixel circuit flexibly under different design requirements.

Optionally, an absolute value of a potential of the first reset signal is greater than an absolute value of a potential of the second reset signal; the driving transistor is a PMOS transistor, and the potential of the first reset signal is lower than that of the second reset signal; alternatively, the driving transistor is an NMOS transistor, and the potential of the first reset signal is higher than the potential of the second reset signal. The absolute value of the potential of the optional first reset signal is larger than the absolute value of the potential of the second reset signal, so that the second reset signal plays a role in biasing in the biasing stage, and the power consumption of the pixel circuit can be reduced by adopting the second reset signal with a lower absolute value of the potential.

In another embodiment, optionally, an absolute value of a potential of the first reset signal is smaller than an absolute value of a potential of the second reset signal; the driving transistor is a PMOS transistor, and the potential of the second reset signal is lower than that of the first reset signal; or, the driving transistor is an NMOS transistor, and the potential of the second reset signal is higher than the potential of the first reset signal. The absolute value of the potential of the optional first reset signal is smaller than the absolute value of the potential of the second reset signal, and in a specific case of the display panel, such as in the case of high-frequency driving, the level of the first reset signal is a negative potential whose absolute value is relatively small in the reset phase, the time of the data write phase can be shortened, thereby contributing to realization of high-frequency driving.

Referring to fig. 15, fig. 15 is a diagram of an eighth operation timing sequence of the pixel circuit, which is selectable in the bias phase, the second reset phase is performed at least twice, and the gate of the driving transistor is disconnected from the reset signal between the adjacent second reset phases. In this embodiment, in the bias stage, a plurality of second reset stages may be designed, each second reset stage may reset the gate potential of the driving transistor, and the gate potential of the driving transistor is stabilized in the bias stage, so that the bias adjustment of the driving transistor is facilitated, and the bias effect is further improved.

Alternatively, as shown in fig. 14 and 15, the gate of the driving transistor is disconnected from the reset signal before the end of the bias phase, and thereafter, the bias phase ends. Before the biasing phase is finished, the seventh transistor T7 is turned off to disconnect the gate of the driving transistor from the reset signal, and then the biasing phase is finished.

Alternatively, as shown in fig. 13, the gate of the driving transistor is disconnected from the reset signal at the same time as the end of the bias phase. In this embodiment, the whole time period of the bias phase overlaps with the reset phase, the turn-on time of the reset phase is earlier than or the same as the turn-on time of the bias phase, and the end time of the reset phase is later than or the same as the end time of the bias phase. As described above, the reset signal is continuously written into the gate of the driving transistor in the reset phase and the bias phase, so that the gate voltage of the driving transistor is ensured to be stable before the data writing phase, and the bias effect is improved.

Optionally, as shown in fig. 3 to fig. 7, in this embodiment, the pixel circuit 10 further includes a data writing module 16, where the data writing module 16 is configured to selectively provide a data signal to the driving module 12; optionally, in this embodiment, the pre-stage includes a bias stage and a data writing stage; in the data writing phase, the data writing module 16, the driving module 12 and the compensation module 13 are all turned on, and the data signal is written into the gate of the driving transistor T0. In the data writing phase, the fifth transistor T5, the driving transistor T0 and the second transistor T2 are all turned on, and the data signal is written into the control terminal of the driving module 12, i.e., the gate of the driving transistor T0, through the turned-on data writing module 16, the driving module 12 and the compensation module 13.

The time length of the optional bias phase is t1, and the time length of the data writing phase is t5, wherein t1> t 5. It is understood that the data writing phase is only used for writing the data signal into the gate of the driving transistor, and thus the reaction time length is satisfied. And in the bias stage, a first power supply signal is written into the drain electrode of the driving transistor, and the bias driving transistor is used for weakening the threshold voltage drift of the driving transistor in the light-emitting stage. Since the time length of the non-bias phase such as the light-emitting phase is long, the time length t1 of the bias phase is increased so as to sufficiently reduce the threshold voltage shift of the non-bias phase. Based on this, t1> t5 is set.

Referring to fig. 16, fig. 16 is a diagram illustrating a ninth operation timing of the pixel circuit, wherein the pixel circuit includes a second interval phase from the end of the optional bias phase to the beginning of the data writing phase, and the first light-emitting control module is turned off and the data writing module is kept turned off in the second interval phase. In this embodiment, in the second interval stage, when the first emission control signal EM1 changes from low level to high level, the first transistor T1 is turned off, and the drain of the driving transistor is disconnected from the first power signal. Meanwhile, the data writing module is kept off, and the driving transistor can have a stable period. At the end of the second interval period, the first emission control signal EM1 remains high, the first transistor T1 is turned off, and the pixel circuit enters the data writing period. After the biasing stage is finished, the transistor is stably driven through the second interval stage, and then the data writing stage is entered, so that the stability of the pixel circuit can be improved.

The time length of the optional bias phase is t1, the time length of the data writing phase is t5, and the time length of the second interval phase is t6, wherein t1 is greater than t6, or t5 is greater than t 6. It is understood that the data writing phase is only used for writing the data signal into the gate of the driving transistor, and the second interval phase is used for stabilizing the driving transistor, so that the duration t5 of the data writing phase and the duration t6 of the second interval phase can only have a reaction time length, and no excessive time is needed, so that t1> t6 or t5 > t6 is set.

In addition, in this embodiment, as shown in fig. 10 to fig. 15, when the optional bias phase is ended, the first light-emitting control module is turned off, and simultaneously, the data writing module is turned on, and the pixel circuit enters the data writing phase. In this embodiment, when the bias phase is ended, the first lighting control module is turned off, and the first power signal is not written into the source of the driving transistor. Meanwhile, the data writing module is started, the pixel circuit enters a data writing stage, and a data signal is written into the drain electrode of the driving transistor through the source electrode of the driving transistor. The first lighting control module is turned off at the data writing stage to avoid the first power signal from influencing the data writing process. In addition, the method can fully shorten the time length of the front stage on the premise of ensuring the time length of the offset stage, thereby being beneficial to realizing high-frequency display.

Optionally, in this embodiment, referring to fig. 6 and fig. 10 to 16, the pixel circuit further includes a data writing module, where the data writing module is configured to selectively provide a data signal to the driving module; the pre-stage sequentially comprises a reset stage, a bias stage and a data writing stage; in the reset stage, the grid electrode of the driving transistor receives a reset signal to reset; in the data writing stage, the data writing module, the driving module and the compensation module are all started, and the data signal is written into the grid electrode of the driving transistor.

In this embodiment, in the pre-stage of the pixel circuit, the gate of the driving transistor is reset first, so that the gate voltage of the driving transistor is pulled down to a negative voltage lower than 0V, which facilitates the subsequent biasing of the driving transistor. And secondly, biasing the driving transistor, writing a first power supply signal into the drain electrode of the driving transistor, and weakening the threshold voltage drift of the driving transistor caused in a non-biasing stage. And finally, in the data writing stage, the data writing module, the driving module and the compensation module are all started, and the data signals are written into the grid electrode of the driving transistor.

The time length of the optional bias phase is t1, the time length of the reset phase is t3, and the time length of the data writing phase is t4, wherein t1> t3, and t1> t 4. Within one frame time, the non-bias stage causes the threshold voltage drift of the driving transistor, while the non-bias stage has a longer time length. The data writing stage is only used for writing the data signal into the gate of the driving transistor, and the time length of the data writing stage is set to be shorter. The reset phase is only used to write a reset signal to the gate of the drive transistor, and the length of time for setting the reset phase is short. Based on this, t1> t3, and t1> t4 are set.

Referring to FIG. 17, FIG. 17 is a schematic diagram of a tenth operation timing sequence of the pixel circuit, which is exemplary, based on any of the above embodiments, that the optional bias phase includes m sub-bias phases, where m ≧ 1; in the m sub-bias stages, the interval between two adjacent sub-bias stages is a third interval stage, and in the third interval stage, the first light emitting control module is turned off.

As shown in fig. 17, the optional bias stages include at least 2 sub-bias stages that are sequentially performed, and in the at least 2 sub-bias stages, an interval between two adjacent sub-bias stages is a third interval stage. In the sub-bias stage, the first light-emitting control module is started, and a first power supply signal is written into the drain electrode of the driving transistor; in a third interval phase, the first lighting control module is switched off. Specifically, in the sub-bias stage, the first light emitting control signal EM1 outputs an effective pulse signal, so that the first light emitting control module is turned on, and the first power signal is written into the drain of the driving transistor through the first light emitting control module and the driving module in sequence, thereby implementing the bias of the driving transistor. In the third interval phase, the first lighting control signal EM1 outputs an invalid pulse signal, so that the first lighting control module is turned off, and the first power supply signal is disconnected from the drain of the driving transistor. The bias stage comprises a plurality of sub-bias stages, each sub-bias stage can weaken the threshold voltage drift of the driving transistor in the non-bias stage, and the threshold voltage drift of the driving transistor caused by the non-bias stage can be fully weakened through the plurality of sub-bias stages, so that the bias effect is further improved.

In other embodiments, the bias phase shown in fig. 11 may also include a sub-bias phase, i.e., a bias phase, and the first lighting control module is normally on.

The selectable bias stages include at least two third interval stages, and wherein the time lengths of the at least two third interval stages are not equal. The time length of the optional third interval phase increases or decreases sequentially with the m sub-bias phases. Optionally, the time length of the at least one third interval phase is shorter than the time length of the at least one sub-bias phase, and the third interval phase is a transition phase between the sub-bias phases, and thus, the time length thereof may be shorter than the time length of the sub-bias phases. In particular, the time length of any third interval phase is shorter than the time length of any sub-bias phase. It can be understood that the durations of the plurality of third interval phases may be the same or different, or the durations of the plurality of third interval phases satisfy the rules of increasing or decreasing, and the embodiments of the present invention flexibly design the bias phase of the pixel circuit according to the bias requirement of the pixel circuit under different conditions, and are not limited thereto.

In the selectable m sub-bias stages, the time lengths of at least two sub-bias stages are not equal. The time length of the first sub-bias phase may be chosen to be longer than the time lengths of the other sub-bias phases. The time length of the optional sub-bias phases becomes shorter in sequence with the m sub-bias phases. It can be understood that the durations of the multiple sub-bias stages may be the same or different, or the durations of the multiple sub-bias stages satisfy the rules of increasing or decreasing, etc., and in the embodiment of the present invention, the bias stage of the pixel circuit is flexibly designed according to the bias requirements of the pixel circuit under different conditions, which is not limited thereto.

For the condition that the time length of the first sub-bias stage is longer than the time lengths of other sub-bias stages, in the bias stage, the driving transistor is biased in the first sub-bias stage, so that the threshold voltage drift of the driving transistor in the non-bias stage can be effectively weakened, the driving transistor is biased through other sub-bias stages with shorter time length, and the bias adjustment can be dynamically carried out according to the bias condition, so that the threshold voltage drift of the driving transistor in the non-bias stage is fully weakened through a plurality of sub-bias stages. Thereby ensuring that the bias phase is not too long.

Optionally, with reference to fig. 17 and fig. 16, a time length of at least one third interval phase is not equal to a time length of the second interval phase, because the third interval phase is an interval phase between any two adjacent sub-bias phases, and the second interval phase is a time interval between a bias phase and a data writing phase, the time lengths of the second interval phase and the third interval phase may be flexibly set according to specific situations.

Illustratively, based on any of the above embodiments, one data writing period of the selectable display panel comprises S frames of refresh pictures including a data writing frame and a holding frame, S >0, wherein at least the data writing frame comprises a bias phase. In the data writing frame stage, the pixel circuit writes new display data; in the frame holding stage, the pixel circuit is refreshed normally, but the display data of the previous frame is held, and new display data is not written. In the time of writing data into the frame picture, in the offset stage, the first light-emitting control module and the driving module are started, the compensation module is turned off, and the first power supply signal is written into the drain electrode of the driving transistor from the source electrode of the driving transistor and is used for offsetting the voltage between the grid electrode and the drain electrode of the driving transistor.

Referring to fig. 18, fig. 18 is a schematic diagram of an eleventh operation timing sequence of the pixel circuit, in this embodiment, at least one data writing frame and at least one holding frame may be selected to include an offset phase, and a time length of the offset phase in the at least one holding frame is longer than a time length of the offset phase in the data writing frame. And in the frame image keeping time, in a bias stage, the first light-emitting control module and the driving module are started, the compensation module is turned off, and the first power supply signal is written into the drain electrode of the driving transistor from the source electrode of the driving transistor and is used for biasing the voltage between the grid electrode and the drain electrode of the driving transistor. The frame display of the previous frame is kept, the data writing stage is not included, as long as the first light-emitting control module is started, the compensation module is turned off, and the second light-emitting control module is turned off, namely the offset stage is formed, so that the offset adjustment can be carried out by adopting more time length. The data writing frame displays a new frame of picture, and the normal light-emitting period duration needs to be ensured. Based on this, the time length of at least one holding intra-frame offset stage can be selected to be longer than the time length of the data writing intra-frame offset stage, and on the basis of ensuring display, a better offset effect can be achieved.

Referring to fig. 19, fig. 19 is a diagram illustrating a twelfth operation timing sequence of the pixel circuit, wherein the selectable display panel comprises at least two data writing frames, and the time lengths of the offset phases in the at least two data writing frames are different. The selectable display panel comprises first data writing frames and second data writing frames, wherein n second data writing frames are arranged between every two adjacent first data writing frames, and n is larger than or equal to 1; the time length of the offset phase in the first data writing frame is t7, and the time length of the offset phase in the second data writing frame is t8, wherein t7 is more than t8 and is more than or equal to 0.

The display panel displays a plurality of second data write frame pictures. In the second data writing frame picture, the time length of the bias phase is t8, and in the bias phase, the voltages of the grid electrode and the drain electrode of the driving transistor can be biased, so that the effect of weakening the threshold voltage drift of the driving transistor is achieved. In practical application, the threshold voltage drift of the driving transistor cannot be sufficiently reduced in the offset stage when the second data is written into the frame, and the display panel displays a plurality of second data written into the frame, and the second data is accumulated for a long time, or internal characteristics of the driving transistor are changed. Based on this, the time length of the bias stage in the first data writing frame is t7, and the time length of the bias stage in the frame picture is increased to weaken the threshold voltage drift of the driving transistor accumulated until the current frame picture, so that the bias effect is improved, and the display uniformity is further improved.

In some embodiments, the second data write frame may further not include the offset phase, i.e., t8 is 0, in which case, the offset phase does not need to be performed in each data write frame, and the offset phase may be set only in the first data write frame, thereby simplifying the driving process of the display panel.

Referring to fig. 20, fig. 20 is a schematic diagram of a thirteenth operation timing sequence of the pixel circuit, where a data writing period of the selectable display panel includes S frames of refresh pictures, including a data writing frame and a holding frame, S >0, where at least one holding frame includes an offset phase, in this embodiment, in the holding frame phase, the pixel circuit is refreshed normally, but the display data of the previous frame is held, and the holding frame does not include the data writing phase, then the holding frame displays the display picture of the previous frame. And in the bias stage, the source electrode of the driving transistor writes a first power supply signal into the drain electrode of the driving transistor in the frame time, and the first power supply signal is used for biasing the voltage between the grid electrode and the drain electrode of the driving transistor. After the bias stage is finished, the frame is directly kept to enter the light-emitting stage to display the previous frame. Therefore, the duration of the frame holding pre-stage can be shortened, the working duration of the frame holding picture is shortened, and the frame refreshing frequency is improved.

Optionally, as shown in fig. 20, in the holding frame, the pre-stage sequentially includes a reset stage and a bias stage; in the reset stage, the grid electrode of the driving transistor receives a reset signal to reset; the data writing phase is not included between the bias phase and the light emitting phase.

Referring to fig. 21, fig. 21 is a schematic diagram of a fourteenth operation timing sequence of the pixel circuit, wherein a data writing period of the selectable display panel comprises S frames of refresh pictures in total, including a data writing frame and a holding frame, S >0, wherein at least one holding frame comprises a bias phase, and wherein in the holding frame, a pre-phase comprises a reset phase and a bias phase; in the reset stage, the grid electrode of the driving transistor receives a reset signal to reset; the reset phase overlaps at least partially with the bias phase in time. In this embodiment, in the frame image, the time of the reset phase and the time of the offset phase are at least partially overlapped, so that the duration of the frame image holding pre-stage can be further shortened, the working duration of the frame image holding is shortened, and the frame refresh frequency is further improved.

It should be noted that, in this embodiment, only the pre-stage of the data write frame may include the offset stage, and the pre-stage of the hold frame does not include the offset stage, and at this time, if only the data write frame can be used, that is, the offset problem is solved, it is not necessary to set the offset stage in the hold frame. It is also possible that only the pre-stage of the hold frame includes the offset stage, and the pre-stage of the data write frame does not include the offset stage, and the data write frame also undertakes the operations of the reset stage and the data write stage, and therefore, if the hold frame can undertake the operations of the offset stage completely, the offset stage may not be set in the data write frame, so as to simplify the timing of the data write frame.

It should be noted that, in the above drawings, the initialization phase of the light emitting element is at least partially overlapped with the bias phase and the reset phase, but the present embodiment is not limited thereto, and in some other embodiments, the initialization phase may not be overlapped with the bias phase, or the initialization phase may be performed simultaneously in the entire bias phase, and the initialization phase may still be performed when the bias phase is ended. The design can be flexibly carried out according to specific circuit conditions.

In the embodiment of the utility model, the working process of the pixel circuit comprises a bias stage, in the bias stage, the first light-emitting control module and the driving module are started, the compensation module is turned off, and the first power supply signal is written into the drain electrode of the driving transistor through the started first light-emitting control module and the started driving module so as to adjust the potential of the drain electrode of the driving transistor and improve the potential difference between the grid potential of the driving transistor and the drain electrode potential of the driving transistor. The pixel circuit comprises at least one non-bias stage, when the driving current is generated in the driving transistor, the gate potential of the driving transistor is possibly larger than the drain potential of the driving transistor, so that the I-V curve of the driving transistor is shifted, and the threshold voltage of the driving transistor is shifted. In the biasing stage, the offset phenomenon of an I-V curve of the driving transistor in the non-biasing stage can be balanced by adjusting the grid potential and the drain potential of the driving transistor, the threshold voltage drift phenomenon of the driving transistor is weakened, and the display uniformity of the display panel is ensured.

Based on the same utility model concept, the embodiment of the utility model also provides a display device, which comprises the display panel as described in any of the above embodiments. The display panel can be selected to be an organic light emitting display panel or a micro LED display panel.

Referring to fig. 22, fig. 22 is a schematic diagram of a display device according to an embodiment of the present invention, which can be applied to an electronic device 100 such as a smart phone and a tablet computer. It can be understood that the above embodiments only provide some examples of the pixel circuit structure and the driving method of the pixel circuit, and the display panel further includes other structures, which are not described in detail herein.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, comprising:

a pixel circuit and a light emitting element;

the light-emitting control module comprises a first light-emitting control module, a second light-emitting control module and a control module, wherein the first light-emitting control module is connected between a first power signal end and a source electrode of the driving transistor, and the first power signal end provides a first power signal;

the driving module comprises a driving transistor;

the pixel circuit comprises a light emission phase and a bias phase, wherein,

in the bias phase, the first light-emitting control module and the driving module are switched on, the compensation module is switched off, the driving transistor and the light-emitting element are switched off, and the first power supply signal is written into the drain electrode of the driving transistor;

the light-emitting control module further comprises a second light-emitting control module, and the second light-emitting control module is connected between the driving transistor and the light-emitting element;

in the bias phase, the second light emitting control module is turned off;

in the lighting phase, the second lighting control module is started;

the first light-emitting control module comprises a first sub light-emitting control module and a second sub light-emitting control module, and the first sub light-emitting control module and the second sub light-emitting control module are connected in parallel between a first power signal end and the driving module;

in the bias phase, the second sub-lighting control module is turned off, and the first sub-lighting control module is turned on.

2. The display panel according to claim 1,

the control end of the first light-emitting control module is connected to the first light-emitting control signal line and used for receiving a first light-emitting control signal;

and the control end of the second light-emitting control module is connected to the second light-emitting control signal line and used for receiving a second light-emitting control signal.

3. The display panel according to claim 2,

the width of the first light-emitting control signal line is greater than that of the second light-emitting control signal line.

4. The display panel according to claim 1,

the control ends of the second light-emitting control module and the second sub light-emitting control module are connected to a third light-emitting control signal line and used for receiving a third light-emitting control signal.

5. The display panel according to claim 1,

and the control end of the first sub light-emitting control module is connected to a bias control signal line and used for receiving a bias control signal.

6. A display device characterized by comprising the display panel according to any one of claims 1 to 5.