CN216792714U - Intelligent brake pump control terminal - Google Patents

Abstract

The utility model discloses an intelligent brake pump control terminal, which comprises a central processing module, a switching value input circuit, a switching value output circuit, an analog input circuit, an RS485 interface circuit, an RS232 interface circuit, a 100M Ethernet interface circuit, a mini-PCIE interface circuit, an SD card interface circuit, an OTG interface circuit, a real-time clock module and a power supply conversion circuit, wherein the switching value input circuit is connected with the switching value output circuit; the central processing module and the power supply conversion circuit are respectively connected with other modules and circuits. The utility model can realize high-speed and accurate control and scheduling of the dispersed small water conservancy facilities, and conveniently carry out combined scheduling of the gate pump group through an integrated algorithm and a control strategy; and the modularized design is adopted, the installation is convenient and simple, the expansion is flexible, at most 2 groups of cascade connection can be realized, 250 nodes of the gate pump can be controlled, data interaction can be carried out with an upper computer through a network, a part of control strategies are operated on a terminal, the calculation amount of the upper computer is reduced, and the intelligent degree is improved.

Description

Intelligent brake pump control terminal

Technical Field

The utility model relates to the technical field of joint scheduling of floodgate pumps in a stagnant flood storage area, in particular to an intelligent floodgate control terminal.

Background

At present, a known gate pump control terminal is controlled by a PLC (programmable logic controller), and an upper computer performs information interaction with the gate pump control terminal through a network by acquiring information such as current gate water level and flow, so as to control water conservancy facilities such as gates and pump stations. However, for the gate pump control of small reservoirs, river channels, water channels, connecting enclosures and the like, the gate pump control terminal based on the PLC has more mechanical and electrical accessories when controlling dispersed small water conservancy facilities, and the daily maintenance workload is larger. And under the combined dispatching environment of the gate pump group, the operation amount of the upper computer is increased, and the intelligent degree is lower.

SUMMERY OF THE UTILITY MODEL

In order to overcome the defect that the conventional PLC-based gate pump control terminal has large workload of daily maintenance in the environment of dispersed small water conservancy facilities, the utility model provides the intelligent gate pump control terminal, which carries out data interaction with an upper computer through a network according to the running condition of each gate pump facility, integrates related gate pump control algorithms, runs part of control strategies on the terminal, reduces the operand of the upper computer and improves the intelligent degree.

In order to achieve the purpose, the utility model adopts the following technical scheme:

the utility model provides an intelligent brake pump control terminal, which comprises a central processing module, a switching value input circuit, a switching value output circuit, an analog input circuit, an RS485 interface circuit, an RS232 interface circuit, a 100M Ethernet interface circuit, a mini-PCIE interface circuit, an SD card interface circuit, an OTG interface circuit, a real-time clock module and a power supply conversion circuit, wherein the switching value input circuit is connected with the switching value output circuit;

the switching value input circuit is connected with the central processing module and is used for acquiring switching value signals of the gate pump and sending the switching value signals to the central processing module;

the switching value output circuit is respectively connected with the central processing module and the gate pump and is used for outputting a switching value signal to drive the gate pump;

the analog input circuit is connected with the central processing module and is used for acquiring an analog signal of the gate pump and sending the analog signal to the central processing module;

the RS485 interface circuit is connected with the central processing module and is used for acquiring digital quantity signals of the gate pump and realizing module expansion;

the RS232 interface circuit is connected with the central processing module and is used for communicating with external debugging equipment;

the 100M Ethernet interface circuit is connected with the central processing module and is connected to an upper computer through a wireless network communication module;

the mini-PCIE interface circuit is connected with the central processing module and is connected to an upper computer in a wireless external connection mode;

the SD card interface circuit is connected with the central processing module and is externally connected with a storage device;

the OTG interface circuit is connected with the central processing module and is used for programming a system or carrying out USB communication;

the real-time clock module is connected with the central processing module and is used for providing real-time;

the power conversion circuit is respectively connected with the central processing module, the switching value input circuit, the switching value output circuit, the analog input circuit, the RS485 interface circuit, the RS232 interface circuit, the 100M Ethernet interface circuit, the mini-PCIE interface circuit, the SD card interface circuit, the OTG interface circuit and the real-time clock module and used for providing a driving power supply.

As the preferred technical scheme, the core processor of the central processing module is an NXP-imx6ul microprocessing unit.

As a preferred technical solution, the switching value input circuit includes 16 input channels, the switching value output circuit includes 4 output channels, and the analog input circuit includes 8 input channels; the switching value input circuit and the switching value output circuit are connected with the central processing module through an expansion I/O chip and then through a first IIC bus, and the model of the expansion I/O chip is CH 422; analog input circuit gathers the chip through the ADC earlier and is connected with central processing module through the SPI bus again, the analog signal is 4 ~ 20mA or 0 ~ 5V, the model that the chip was gathered to the ADC is ADS 1256.

As a preferable technical scheme, the RS485 interface circuit includes 2 paths of digital quantity acquisition interfaces for acquiring digital quantity signals of the gate pump, a TVS tube with model number of SMAJ5.0CA, an SP3485 signal conversion chip, and 2 paths of interfaces electrically connected with an intelligent gate pump control terminal expansion module; the TVS tube with the model number of SMAJ5.0CA is connected with the SP3485 signal conversion chip and used for realizing conversion between a TTL signal of the central processing module and a digital quantity signal of the gate pump.

As a preferred technical solution, the RS232 interface circuit realizes conversion between an external debugging device signal and a TTL signal of the central processing module through a MAX3232 signal conversion chip.

As a preferred technical solution, the 100M ethernet interface circuit includes an ethernet PHY layer chip of type LAN8720, which is connected to the central processing module through an RMII interface;

the mini-PCIE interface circuit transmits TTL signals and USB signals of the central processing module to an upper computer through a wireless communication module, and the wireless communication module comprises a 4G module, a 5G module and an NB module.

As a preferred technical solution, the SD card interface circuit includes an SD card seat and an SD card interface TVS transistor; the SD card socket generates an SD card signal after being connected with an SD card and transmits the SD card signal to the central processing module through the TVS tube of the SD card interface; the model of the SD card interface TVS tube is SWSRV 05-4.

As a preferred technical scheme, the OTG interface circuit includes a power switch chip, an OTG interface TVS tube and a micro USB interface, and data transmitted by the micro USB interface is transmitted to the central processing module through the OTG interface TVS tube; the power switch chip is used for switching a switch of a micro USB interface power supply; the model of the power switch chip is SY6280, and the model of the OTG interface TVS tube is SWSRV 05-4.

As a preferred technical solution, the real-time clock module is of an ISL1208, and is connected to the central processing module through a second IIC bus.

As a preferred technical solution, the power conversion circuit includes a module for converting direct current 12V into direct current 5V and a module for converting direct current 5V into direct current 3.3V; the model of the module for converting direct current 12V into direct current 5V is TPS54331, and the model of the module for converting direct current 5V into direct current 3.3V is TPS 54327.

Compared with the prior art, the utility model has the following advantages and beneficial effects:

(1) the utility model can realize high-speed and accurate control and scheduling of the dispersed small water conservancy facilities, and conveniently carry out combined scheduling of the gate pump group through an integrated algorithm and a control strategy; the utility model adopts modular design, is convenient and simple to install, is flexible to expand, can cascade at most 2 groups, can control 250 nodes of the gate pump, and can meet the requirements of most occasions.

(2) According to the utility model, data interaction is carried out on the operating condition of each gate pump facility through the network and the upper computer, the control algorithm of the related gate pump is integrated, a part of control strategies are operated on the terminal, the calculation amount of the upper computer is reduced, the intelligent degree is improved, and the defect that the daily maintenance workload of the existing gate pump control terminal based on the PLC is larger in the dispersed small water conservancy facility environment is overcome.

(3) The switching value input circuit and the switching value output circuit are connected with the central processing module through the expansion I/O chip and the IIC bus, so that the number of pins for controlling and acquiring external equipment by the central processing module is saved, and the purpose of optimizing circuit wiring is achieved;

(4) according to the utility model, the analog quantity signal is converted by the high-precision ADC acquisition chip with the model number of ADS1256, and the high-precision ADC acquisition chip is connected with the central processing module through the SPI bus, so that the analog-to-digital conversion precision is improved, and the purpose of accurately acquiring the analog quantity signal is achieved.

Drawings

Fig. 1 is a block diagram of an overall circuit structure of an intelligent brake pump control terminal according to the present invention;

FIG. 2 is a circuit diagram of an extended I/O converter circuit of the present invention, wherein FIG. 2(a) is a circuit diagram of an extended I/O chip U8, and FIG. 2(b) is a circuit diagram of an extended I/O chip U9;

FIG. 3 is a relay output circuit of the present invention;

FIG. 4 is a digital input circuit of the present invention;

FIG. 5 is a circuit diagram of an ADC acquisition chip in the utility model, wherein FIG. 5(a) is a circuit diagram of an operational amplifier U2;

FIG. 6 is an analog-to-digital conversion acquisition circuit of the present invention;

FIG. 7 is an RS485 interface circuit of the present invention;

FIG. 8 is an Ethernet interface circuit of the present invention;

FIG. 9 is a mini-PCIE interface circuit of the present invention;

FIG. 10 is an SD card interface circuit of the present invention;

FIG. 11 is an OTG interface circuit of the present invention;

FIG. 12 is a real time clock circuit of the present invention;

FIG. 13 is a circuit for converting DC 12V to DC 5V according to the present invention;

fig. 14 shows a power conversion circuit for converting dc 5V to dc 3.3V according to the present invention.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Examples

As shown in fig. 1, this embodiment provides an intelligent gate pump control terminal, which specifically includes a central processing module, 16 switching value input circuits, 4 switching value output circuits, 8 analog input circuits, 4 RS485 interface circuits, 1 RS232 interface circuit, 1 ethernet 100 interface circuit, 1 mini-PCIE interface circuit, 1 SD card interface circuit, 1 OTG interface circuit, 1 real-time clock module, and a power conversion circuit;

(1) the central processing module is used for managing and controlling the whole system;

further, the core processor of the central processing module is an NXP-imx6ull microprocessing unit.

(2) The switching value input circuit is connected with the central processing module and is used for collecting switching value signals of external equipment such as a liquid level meter and a limit switch and sending the switching value signals to the central processing module;

(3) the switching value output circuit is respectively connected with the central processing module and the gate pump and is used for outputting a switching value signal to drive the gate pump;

furthermore, the switching value input circuit and the switching value output circuit in (2) and (3) are connected with the central processing module through the expansion I/O chip and then the first IIC bus, so that the number of control and acquisition pins of external equipment by the central processing module is saved, and the purpose of optimizing circuit wiring is achieved; the model of the extended I/O chip is CH 422;

furthermore, as shown in fig. 2, the 5 pin SCL and the 6 pin SDA of the extended I/O chip with the model CH422 are IIC bus communication lines, and are connected to the central processing module for data interaction; as shown in FIG. 2(a), the extended I/O chip U8 is connected to 1-8 switching value input circuits, and as shown in FIG. 2(b), the extended I/O chip U9 is connected to 9-16 switching value input circuits and 1-4 switching value output circuits.

Further, as shown in the relay circuit of fig. 3, pin 1 of a photocoupler U3 with model TLP185 is pulled up to direct current 5V through a pull-up resistor; pin 2 of the photocoupler U3 is connected to an external device; pin 3 of the photoelectric coupler U3 is pulled down to the ground wire; pin 4 of the photoelectric coupler U3 is connected with a switching value acquisition pin of the expansion I/O chip and is pulled up to direct current 3.3V through a pull-up resistor.

Furthermore, as shown in fig. 4, pin 2 of the relay U4 is connected to pin 3 of the transistor Q1 through a current limiting resistor R12, and is also connected to pin 1 of the diode D1, pin 2 of the transistor Q1 is pulled down to ground, and pin 1 of the transistor Q1 is connected to the switching value control pin of the extended I/O chip; the 4 pin of the relay U4 is connected to a direct current 5V power supply, and is simultaneously connected with the 2 pin of a diode D1, wherein the diode D1 is used for freewheeling so as to protect the circuit; pins 1 and 3 of the relay U4 are connected to an external control device.

(4) The analog input circuit is connected with the central processing module and is used for acquiring analog signals of external equipment such as a water level meter, a hoist and the like and sending the analog signals to the central processing module;

further, analog input circuit gathers the chip through high accuracy ADC earlier and is connected with central processing module through the SPI bus again, the analog signal is 4 ~ 20mA or 0 ~ 5V, the model that high accuracy ADC gathered the chip is ADS 1256.

Further, as shown in fig. 5(a), pins 19 and 18 of a high-precision ADC acquisition chip U1 with the model number ADS1256 are respectively connected to two pins of a passive crystal oscillator X1 to provide a basic clock signal; as shown in fig. 5(b), the reference voltage signals of the 3 pin and the 4 pin of the acquisition chip U1 are generated by an operational amplifier U2 with model number LM 358. The analog quantity acquisition mode is characterized in that an analog quantity signal is converted by a high-precision ADC acquisition chip with the model number of ADS1256 and is connected with a central processing module through an SPI bus, so that the analog-to-digital conversion precision is improved, and the purpose of accurately acquiring the analog quantity signal is achieved;

furthermore, as shown in fig. 6, after the analog input signal current value is converted into a voltage value through the resistor R9, the voltage value is connected to the acquisition pin of the high-precision ADC acquisition chip U1 through the TVS tube VR1 with model number SMAJ5.0CA.

(5) The RS485 interface circuit is connected with the central processing module and is used for collecting digital quantity signals of external equipment such as an electromagnetic flowmeter, a serial port camera and the like and realizing module expansion (an intelligent brake pump control terminal expansion module);

further, the RS485 interface circuit includes 2 digital acquisition interfaces for acquiring digital signals of external devices, a TVS tube of model SMAJ5.0CA, an SP3485 signal conversion chip, and 2 interfaces electrically connected to the intelligent gate pump control terminal expansion module; the RS485 signal firstly passes through a TVS tube with the model number of SMAJ5.0CA, then is converted into a TTL signal through an SP3485 signal conversion chip and is sent to the central processing module.

Furthermore, as shown in fig. 7, pin 1 RO of an RS485 conversion chip U20 with model number SP3485 is connected to a serial port UART _ RXD pin of the central processing module, and is pulled up to direct current 3.3V through a pull-up resistor; a2 pin RE and a3 pin DE of the RS485 conversion chip U20 are simultaneously connected to a3 pin of a triode Q10 and are pulled up to direct current of 3.3V through a pull-up resistor; a pin 1 of the triode Q10 is connected with a serial port UART _ TXD pin of the central processing module and is pulled up to direct current of 3.3V through a pull-up resistor; a pin 2 of the triode Q10 is connected with a pin 4 DI of the RS485 conversion chip U20 and is pulled down to the ground wire; the TTL signal of the central processing module is converted by the RS485 conversion chip to generate an RS485 signal, and the RS485 signal is communicated with external equipment through a TVS tube VR3 with the model number of SMAJ5.0CA.

Furthermore, a TXD of a serial port UART in the RS485 circuit is connected with a base electrode of an NPN triode and is pulled up to 3.3V of direct current through a pull-up resistor, a collector electrode of the NPN triode is connected with a receiving and transmitting enabling pin in the RS485 chip and is pulled up to 3.3V of direct current through the pull-up resistor, an emitter electrode of the NPN triode is connected with a data input pin in the RS485 chip and is connected to a ground wire, and therefore data receiving and transmitting of the RS485 circuit are switched automatically;

(6) the RS232 interface circuit is connected with the central processing module and is used for communicating with external debugging equipment;

further, the RS232 interface circuit converts the TTL signal into an RS232 signal through a MAX3232 signal conversion chip.

(7) The 100M Ethernet interface circuit is connected with the central processing module and is connected to an upper computer through a wireless network communication module;

further, the 100M ethernet interface circuit includes an ethernet PHY layer chip of a type of LAN8720, and the ethernet PHY layer chip is connected to the central processing module through an RMII interface;

further, as shown in fig. 8, an ethernet RJ45 interface U5, model HR911105A, provides ethernet signals TX _ N, TX _ P, RX _ N, RX _ P to pins 21, 20, 23, 22, respectively, of an ethernet PHY chip U6, model LAN 8720A; the ethernet PHY chip U6 transmits signals of RST, MDIO, MDC, RXD0, RXD1, CRS _ DV, RXER, TXD0, TXD1, TXEN, INT, CLKIN of 15 pins, 12 pins, 13 pins, 8 pins, 7 pins, 11 pins, 10 pins, 17 pins, 18 pins, 16 pins, 14 pins, 5 pins to the central processing module through the RMII bus, respectively.

(8) The mini-PCIE interface circuit is connected with the central processing module and is connected to an upper computer in a wireless external connection mode;

further, the mini-PCIE interface circuit transmits a TTL signal and a USB signal of the central processing module to the upper computer through the wireless communication module, where the wireless communication module includes a 4G module, a 5G module, and an NB module.

Furthermore, as shown in fig. 9, pins 11, 13, 36, and 38 of the mini-PCIE interface CON8 are respectively connected to the central processing module, so as to implement transmission of UART _ TX, UART _ RX, and USB _ N, USB _ P signals; the 8 pins, 10 pins, 12 pins, 14 pins, and 16 pins of the mini-PCIE interface CON8 are respectively connected to the SIM card socket CON9, and provide VCC, RST, CLK, VPP, and I/O signals to the SIM card.

(9) The SD card interface circuit is connected with the central processing module and is externally connected with a storage device;

further, the SD card interface circuit includes an SD card seat and a TVS tube; the SD card socket generates an SD card signal after being connected with an SD card and transmits the SD card signal to the central processing module through the TVS tube of the SD card interface; the model of the SD card interface TVS tube is SWSRV 05-4.

Further, as shown in fig. 10, pins 1, 2, 3, 5, 7 and 8 of the SD card socket CON12 respectively provide DATA2, DATA3, CMD, CLK, DATA0 and DATA1 signals of the SDIO bus to the central processing module.

(10) The OTG interface circuit is connected with the central processing module and is used for programming a system or carrying out USB communication;

furthermore, the OTG interface circuit comprises a power switch chip, an OTG interface TVS tube and a micro USB interface, and data transmitted by the micro USB interface is transmitted to the central processing module through the OTG interface TVS tube; the power switch chip is used for switching a switch of a micro USB interface power supply; the model of the power switch chip is SY6280, and the model of the OTG interface TVS tube is SWSRV 05-4.

Furthermore, as shown in fig. 11, USB _ OTG device signals USB _ OTG _ N and USB _ OTG _ P are input to the central processing module from the micro USB interface through the TVS tube U13 with model number SWSRV05-4, and the TVS tube can effectively prevent overvoltage, overcurrent, and surge, and protect the input port from being damaged; when the USB _ OTG _ ID input signal is at a high level or is suspended, the triode Q2 is conducted, the power switch chip U11 with the model number of SY6280 is disabled, and the USB _ OTG device serves as a peripheral and does not increase a power supply to the outside; when the USB _ OTG _ ID input signal is at a low level, the triode Q2 is cut off, the power switch chip U11 with the model number of SY6280 is enabled, the USB _ OTG device serves as a host, direct current 5V is output from the pin 1 of the power switch chip U11, and power is supplied to external equipment after passing through the diode D2.

(11) The real-time clock module is connected with the central processing module and is used for providing real-time;

furthermore, the real-time clock module is of an ISL1208 model and is connected with the central processing module through a second IIC bus.

Further, as shown in fig. 12, pin 1X 1 and pin 2X 2 of the real-time clock chip U22 with model number ISL1208 are respectively connected to two pins of the passive crystal oscillator X2 to provide a basic clock signal; the 5-pin SDA and the 6-pin SCL of the ISL1208 are IIC bus communication lines and are connected to the central processing module for data interaction.

(12) The power conversion circuit is respectively connected with the central processing module, the switching value input circuit, the switching value output circuit, the analog input circuit, the RS485 interface circuit, the RS232 interface circuit, the 100M Ethernet interface circuit, the mini-PCIE interface circuit, the SD card interface circuit, the OTG interface circuit and the real-time clock module and used for providing a driving power supply.

Further, the power conversion circuit comprises a module for converting direct current 12V into direct current 5V and a module for converting direct current 5V into direct current 3.3V; the model of the direct current 12V to direct current 5V module is TPS54331, and the model of the direct current 5V to direct current 3.3V module is TPS 54327.

Further, as shown in fig. 13, a power conversion module U16 of the type TPS54331 converts direct current 12V into direct current 5V, a direct current 12V signal is input from a 2-pin VIN of the TPS54331, a direct current 5V signal is output from an 8-pin PH of the TPS54331 after the direct current 12V signal is converted, and the direct current 5V signal is provided to a power utilization module after being filtered by an inductor L1, an electrolytic capacitor EC1, and a capacitor C38, and a zener diode D3 is used for stabilizing voltage and protecting a circuit.

Further, as shown in fig. 14, a power conversion module U17 with a model number of TPS54327 converts dc 5V into dc 3.3V, a dc 3.3V signal is input from pin 8 VIN of TPS54327, and is converted to output a dc 3.3V signal from pin 6 SW of TPS54327, and the dc 3.3V signal is filtered by inductor L2, electrolytic capacitor EC4, and capacitor C47 to provide dc 3.3V to a power utilization module, and a zener diode D5 is used to stabilize voltage and protect the circuit.

The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims (10)

1. An intelligent gate pump control terminal is characterized by comprising a central processing module, a switching value input circuit, a switching value output circuit, an analog input circuit, an RS485 interface circuit, an RS232 interface circuit, a 100M Ethernet interface circuit, a mini-PCIE interface circuit, an SD card interface circuit, an OTG interface circuit, a real-time clock module and a power supply conversion circuit;

the switching value input circuit is connected with the central processing module and is used for acquiring switching value signals of the gate pump and sending the switching value signals to the central processing module;

the switching value output circuit is respectively connected with the central processing module and the gate pump and is used for outputting a switching value signal to drive the gate pump;

the analog input circuit is connected with the central processing module and is used for acquiring an analog signal of the gate pump and sending the analog signal to the central processing module;

the RS485 interface circuit is connected with the central processing module and is used for acquiring digital quantity signals of the gate pump and realizing module expansion;

the RS232 interface circuit is connected with the central processing module and is used for communicating with external debugging equipment;

the 100M Ethernet interface circuit is connected with the central processing module and is connected to an upper computer through a wireless network communication module;

the mini-PCIE interface circuit is connected with the central processing module and is connected to an upper computer in a wireless external connection mode;

the SD card interface circuit is connected with the central processing module and is externally connected with a storage device;

the OTG interface circuit is connected with the central processing module and is used for programming a system or carrying out USB communication;

the real-time clock module is connected with the central processing module and is used for providing real-time;

the power conversion circuit is respectively connected with the central processing module, the switching value input circuit, the switching value output circuit, the analog input circuit, the RS485 interface circuit, the RS232 interface circuit, the 100M Ethernet interface circuit, the mini-PCIE interface circuit, the SD card interface circuit, the OTG interface circuit and the real-time clock module and used for providing a driving power supply.

2. The intelligent brake pump control terminal of claim 1, wherein the core processor of the central processing module is an NXP-imx6ul micro-processing unit.

3. The intelligent brake pump control terminal of claim 1, wherein the switching value input circuit comprises 16 input channels, the switching value output circuit comprises 4 output channels, and the analog input circuit comprises 8 input channels; the switching value input circuit and the switching value output circuit are connected with the central processing module through an expansion I/O chip and then a first IIC bus, and the model of the expansion I/O chip is CH 422; analog input circuit gathers the chip through the ADC earlier and is connected with central processing module through the SPI bus again, the analog signal is 4 ~ 20mA or 0 ~ 5V, the model that the chip was gathered to the ADC is ADS 1256.

4. The intelligent brake pump control terminal of claim 1, wherein the RS485 interface circuit comprises 2 digital acquisition interfaces for acquiring digital signals of the brake pump, a TVS tube with model number of SMAJ5.0CA, a SP3485 signal conversion chip, and 2 interfaces electrically connected with an expansion module of the intelligent brake pump control terminal; the TVS tube with the model number of SMAJ5.0CA is connected with the SP3485 signal conversion chip and used for realizing conversion between a TTL signal of the central processing module and a digital quantity signal of the gate pump.

5. The intelligent gate pump control terminal of claim 1, wherein the RS232 interface circuit implements conversion between external debugging device signals and TTL signals of the central processing module through a MAX3232 signal conversion chip.

6. The intelligent gate control terminal according to claim 1, wherein the 100M ethernet interface circuit comprises an ethernet PHY layer chip of type LAN8720, the ethernet PHY layer chip being connected to the central processing module via an RMII interface;

the mini-PCIE interface circuit transmits TTL signals and USB signals of the central processing module to an upper computer through a wireless communication module, and the wireless communication module comprises a 4G module, a 5G module and an NB module.

7. The intelligent brake pump control terminal of claim 1, wherein the SD card interface circuit comprises an SD card socket and an SD card interface TVS tube; the SD card socket generates an SD card signal after being connected with an SD card and transmits the SD card signal to the central processing module through the TVS tube of the SD card interface; the model of the SD card interface TVS tube is SWSRV 05-4.

8. The intelligent gate pump control terminal of claim 1, wherein the OTG interface circuit comprises a power switch chip, an OTG interface TVS tube and a micro USB interface, and data transmitted by the micro USB interface is transmitted to the central processing module through the OTG interface TVS tube; the power switch chip is used for switching a switch of a micro USB interface power supply; the chip model of the power switch chip is SY6280, and the model of the OTG interface TVS tube is SWSRV 05-4.

9. The intelligent brake pump control terminal of claim 1, wherein the real-time clock module is of type ISL1208 and is connected to the central processing module via the second IIC bus.

10. The intelligent brake pump control terminal of claim 1, wherein the power conversion circuit comprises a dc 12V to dc 5V module and a dc 5V to dc 3.3V module; the model of the module for converting direct current 12V into direct current 5V is TPS54331, and the model of the module for converting direct current 5V into direct current 3.3V is TPS 54327.

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