CN216792714U - An intelligent gate pump control terminal - Google Patents

Abstract

The utility model discloses an intelligent brake pump control terminal, which comprises a central processing module, a switching value input circuit, a switching value output circuit, an analog input circuit, an RS485 interface circuit, an RS232 interface circuit, a 100M Ethernet interface circuit, a mini-PCIE interface circuit, an SD card interface circuit, an OTG interface circuit, a real-time clock module and a power supply conversion circuit, wherein the switching value input circuit is connected with the switching value output circuit; the central processing module and the power supply conversion circuit are respectively connected with other modules and circuits. The utility model can realize high-speed and accurate control and scheduling of the dispersed small water conservancy facilities, and conveniently carry out combined scheduling of the gate pump group through an integrated algorithm and a control strategy; and the modularized design is adopted, the installation is convenient and simple, the expansion is flexible, at most 2 groups of cascade connection can be realized, 250 nodes of the gate pump can be controlled, data interaction can be carried out with an upper computer through a network, a part of control strategies are operated on a terminal, the calculation amount of the upper computer is reduced, and the intelligent degree is improved.

Description

An intelligent gate pump control terminal

technical field

The utility model relates to the technical field of joint scheduling of gates and pumps in flood storage and detention areas, in particular to an intelligent gate-pump control terminal.

Background technique

At present, the known gate pump control terminal is controlled by PLC. By collecting the current gate water level, flow and other information, the upper computer exchanges information with the gate pump control terminal through the network, thereby controlling water conservancy facilities such as gates and pumping stations. However, for the gate and pump control of small reservoirs, rivers, canals, and enclosures, the PLC-based gate and pump control terminal has many mechanical and electrical accessories when controlling scattered small water conservancy facilities, and the daily maintenance workload is large. In addition, in the joint scheduling environment of the gate-pump group, the calculation amount of the upper computer is increased, and the degree of intelligence is low.

Utility model content

In order to overcome the defect that the existing PLC-based gate pump control terminal has a large daily maintenance workload in the environment of scattered small water conservancy facilities, the utility model provides an intelligent gate pump control terminal, which can pass the network according to the operation condition of each gate pump facility. Data exchange with the host computer, integrate the relevant gate pump control algorithms, run some control strategies on the terminal, reduce the computational load of the host computer, and improve the degree of intelligence.

In order to achieve the above object, the utility model adopts the following technical solutions:

The utility model provides an intelligent gate pump control terminal, comprising a central processing module, a switch quantity input circuit, a switch quantity output circuit, an analog quantity input circuit, an RS485 interface circuit, an RS232 interface circuit, a 100M Ethernet interface circuit, and a mini-PCIE Interface circuit, SD card interface circuit, OTG interface circuit, real-time clock module and power conversion circuit;

The switch quantity input circuit is connected with the central processing module, and is used to collect the switch quantity signal of the gate pump and send it to the central processing module;

The switch quantity output circuit is respectively connected with the central processing module and the gate pump, and is used for outputting the switch quantity signal to drive the gate pump;

The analog input circuit is connected to the central processing module for collecting the analog signal of the gate pump and sending it to the central processing module;

The RS485 interface circuit is connected with the central processing module, and is used to collect the digital signal of the gate pump and realize module expansion;

The RS232 interface circuit is connected with the central processing module for communicating with external debugging equipment;

The 100M Ethernet interface circuit is connected to the central processing module, and is connected to the upper computer through the wireless network communication module;

The mini-PCIE interface circuit is connected to the central processing module, and is connected to the upper computer through a wireless external connection;

The SD card interface circuit is connected with the central processing module, and is connected with an external storage device;

The OTG interface circuit is connected with the central processing module, and is used for programming the system or performing USB communication;

The real-time clock module is connected to the central processing module for providing real-time time;

The power conversion circuit is respectively connected with the central processing module, switch input circuit, switch output circuit, analog input circuit, RS485 interface circuit, RS232 interface circuit, 100M Ethernet interface circuit, mini-PCIE interface circuit and SD card interface circuit. , OTG interface circuit and real-time clock module connection to provide driving power.

As a preferred technical solution, the core processor of the central processing module is an NXP-imx6ull microprocessor unit.

As a preferred technical solution, the digital input circuit includes 16 input channels, the digital output circuit includes 4 output channels, and the analog input circuit includes 8 input channels; the digital input circuit and the switch The quantity output circuit is first connected to the central processing module through the extended I/O chip and then through the first IIC bus. The model of the extended I/O chip is CH422; the analog quantity input circuit first collects the chip through the ADC and then communicates with the CPU through the SPI bus. The central processing module is connected, the analog signal is 4-20mA or 0-5V, and the model of the ADC acquisition chip is ADS1256.

As a preferred technical solution, the RS485 interface circuit includes two digital acquisition interfaces for collecting digital signals of the gate pump, a TVS tube with a model of SMAJ5.0CA, an SP3485 signal conversion chip, and two channels with intelligent gate pump control The interface for the electrical connection of the terminal expansion module; the TVS tube of the model SMAJ5.0CA is connected with the SP3485 signal conversion chip, which is used to realize the conversion between the TTL signal of the central processing module and the digital signal of the gate pump.

As a preferred technical solution, the RS232 interface circuit realizes the conversion between the external debugging device signal and the TTL signal of the central processing module through the MAX3232 signal conversion chip.

As a preferred technical solution, the 100M Ethernet interface circuit includes an Ethernet PHY layer chip with a model of LAN8720, and the Ethernet PHY layer chip is connected to the central processing module through the RMII interface;

The mini-PCIE interface circuit transmits the TTL signal and the USB signal of the central processing module to the upper computer through the wireless communication module, and the wireless communication module includes a 4G module, a 5G module and an NB module.

As a preferred technical solution, the SD card interface circuit includes an SD card holder and an SD card interface TVS pipe; after the SD card holder is connected to the SD card, an SD card signal is generated, and is transmitted to the central processing module through the SD card interface TVS pipe; The model of the SD card interface TVS tube is SWSRV05-4.

As a preferred technical solution, the OTG interface circuit includes a power switch chip, an OTG interface TVS tube and a micro USB interface, and the data transmitted by the micro USB interface is transmitted to the central processing module through the OTG interface TVS tube; the power switch chip is used for switching. Micro USB interface power switch; the chip model of the power switch chip is SY6280, and the model of the OTG interface TVS tube is SWSRV05-4.

As a preferred technical solution, the model of the real-time clock module is ISL1208, which is connected to the central processing module through the second IIC bus.

As a preferred technical solution, the power conversion circuit includes a DC 12V to DC 5V module and a DC 5V to DC 3.3V module; the model of the DC 12V to DC 5V module is TPS54331, and the model of the DC 5V to DC 3.3V module is TPS54327 .

Compared with the prior art, the utility model has the following advantages and beneficial effects:

(1) The present utility model can realize the high-speed and accurate control and dispatch of scattered small water conservancy facilities, and at the same time, through the integrated algorithm and control strategy, the joint dispatch of the gate-pump group can be conveniently carried out; and the utility model adopts the modular design, and the installation is convenient. Simple, flexible expansion, can be cascaded up to 2 groups, can control 250 nodes of the gate pump, can meet the requirements of most occasions.

(2) The utility model conducts data exchange with the host computer through the network according to the operation situation of each gate pump facility, integrates the relevant gate pump control algorithms, runs part of the control strategy on the terminal, reduces the calculation amount of the host computer, and improves the degree of intelligence , to overcome the defect that the existing PLC-based gate pump control terminal has a large daily maintenance workload in the environment of scattered small water conservancy facilities.

(3) The switch quantity input circuit and switch quantity output circuit of the present utility model are connected with the central processing module through the expansion I/O chip and then through the IIC bus, which saves the control and collection pins of the external equipment by the central processing module, and achieves The purpose of optimizing circuit routing;

(4) The utility model converts analog signals through a high-precision ADC acquisition chip with a model of ADS1256, and connects the central processing module through the SPI bus, which improves the analog-to-digital conversion accuracy and achieves the purpose of accurately collecting analog signals.

Description of drawings

Fig. 1 is the overall circuit structure block diagram of a kind of intelligent gate pump control terminal described in the present utility model;

Fig. 2 is the extension I/O conversion circuit of the present utility model, wherein Fig. 2 (a) is the circuit diagram of extension I/O chip U8, Fig. 2 (b) is the circuit diagram of extension I/O chip U9;

Fig. 3 is the relay output circuit of the present utility model;

Fig. 4 is the digital quantity input circuit of the present utility model;

5 is an analog-to-digital conversion circuit of the present utility model, wherein FIG. 5(a) is a circuit diagram of an ADC acquisition chip, and FIG. 5(b) is a circuit diagram of an operational amplifier U2;

Fig. 6 is the analog-to-digital conversion acquisition circuit of the present utility model;

Fig. 7 is the RS485 interface circuit of the present utility model;

Fig. 8 is the Ethernet interface circuit of the present utility model;

Fig. 9 is the mini-PCIE interface circuit of the present invention;

Fig. 10 is the SD card interface circuit of the present invention;

Fig. 11 is the OTG interface circuit of the present utility model;

Fig. 12 is the real-time clock circuit of the present utility model;

Fig. 13 is the power conversion circuit of the present utility model from DC 12V to DC 5V;

FIG. 14 is a power conversion circuit of the present invention for converting DC 5V to DC 3.3V.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present application, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of this application.

Example

As shown in FIG. 1 , this embodiment provides an intelligent gate pump control terminal, which specifically includes a central processing module, 16 channels of digital input circuits, 4 channels of digital output circuits, 8 channels of analog input circuits, and 4 channels of RS485 interface circuits. , 1-way RS232 interface circuit, 1-way 100M Ethernet interface circuit, 1-way mini-PCIE interface circuit, 1-way SD card interface circuit, 1-way OTG interface circuit, 1-way real-time clock module and power conversion circuit;

(1) The central processing module is used to manage and control the entire system;

Further, the core processor of the central processing module is an NXP-imx6ull microprocessor unit.

(2) The digital input circuit is connected to the central processing module, and is used to collect digital signals including liquid level gauges, limit switches and other external devices and send them to the central processing module;

(3) The switching quantity output circuit is respectively connected with the central processing module and the gate pump, and is used for outputting the switching quantity signal to drive the gate pump;

Further, the switch quantity input circuit and switch quantity output circuit in (2) and (3) are first connected with the central processing module through the extended I/O chip and then through the first IIC bus, so as to save the central processing module on the external equipment. The number of control and acquisition pins to achieve the purpose of optimizing circuit wiring; the model of the extended I/O chip is CH422;

Further, as shown in Figure 2, the 5-pin SCL and 6-pin SDA of the extended I/O chip model CH422 are IIC bus communication lines, which are connected to the central processing module for data exchange; among them, Figure 2 ( As shown in a), the expansion I/O chip U8 is connected to 1 to 8 digital input circuits. As shown in Figure 2(b), the extended I/O chip U9 is connected to 9 to 16 digital input circuits and 1 to 4 channels. Switch output circuit.

Further, as shown in the relay circuit in Figure 3, the pin 1 of the optocoupler U3 of the model TLP185 is pulled up to DC 5V through the pull-up resistor; the pin 2 of the optocoupler U3 is connected to external equipment; the optocoupler The pin 3 of the photocoupler U3 is pulled down to the ground line; the pin 4 of the photocoupler U3 is connected to the switch value acquisition pin of the extended I/O chip, and is pulled up to DC 3.3V through the pull-up resistor.

Further, as shown in Figure 4, the 2-pin of the relay U4 is connected to the 3-pin of the transistor Q1 through the current limiting resistor R12, and is connected to the 1-pin of the diode D1 at the same time, and the 2-pin of the transistor Q1 is pulled down to the ground wire. , the 1 pin of the transistor Q1 is connected to the switch control pin of the expansion I/O chip; the 4 pin of the relay U4 is connected to the DC 5V power supply, and is connected to the 2 pin of the diode D1, wherein the diode D1 is used for continuous to protect the circuit; pin 1 and pin 3 of relay U4 are connected to external control equipment.

(4) The analog input circuit is connected to the central processing module, and is used to collect analog signals including water level gauges, hoists and other external equipment and send them to the central processing module;

Further, the analog input circuit is first connected to the central processing module through a high-precision ADC acquisition chip and then through the SPI bus, the analog signal is 4-20mA or 0-5V, and the model of the high-precision ADC acquisition chip is ADS1256.

Further, as shown in Figure 5(a), the 19-pin and 18-pin of the high-precision ADC acquisition chip U1 of the model ADS1256 are respectively connected to the two pins of the passive crystal oscillator X1 to provide the basic clock signal; As shown in Figure 5(b), the reference voltage signals of the 3-pin and 4-pin of the acquisition chip U1 are generated by an operational amplifier U2 whose model is LM358. The analog quantity acquisition method converts the analog quantity signal through the high-precision ADC acquisition chip model ADS1256, and connects the central processing module through the SPI bus to improve the analog-to-digital conversion accuracy and achieve the purpose of accurately collecting the analog quantity signal;

Further, as shown in Figure 6, after the current value of the analog input signal is converted into a voltage value through the resistor R9, it is connected to the acquisition pin of the high-precision ADC acquisition chip U1 through the TVS tube VR1 of the model SMAJ5.0CA.

(5) The RS485 interface circuit is connected with the central processing module, and is used to collect digital signals including external devices such as electromagnetic flowmeters, serial cameras, etc., and realize module expansion (intelligent gate pump control terminal expansion module);

Further, the RS485 interface circuit includes 2 digital acquisition interfaces for collecting digital signals from external equipment, a TVS tube with a model of SMAJ5.0CA, a SP3485 signal conversion chip, and 2 digital acquisition interfaces with the intelligent gate pump control terminal expansion module. Interface for electrical connection; RS485 signal first passes through TVS tube with model SMAJ5.0CA, and then is converted into TTL signal through SP3485 signal conversion chip and sent to the central processing module.

Further, as shown in Figure 7, the 1 pin RO of the RS485 conversion chip U20 with the model SP3485 is connected to the serial port UART_RXD pin of the central processing module, and pulled up to DC 3.3V through a pull-up resistor; the RS485 conversion chip U20 The 2-pin RE and the 3-pin DE are connected to the 3-pin of the transistor Q10 at the same time, and pulled up to DC 3.3V through the pull-up resistor; the 1-pin of the transistor Q10 is connected to the serial port UART_TXD pin of the central processing module, and the The pull-up resistor is pulled up to DC 3.3V; the 2-pin of the transistor Q10 is connected to the 4-pin DI of the RS485 conversion chip U20, and it is pulled down to the ground wire at the same time; the TTL signal of the central processing module is converted by the RS485 conversion chip to generate an RS485 signal, And communicate with external equipment through TVS tube VR3 whose model is SMAJ5.0CA.

Further, the TXD of the serial port UART in the RS485 circuit is connected to the base of the NPN transistor, and pulled up to DC 3.3V through a pull-up resistor, and the collector of the NPN transistor is connected to the RS485 chip. The resistor is pulled up to DC 3.3V, and the emitter of the NPN transistor is connected to the data input pin in the RS485 chip and connected to the ground wire to realize the RS485 circuit data sending and receiving self-switching;

(6) The RS232 interface circuit is connected to the central processing module for communicating with external debugging equipment;

Further, the RS232 interface circuit converts the TTL signal into the RS232 signal through the MAX3232 signal conversion chip.

(7) The 100M Ethernet interface circuit is connected with the central processing module, and is connected to the upper computer through the wireless network communication module;

Further, the 100M Ethernet interface circuit includes an Ethernet PHY layer chip with a model of LAN8720, and the Ethernet PHY layer chip is connected to the central processing module through an RMII interface;

Further, as shown in Figure 8, the Ethernet RJ45 interface U5 with the model HR911105A provides the Ethernet signals TX_N, TX_P, RX_N, RX_P respectively to the 21 pins, 20 pins, 23 pins, 22 pins; Ethernet PHY chip U6 connects 15 pins, 12 pins, 13 pins, 8 pins, 7 pins, 11 pins, 10 pins, 17 pins, 18-pin, 16-pin, 14-pin, 5-pin RST, MDIO, MDC, RXD0, RXD1, CRS_DV, RXER, TXD0, TXD1, TXEN, INT, CLKIN signals are transmitted to the central processing module.

(8) The mini-PCIE interface circuit is connected to the central processing module, and is connected to the host computer by wireless external connection;

Further, the mini-PCIE interface circuit transmits the TTL signal and the USB signal of the central processing module to the upper computer through a wireless communication module, and the wireless communication module includes a 4G module, a 5G module, and an NB module.

Further, as shown in Figure 9, pins 11, 13, 36, and 38 of the mini-PCIE interface CON8 are respectively connected to the central processing module to realize the transmission of UART_TX, UART_RX, USB_N, and USB_P signals; The 8-pin, 10-pin, 12-pin, 14-pin, and 16-pin of the mini-PCIE interface CON8 are respectively connected with the SIM card holder CON9, providing VCC, RST, CLK, VPP, I/O signals to the SIM card .

(9) The SD card interface circuit is connected to the central processing module, and an external storage device is connected;

Further, the SD card interface circuit includes an SD card holder and an SD card interface TVS tube; after the SD card holder is connected to the SD card, an SD card signal is generated, and is transmitted to the central processing module through the SD card interface TVS tube; the SD card The model of the card interface TVS tube is SWSRV05-4.

Further, as shown in Figure 10, pins 1, 2, 3, 5, 7, and 8 of the SD card socket CON12 respectively provide DATA2, DATA3, CMD, and CLK of the SDIO bus. , DATA0, DATA1 signals to the central processing module.

(10) The OTG interface circuit is connected with the central processing module, and is used for programming the system or carrying out USB communication;

Further, the OTG interface circuit includes a power switch chip, an OTG interface TVS tube and a micro USB interface, and the data transmitted by the micro USB interface is transmitted to the central processing module through the OTG interface TVS tube; the power switch chip is used to switch the micro USB interface. Power switch; the chip model of the power switch chip is SY6280, and the model of the OTG interface TVS tube is SWSRV05-4.

Further, as shown in Figure 11, the USB_OTG device signals USB_OTG_N and USB_OTG_P are input to the central processing module from the micro USB interface through the TVS tube U13 of the model SWSRV05-4. The TVS tube can effectively prevent overvoltage, overcurrent, and resist waves. surge to protect the input port from being damaged; when the USB_OTG_ID input signal is high level or floating, the transistor Q2 is turned on, and the power switch chip U11 of the model SY6280 is disabled. The USB_OTG device is used as a peripheral device and does not increase the power externally. ; When the USB_OTG_ID input signal is low level, the transistor Q2 is turned off, the power switch chip U11 of the model SY6280 is enabled, the USB_OTG device is used as the host, and the DC 5V is output from the 1 pin of the power switch chip U11, after the diode D2 Provides power to external devices.

(11) the real-time clock module is connected with the central processing module for providing real-time time;

Further, the model of the real-time clock module is ISL1208, and is connected to the central processing module through the second IIC bus.

Further, as shown in Figure 12, the 1 pin X1 and the 2 pin X2 of the real-time clock chip U22 of the model ISL1208 are respectively connected to the two pins of the passive crystal oscillator X2 to provide the basic clock signal; 5 of the ISL1208 The pin SDA and the 6-pin SCL are the IIC bus communication lines, which are connected to the central processing module for data exchange.

(12) The power conversion circuit is respectively connected with the central processing module, switch input circuit, switch output circuit, analog input circuit, RS485 interface circuit, RS232 interface circuit, 100M Ethernet interface circuit, mini-PCIE interface circuit, SD The card interface circuit, the OTG interface circuit and the real-time clock module are connected to provide driving power.

Further, the power conversion circuit includes a DC 12V to DC 5V module and a DC 5V to DC 3.3V module; the model of the DC 12V to DC 5V module is TPS54331, and the model of the DC 5V to DC 3.3V module is TPS54327.

Further, as shown in Figure 13, the power conversion module U16 of the model TPS54331 converts DC 12V to DC 5V, the DC 12V signal is input from the 2-pin VIN of the TPS54331, and after the conversion, the 8-pin PH of the TPS54331 outputs DC. The 5V signal is filtered by the inductor L1, the electrolytic capacitor EC1, and the capacitor C38 to provide DC 5V to the power module. The Zener diode D3 is used to stabilize the voltage and protect the circuit.

Further, as shown in Figure 14, the power conversion module U17 of the model TPS54327 converts DC 5V to DC 3.3V, and the DC 3.3V signal is input from the 8-pin VIN of the TPS54327, and converted from the 6-pin SW of the TPS54327. The output DC 3.3V signal can provide DC 3.3V to the power module after being filtered by the inductor L2, the electrolytic capacitor EC4 and the capacitor C47. The Zener diode D5 is used to stabilize the voltage and protect the circuit.

The above-mentioned embodiments are preferred embodiments of the present utility model, but the embodiments of the present utility model are not limited by the above-mentioned embodiments, and any other changes, modifications, and substitutions made without departing from the spirit and principle of the present utility model , combination and simplification, all should be equivalent replacement methods, which are all included in the protection scope of the present invention.

Claims (10)

1. An intelligent gate pump control terminal is characterized by comprising a central processing module, a switching value input circuit, a switching value output circuit, an analog input circuit, an RS485 interface circuit, an RS232 interface circuit, a 100M Ethernet interface circuit, a mini-PCIE interface circuit, an SD card interface circuit, an OTG interface circuit, a real-time clock module and a power supply conversion circuit;

the switching value input circuit is connected with the central processing module and is used for acquiring switching value signals of the gate pump and sending the switching value signals to the central processing module;

the switching value output circuit is respectively connected with the central processing module and the gate pump and is used for outputting a switching value signal to drive the gate pump;

the analog input circuit is connected with the central processing module and is used for acquiring an analog signal of the gate pump and sending the analog signal to the central processing module;

the RS485 interface circuit is connected with the central processing module and is used for acquiring digital quantity signals of the gate pump and realizing module expansion;

the RS232 interface circuit is connected with the central processing module and is used for communicating with external debugging equipment;

the 100M Ethernet interface circuit is connected with the central processing module and is connected to an upper computer through a wireless network communication module;

the mini-PCIE interface circuit is connected with the central processing module and is connected to an upper computer in a wireless external connection mode;

the SD card interface circuit is connected with the central processing module and is externally connected with a storage device;

the OTG interface circuit is connected with the central processing module and is used for programming a system or carrying out USB communication;

the real-time clock module is connected with the central processing module and is used for providing real-time;

the power conversion circuit is respectively connected with the central processing module, the switching value input circuit, the switching value output circuit, the analog input circuit, the RS485 interface circuit, the RS232 interface circuit, the 100M Ethernet interface circuit, the mini-PCIE interface circuit, the SD card interface circuit, the OTG interface circuit and the real-time clock module and used for providing a driving power supply.

2. The intelligent brake pump control terminal of claim 1, wherein the core processor of the central processing module is an NXP-imx6ul micro-processing unit.

3. The intelligent brake pump control terminal of claim 1, wherein the switching value input circuit comprises 16 input channels, the switching value output circuit comprises 4 output channels, and the analog input circuit comprises 8 input channels; the switching value input circuit and the switching value output circuit are connected with the central processing module through an expansion I/O chip and then a first IIC bus, and the model of the expansion I/O chip is CH 422; analog input circuit gathers the chip through the ADC earlier and is connected with central processing module through the SPI bus again, the analog signal is 4 ~ 20mA or 0 ~ 5V, the model that the chip was gathered to the ADC is ADS 1256.

4. The intelligent brake pump control terminal of claim 1, wherein the RS485 interface circuit comprises 2 digital acquisition interfaces for acquiring digital signals of the brake pump, a TVS tube with model number of SMAJ5.0CA, a SP3485 signal conversion chip, and 2 interfaces electrically connected with an expansion module of the intelligent brake pump control terminal; the TVS tube with the model number of SMAJ5.0CA is connected with the SP3485 signal conversion chip and used for realizing conversion between a TTL signal of the central processing module and a digital quantity signal of the gate pump.

5. The intelligent gate pump control terminal of claim 1, wherein the RS232 interface circuit implements conversion between external debugging device signals and TTL signals of the central processing module through a MAX3232 signal conversion chip.

6. The intelligent gate control terminal according to claim 1, wherein the 100M ethernet interface circuit comprises an ethernet PHY layer chip of type LAN8720, the ethernet PHY layer chip being connected to the central processing module via an RMII interface;

the mini-PCIE interface circuit transmits TTL signals and USB signals of the central processing module to an upper computer through a wireless communication module, and the wireless communication module comprises a 4G module, a 5G module and an NB module.

7. The intelligent brake pump control terminal of claim 1, wherein the SD card interface circuit comprises an SD card socket and an SD card interface TVS tube; the SD card socket generates an SD card signal after being connected with an SD card and transmits the SD card signal to the central processing module through the TVS tube of the SD card interface; the model of the SD card interface TVS tube is SWSRV 05-4.

8. The intelligent gate pump control terminal of claim 1, wherein the OTG interface circuit comprises a power switch chip, an OTG interface TVS tube and a micro USB interface, and data transmitted by the micro USB interface is transmitted to the central processing module through the OTG interface TVS tube; the power switch chip is used for switching a switch of a micro USB interface power supply; the chip model of the power switch chip is SY6280, and the model of the OTG interface TVS tube is SWSRV 05-4.

9. The intelligent brake pump control terminal of claim 1, wherein the real-time clock module is of type ISL1208 and is connected to the central processing module via the second IIC bus.

10. The intelligent brake pump control terminal of claim 1, wherein the power conversion circuit comprises a dc 12V to dc 5V module and a dc 5V to dc 3.3V module; the model of the module for converting direct current 12V into direct current 5V is TPS54331, and the model of the module for converting direct current 5V into direct current 3.3V is TPS 54327.

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