CN216771830U - Super capacitor power-down detection system - Google Patents
Super capacitor power-down detection system Download PDFInfo
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- CN216771830U CN216771830U CN202220072523.7U CN202220072523U CN216771830U CN 216771830 U CN216771830 U CN 216771830U CN 202220072523 U CN202220072523 U CN 202220072523U CN 216771830 U CN216771830 U CN 216771830U
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- 239000003990 capacitor Substances 0.000 title claims abstract description 56
- 238000001514 detection method Methods 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000001105 regulatory effect Effects 0.000 claims description 16
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Abstract
The utility model discloses a super capacitor power failure detection system, which comprises: the power failure detection circuit comprises a super capacitor, a power failure detection circuit and a CPU; the input end of the power failure detection circuit is connected with the output end of the super capacitor, and the output end of the power failure detection circuit is connected with a GPIO pin of the CPU; the power failure detection circuit responds to a preset voltage threshold value of the super capacitor, and the CPU receives and processes a level signal sent by the power failure detection circuit. And the CPU receives and processes the high level signal and the low level signal sent by the power failure detection circuit. The circuit of the system is simple, the occupied hardware resources are few, the circuit is easy to replace components, the device cost is low, different super capacitors can be matched according to requirements for detection, and the system is convenient and practical.
Description
Technical Field
The utility model belongs to the field of super capacitors, and particularly relates to a super capacitor power failure detection system.
Background
For a device or equipment, when the device or equipment works normally, all parts operate normally and belong to a normal operation state; when the super capacitor or the power supply and the like are under-voltage, an abnormal working state occurs. At this time, a power down detection circuit is required to detect whether it is in such a state, and thereby to give a signal to terminate or take other measures against such a state. The long-time undervoltage can cause various damages to the device or equipment, such as damage to components, failure of the device or equipment to work normally, and the like. Some devices or equipment are equipped with a super capacitor, and the voltage state of the super capacitor needs to be detected.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problems in the background technology and provide a super capacitor power failure detection system.
In order to solve the technical problem, the technical scheme of the utility model is as follows:
a super capacitor power down detection system comprising: the power failure detection circuit comprises a super capacitor, a power failure detection circuit and a CPU; the input end of the power failure detection circuit is connected with the output end of the super capacitor, and the output end of the power failure detection circuit is connected with a GPIO pin of the CPU;
and the power failure detection circuit responds to a preset voltage threshold value of the super capacitor, and the CPU receives and processes the level signal sent by the power failure detection circuit.
It can be understood that: and determining whether the triode is conducted or not according to the voltage regulated by the voltage regulating resistor. When the voltage of the super capacitor is greater than a set threshold value, the triode is not conducted, and a collector outputs a high-level signal; when the voltage of the super capacitor is smaller than a set threshold, the triode is conducted, and a collector outputs a low-level signal; correspondingly, the signal is transmitted to the CPU, the CPU processes the received signal, and an alarm signal is sent out when the voltage is undervoltage.
Further, the CPU receives and processes the high level signal and the low level signal sent by the power failure detection circuit.
Further, the power down detection circuit includes: the circuit comprises a TL431 chip U7, a current-limiting resistor R53, a voltage-regulating resistor R52, a voltage-regulating resistor R57, a voltage-regulating resistor R61, a voltage-regulating resistor R63, a diode D1, a resistor R51, a resistor R55, a resistor R56, a resistor R58, a capacitor C36, a triode Q2 and a capacitor C43;
one end of the current-limiting resistor R53 is connected with the output end of the super capacitor, the other end of the current-limiting resistor R53 is connected with one end of a voltage-regulating resistor R52 and the 1 port of a TL431 chip U7, the other end of the voltage-regulating resistor R52 is connected with one end of a voltage-regulating resistor R57, the other end of the voltage-regulating resistor R57 is connected with the 2 ports of one end of a voltage-regulating resistor R61 and a TL431 chip U7, the other end of the voltage-regulating resistor R61 is connected with one end of a voltage-regulating resistor R63, the other end of the voltage-regulating resistor R63 is connected with the 3 port of the TL431 chip U7 and one end of a resistor R58 and one end of a diode D1, the other end of the resistor R58 is grounded, the other end of the diode D1 is connected with one end of a resistor R55, the other end of the resistor R55 is connected with one end of a capacitor C36 and one end of a resistor R56, the other end of the capacitor C36 is grounded, the other end of the resistor R56 is connected with the base of a transistor Q2, the emitting electrode of triode Q2 is grounded, the collecting electrode of triode Q2 connects the GPIO pin of CPU, one end of resistance R51 is connected with power VCC, another end of resistance R51 connects the collecting electrode of triode Q2, one end of electric capacity C43 connects the collecting electrode of triode Q2, the other end of electric capacity C43 is grounded.
Further, the current limiting resistor R53 limits the current flowing from the super capacitor to the power down detection circuit.
Further, the voltage regulating resistor R52, the voltage regulating resistor R57, the voltage regulating resistor R61 and the voltage regulating resistor R63 jointly regulate the voltage on the TL431 chip U7; and simultaneously, jointly determining the power-down threshold of the super capacitor.
Further, the CPU adopts a singlechip.
Compared with the prior art, the utility model has the advantages that: the circuit of the system is simple, the occupied hardware resources are few, the circuit is easy to replace components, the device cost is low, different super capacitors can be matched according to requirements for detection, and the system is convenient and practical.
Drawings
FIG. 1 is a system block diagram of a super capacitor power-down detection system according to the present invention;
FIG. 2 is a power down detection circuit diagram of a super capacitor power down detection system of the present invention;
FIG. 3 is a diagram of a charging process of a super capacitor;
FIG. 4 is a diagram of the discharge process of the super capacitor.
Detailed Description
The following describes embodiments of the present invention with reference to examples:
it should be noted that the structures, proportions, sizes, and the like shown in the specification are only used for matching with the contents disclosed in the specification, so that those skilled in the art can understand and read the contents, and do not limit the practical limitations of the present invention, and any modifications of the structures, changes of the proportion relation, or adjustments of the sizes, should fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention.
In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
The first embodiment is as follows:
as shown in fig. 1, a super capacitor power down detection system includes: the power failure detection circuit comprises a super capacitor, a power failure detection circuit and a CPU; the input end of the power failure detection circuit is connected with the output end of the super capacitor, and the output end of the power failure detection circuit is connected with a GPIO pin of the CPU;
the power failure detection circuit responds to a preset voltage threshold value of the super capacitor, and the CPU receives and processes a level signal sent by the power failure detection circuit.
It can be understood that: and determining whether the triode is conducted or not according to the voltage regulated by the voltage regulating resistor. When the voltage of the super capacitor is greater than a set threshold value, the triode is not conducted, and a collector outputs a high-level signal; when the voltage of the super capacitor is smaller than a set threshold, the triode is conducted, and a collector outputs a low-level signal; correspondingly, the signal is transmitted to the CPU, the CPU processes the received signal, and an alarm signal is sent out when the voltage is undervoltage.
Further, the CPU receives and processes the high level signal and the low level signal sent by the power failure detection circuit.
Further, as shown in fig. 2, the power down detection circuit includes: a TL431 chip U7, a current-limiting resistor R53, a voltage-regulating resistor R52, a voltage-regulating resistor R57, a voltage-regulating resistor R61, a voltage-regulating resistor R63, a diode D1, a resistor R51, a resistor R55, a resistor R56, a resistor R58, a capacitor C36, a triode Q2 and a capacitor C43;
the utility model discloses a super capacitor's output is connected to current-limiting resistor R53's an end, current-limiting resistor R53's the other end connects simultaneously at voltage-regulating resistor R52's one end and TL431 chip U7's 1 port, voltage-regulating resistor R52's the other end connects voltage-regulating resistor R57's one end simultaneously, voltage-regulating resistor R57's the other end connects simultaneously at voltage-regulating resistor R61's one end and TL431 chip U7's 2 ports, voltage-regulating resistor R61's the other end connects voltage-regulating resistor R63's one end, voltage-regulating resistor R63's the other end connects simultaneously at TL431 chip U7's 3 ports and resistance R58's one end and diode D1's one end, resistance R58's the other end ground connection, diode D1's the other end connects resistance R55's one end, resistance R55's the other end connects simultaneously electric capacity C36's one end and resistance R56's one end, electric capacity C36's the other end ground, resistance R56's the other end termination is Q2's base, the emitting electrode of triode Q2 is grounded, the collecting electrode of triode Q2 connects the GPIO pin of CPU, one end of resistance R51 is connected with power VCC, another end of resistance R51 connects the collecting electrode of triode Q2, one end of electric capacity C43 connects the collecting electrode of triode Q2, the other end of electric capacity C43 is grounded.
Further, the current limiting resistor R53 limits the current flowing from the super capacitor to the power down detection circuit.
Further, the voltage regulating resistor R52, the voltage regulating resistor R57, the voltage regulating resistor R61 and the voltage regulating resistor R63 jointly regulate the voltage on the TL431 chip U7; and simultaneously, jointly determining the power-down threshold of the super capacitor.
Further, the CPU adopts a singlechip.
Example two:
as shown in fig. 3 and 4, wherein the coordinates: "1" represents a high level, "0" represents a low level;
fig. 3 shows the charging process of the super capacitor, with the voltage going from low to high. When the voltage of the super capacitor is smaller than a set threshold value, the circuit outputs a high level signal under the action of a pull-up level, and the high level signal is fed back to a GPIO port of the single chip microcomputer to be 1; when the voltage of the super capacitor is larger than the set threshold value, the triode Q2 is conducted, the circuit outputs a low level signal, and the low level signal is fed back to the GPIO port of the single chip microcomputer to be 0.
The discharging process is the reverse of the charging process.
While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Many other changes and modifications can be made without departing from the spirit and scope of the utility model. It is to be understood that the utility model is not to be limited to the specific embodiments, but only by the scope of the appended claims.
Claims (6)
1. A super capacitor power down detection system, comprising: the power failure detection circuit comprises a super capacitor, a power failure detection circuit and a CPU; the input end of the power failure detection circuit is connected with the output end of the super capacitor, and the output end of the power failure detection circuit is connected with a GPIO pin of the CPU;
the power failure detection circuit responds to a preset voltage threshold value of the super capacitor, and the CPU receives and processes a level signal sent by the power failure detection circuit.
2. The supercapacitor power-down detection system according to claim 1, wherein the CPU receives and processes a high-level signal and a low-level signal sent by the power-down detection circuit.
3. The supercapacitor power down detection system according to claim 1, wherein the power down detection circuit comprises: a TL431 chip U7, a current-limiting resistor R53, a voltage-regulating resistor R52, a voltage-regulating resistor R57, a voltage-regulating resistor R61, a voltage-regulating resistor R63, a diode D1, a resistor R51, a resistor R55, a resistor R56, a resistor R58, a capacitor C36, a triode Q2 and a capacitor C43;
one end of the current-limiting resistor R53 is connected with the output end of the super capacitor, the other end of the current-limiting resistor R53 is connected with one end of a voltage-regulating resistor R52 and the 1 port of a TL431 chip U7, the other end of the voltage-regulating resistor R52 is connected with one end of a voltage-regulating resistor R57, the other end of the voltage-regulating resistor R57 is connected with the 2 ports of one end of a voltage-regulating resistor R61 and a TL431 chip U7, the other end of the voltage-regulating resistor R61 is connected with one end of a voltage-regulating resistor R63, the other end of the voltage-regulating resistor R63 is connected with the 3 port of the TL431 chip U7 and one end of a resistor R58 and one end of a diode D1, the other end of the resistor R58 is grounded, the other end of the diode D1 is connected with one end of a resistor R55, the other end of the resistor R55 is connected with one end of a capacitor C36 and one end of a resistor R56, the other end of the capacitor C36 is grounded, the other end of the resistor R56 is connected with the base of a transistor Q2, the emitting electrode of triode Q2 is grounded, the collecting electrode of triode Q2 connects the GPIO pin of CPU, one end of resistance R51 is connected with power VCC, another end of resistance R51 connects the collecting electrode of triode Q2, one end of electric capacity C43 connects the collecting electrode of triode Q2, the other end of electric capacity C43 is grounded.
4. The system according to claim 3, wherein the current limiting resistor R53 limits the current flowing from the super capacitor to the power down detection circuit.
5. The supercapacitor power failure detection system according to claim 3, wherein the voltage regulating resistor R52, the voltage regulating resistor R57, the voltage regulating resistor R61 and the voltage regulating resistor R63 jointly regulate the voltage on the TL431 chip U7; and simultaneously, jointly determining the power-down threshold of the super capacitor.
6. The supercapacitor power failure detection system according to any one of claims 1 to 3, wherein the CPU employs a single chip microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220072523.7U CN216771830U (en) | 2022-01-12 | 2022-01-12 | Super capacitor power-down detection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220072523.7U CN216771830U (en) | 2022-01-12 | 2022-01-12 | Super capacitor power-down detection system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216771830U true CN216771830U (en) | 2022-06-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220072523.7U Active CN216771830U (en) | 2022-01-12 | 2022-01-12 | Super capacitor power-down detection system |
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| Country | Link |
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| CN (1) | CN216771830U (en) |
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- 2022-01-12 CN CN202220072523.7U patent/CN216771830U/en active Active
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A Supercapacitor Power-Down Detection System Effective date of registration: 20220829 Granted publication date: 20220617 Pledgee: Xi'an Caijin Financing Guarantee Co.,Ltd. Pledgor: SHAANXI ZHONGXING XIANGLIN ELECTRONIC TECHNOLOGY CO.,LTD. Registration number: Y2022610000537 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20231016 Granted publication date: 20220617 Pledgee: Xi'an Caijin Financing Guarantee Co.,Ltd. Pledgor: SHAANXI ZHONGXING XIANGLIN ELECTRONIC TECHNOLOGY CO.,LTD. Registration number: Y2022610000537 |
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| CP03 | Change of name, title or address |
Address after: 710086 9th Floor, Building 10, Qihang Xinyuan, Jianzhang Road Street, Fengdong New City, Xixian New District, Xi'an City, Shaanxi Province Patentee after: Shaanxi Huatian Juneng Technology Co.,Ltd. Address before: 710086 room 505, building 4, Zhongxing dark blue Technology Industrial Park, No. 2296, Keyuan 4th Road, Fengdong new town, Xixian New District, Xi'an City, Shaanxi Province Patentee before: SHAANXI ZHONGXING XIANGLIN ELECTRONIC TECHNOLOGY CO.,LTD. |