CN216721352U - Voltage mode pre-emphasis equalization circuit, SerDes transmitter and chip - Google Patents

Voltage mode pre-emphasis equalization circuit, SerDes transmitter and chip Download PDF

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CN216721352U
CN216721352U CN202220108056.9U CN202220108056U CN216721352U CN 216721352 U CN216721352 U CN 216721352U CN 202220108056 U CN202220108056 U CN 202220108056U CN 216721352 U CN216721352 U CN 216721352U
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丁浩
龚广伟
刘继斌
刘培国
黄贤俊
徐延林
刘晨曦
查淞
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National University of Defense Technology
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Abstract

The utility model discloses a voltage mode pre-emphasis equalization circuit, a SerDes transmitter and a chip, wherein the circuit adopts a voltage mode framework and comprises the following components: a driver circuit for delivering an input signal to a channel; and the pre-emphasis circuit is used for enhancing the high-frequency component on the premise of not compressing the low-frequency component. The utility model adopts a pre-emphasis scheme, improves the absolute amplitude of the high-frequency component in a pulse superposition mode, realizes the decoupling of the equilibrium strength and the output oscillation amplitude, and ensures that the adjustment of the high-frequency component does not influence the output oscillation amplitude. The utility model can eliminate the influence of the equalizing intensity on the output swing in the de-emphasis equalization, avoid the restriction of the output swing on the linearity, and reduce the dependence on the tail current to reduce the power consumption.

Description

Voltage mode pre-emphasis equalization circuit, SerDes transmitter and chip
Technical Field
The utility model relates to the technical field of equalization circuits, in particular to a voltage mode pre-emphasis equalization circuit, a SerDes transmitter and a chip.
Background
A SerDes (Serializer-Deserializer) is widely used in the fields of data centers and high-performance computing, and is responsible for high-speed data interaction between processors and memories. The transmitter is located at the SerDes transmitting end and is used to convert the low-speed parallel signal into a high-speed serial signal, which is then transmitted to the channel. Due to the non-ideal effects of the skin effect, the dielectric loss and the like of the transmission channel, the high-frequency component of the signal is attenuated, the quality of the signal is deteriorated, and the error rate is increased. To ensure the quality of signal transmission, the transmitter usually equalizes the signal before transmission, i.e. increases the high frequency components in advance to counteract the channel attenuation.
Transmitter equalization typically employs a Feed-Forward equalization (FFE) architecture, as shown in fig. 1. It essentially corresponds to a Finite Impulse Response Filter (FIR), in which the input signal is delayed several times (delay time T) during operation, and the delayed data are summed with different weights (weight α)-1、α0、α1……αn) The number of summed data streams is called the number of taps, and the length of the delay is called the tap interval. The conventional structure compensates for channel attenuation by adjusting the number of taps and weights, but since the tap Interval is a fixed Unit symbol length of 1UI (Unit Interval, symbol length), only channel attenuation within the nyquist band can be compensated for regardless of the adjustment.
To solve the problems mentioned aboveIn question, some have studied feed forward equalizers based on fractional symbol tap spacing, the structure of which is shown in fig. 2. Compared with the conventional structure shown in FIG. 1, the main difference is that the tap spacing is adjustable fractional symbol spacing (0 < β ≦ 1). Simulation analysis proves that the frequency compensation range of the structure is fNyquistAnd/beta, the compensation range far exceeding the Nyquist frequency can be obtained by adjusting beta.
The Current feed-forward equalizer based on the partial symbol tap spacing is mainly based on the CML architecture (Current-Mode Logic), and for convenience of description, a two-tap example is taken as an example, and the circuit structure of the Current feed-forward equalizer is shown in fig. 3. The circuit consists of 1 main tap and 1 Post tap, RLVop/Von is a differential output end for a load resistor, D1p/D1n is a differential input signal of a Post tap, D0p/D0n is an input signal of a main tap, and the ratio of tail currents of the main tap and the Post tap is (1-alpha)1)/α1. The input signal of the Post tap lags behind the main tap β T (T ═ 1UI, 0 < β ≦ 1), and the delay is generated by the delay unit, as shown in fig. 4. The control of the delay unit can realize the adjustment of the tap interval, thereby obtaining different frequency compensation ranges.
The structure shown in fig. 3 has the following disadvantages: (1) as shown in fig. 5, de-emphasis equalization is adopted, that is, the relative amplitude of the high-frequency component is increased by compressing the low-frequency component, the stronger the equalization intensity is, the more the low-frequency component is compressed, the smaller the signal swing amplitude is, and the signal quality will be deteriorated if the low-frequency component is severe; (2) for a signal adopting multi-level modulation, the change of the output swing amplitude can influence the tail current through the channel length modulation effect, and the changed tail current can cause the fluctuation of the signal level, so that the linearity is deteriorated and the signal-to-noise ratio is reduced; (3) each tap corresponds to a tail current source, and the power consumption is high.
SUMMERY OF THE UTILITY MODEL
Aiming at the problems of the prior art in the Fractional-Spaced FFE based on the CML framework, the utility model provides a voltage modulus pre-emphasis equalization circuit, a SerDes transmitter and a chip, aiming at eliminating the influence of the equalization intensity in de-emphasis equalization on the output swing amplitude, avoiding the restriction of the output swing amplitude on the linearity, and reducing the dependence on the tail current to reduce the power consumption.
In order to achieve the purpose, the utility model adopts the technical scheme that:
in one aspect, the present invention provides a voltage-mode pre-emphasis equalization circuit, where the circuit adopts a voltage-mode architecture, and the voltage-mode pre-emphasis equalization circuit includes:
a driver circuit for delivering an input signal to a channel;
and the pre-emphasis circuit is used for enhancing the high-frequency component on the premise of not compressing the low-frequency component.
In another aspect, the present invention provides a SerDes transmitter comprising an equalization circuit that is any of the voltage-mode pre-emphasis equalization circuits described above.
In another aspect, the present invention provides a chip comprising any one of the voltage modulo pre-emphasis equalization circuits described above.
The utility model adopts a voltage mode framework, reduces the dependence on a current source and reduces the power consumption compared with a current mode framework. The pre-emphasis circuit of the utility model directly superposes high-frequency components on the original signals, and the absolute value of the high-frequency components is added; conventional de-emphasis circuits boost the "relative amplitude" of the high frequency components by compressing the low frequency components without altering the high frequency components. Compared with the prior art, the utility model has the following beneficial technical effects:
1. compared with a feedforward equalizer (Fractional-spaced FFE) based on partial symbol tap spacing in a CML architecture, the utility model has the advantage that the equalization strength does not influence the output swing. The concrete expression is as follows: compared with the conventional CML framework which adopts a de-emphasis scheme and improves the relative amplitude of a high-frequency component in a mode of compressing a low-frequency component, the utility model adopts a pre-emphasis scheme and improves the absolute amplitude of the high-frequency component in a mode of overlapping pulses, thereby realizing the decoupling of the balanced strength and the output swing amplitude and ensuring that the adjustment of the high-frequency component does not influence the output swing amplitude.
2. Compared with the CML framework Fractional-Spaced FFE, the utility model has the advantage of low power consumption. The concrete expression is as follows: unlike the current CML architecture Fractional-Spaced FFE which generates an output swing by generating a voltage drop in a load circuit through a tail current, the output swing of the present invention is VDD/2 and is only related to a power supply voltage. When the same swing is output, the power consumption required by the utility model is only 1/4 of the CML framework Fractional-Spaced FFE, and the power consumption is obviously reduced.
3. Compared with the CML framework Fractional-Spaced FFE, the utility model has the advantage of high output linearity under multi-level modulation. The concrete points are as follows: different from the CML framework Fractional-Spaced FFE which realizes different output levels by changing the distribution of tail current in the load resistor, the utility model generates different output levels by a resistor voltage division mode, and the interval between the levels is only related to voltage, thereby avoiding the problem of linearity deterioration caused by channel length modulation effect.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a diagram of a conventional feed forward equalizer structure;
FIG. 2is a diagram of a prior art feed-forward equalizer structure based on partial symbol tap spacing;
FIG. 3is a circuit diagram of a prior art partial symbol tap spacing based feed forward equalizer based CML architecture;
FIG. 4 is a schematic diagram of delay elements for generating a delay in a partial symbol tap spacing based feed forward equalizer of the prior art CML-based architecture of FIG. 3;
FIG. 5 is a waveform diagram of an output signal of the prior art partial symbol tap spacing based feed forward equalizer based on the CML architecture of FIG. 3;
FIG. 6 is a schematic structural view of example 1 of the present invention;
fig. 7 is a control signal generation circuit diagram according to embodiment 1 of the present invention;
FIG. 8 is a timing diagram of control signals according to embodiment 1 of the present invention;
FIG. 9 is a waveform diagram of an output according to embodiment 1 of the present invention;
FIG. 10 is a schematic structural view of example 2 of the present invention;
fig. 11 is a control signal generation circuit diagram according to embodiment 2 of the present invention;
FIG. 12 is a timing chart of control signals according to embodiment 2 of the present invention;
FIG. 13 is a waveform diagram of an output according to embodiment 2 of the present invention;
the objects, features and advantages of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the description in the present invention as referring to "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In addition, the technical solutions in the embodiments of the present invention may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination of technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
In order to solve the problems faced by the conventional CML architecture-based Fractional-Spaced FFE, the utility model provides a voltage mode pre-emphasis equalization circuit, which is a pre-emphasis feed-forward equalization structure of a voltage mode architecture and aims to eliminate the influence of equalization strength on output swing amplitude in de-emphasis equalization, avoid the restriction of the output swing amplitude on linearity and reduce the dependence on tail current so as to reduce power consumption. The pre-emphasis circuit of the utility model directly superposes high-frequency components on the original signals, and the absolute value of the high-frequency components is added; conventional de-emphasis circuits boost the "relative amplitude" of the high frequency components by compressing the low frequency components without altering the high frequency components.
Referring to fig. 6 to 9, a voltage-mode pre-emphasis equalization circuit according to an embodiment of the present invention provides a circuit structure when NRZ modulation (Non-return-Zero) is used, and the circuit uses a voltage-mode architecture, so that dependence on a current source is reduced and power consumption is reduced compared with a current-mode architecture. In particular, it consists of a drive unit and a pre-emphasis unit.
The input signals include input signals Vip and Vin, and the input signals Vip and Vin are differential input signals. The circuit comprises a first inverter I1, a second inverter I2, a first resistor R1, a second resistor R2 and a load 2RLConstituting a drive unit, load 2RLThe two ends are differential output ends. The driving unit is used for transmitting the input signals Vip and Vin to the channel. The input signal Vip is input from the first inverter I1, the first inverter I1 is connected to a first terminal of the first resistor R1, a second terminal of the first resistor R1 is connected to a first terminal of the load, the input signal Vin is input from the second inverter I2, the second inverter I2 is connected to a first terminal of the second resistor R2, and a second terminal of the second resistor R2 is connected to a second terminal of the load. The output resistance of the series branch of the first inverter I1 and the first resistor R1 is equal to the output resistance of the series branch of the second inverter I2 and the second resistor R2, so as to realize impedance matching. The specific resistance values of the first resistor R1 and the second resistor R2 are selected according to actual conditions. In an embodiment of the utility model, an output resistance of a series branch of the first inverter I1 and the first resistor R1 is 50 ohms, an output resistance of a series branch of the second inverter I2 and the second resistor R2 is also 50 ohms, and the load 2R is providedLIs 100 ohms.
The first MOS transistor P1, the second MOS transistor P2, the third MOS transistor N1, the fourth MOS transistor N2, the first current source and the second current source form a pre-emphasis unit, and the pre-emphasis unit is used for enhancing the high-frequency component on the premise that the low-frequency component is not compressed.
The source electrode of the first MOS transistor P1, the second MOS transistorThe source of the MOS transistor P2 is connected to a first current source, and the gate of the first MOS transistor P1 is used as a control signal
Figure BDA0003471211370000061
The gate of the second MOS transistor P2 is used as the input terminal of the control signal VPD, the drain of the first MOS transistor P1 is connected to the second end of the load, the drain of the second MOS transistor P2 is connected to the first end of the load, the source of the third MOS transistor N1 and the source of the fourth MOS transistor N2 are connected to the second current source, and the gate of the third MOS transistor N1 is used as the control signal VPD
Figure BDA0003471211370000071
The gate of the fourth MOS transistor N2 is used as the input terminal of the control signal VPU, the drain of the third MOS transistor N1 is connected to the second end of the load, and the drain of the fourth MOS transistor N2 is connected to the first end of the load; the control signal VPU is a rising edge signal of the first input signal Vip with a certain pulse width extracted from the time when the rising edge of the first input signal Vip comes; the control signal VPD is a falling edge signal of the first input signal Vip having a certain pulse width extracted from the arrival of the falling edge of the first input signal Vip; control signal
Figure BDA0003471211370000072
And
Figure BDA0003471211370000073
inverted signals respectively representing the control signal VPU and the control signal VPD, the control signals VPU, VPD,
Figure BDA0003471211370000074
And
Figure BDA0003471211370000075
the pulse widths of (1) are all beta T, wherein beta is a pulse width modulation factor and has a value range of 0<Beta is less than or equal to 1, T is the length of a unit code element, and the value is the reciprocal of the baud rate of the data stream. The pulse width is generated by a delay unit, and the range size of the pulse width can be adjusted under the control of an external voltage.
Referring to FIG. 7, in one embodiment of the present invention, control signals VPU and
Figure BDA0003471211370000076
the generating circuit comprises a delay unit, an AND gate and an OR gate, wherein a first input signal VIP is connected with a first input end of the AND gate, a second input signal VIN is connected with a second input end of the AND gate after passing through the delay unit, and a signal output by an output end of the AND gate is a control signal VPU; the second input signal VIN is connected with the first input end of the OR gate, the first input signal VIP is connected with the second input end of the OR gate after passing through the delay unit, and the output signal of the output end of the OR gate is a control signal
Figure BDA0003471211370000077
Referring to FIG. 7, in one embodiment of the present invention, control signals VPD and
Figure BDA0003471211370000078
the generating circuit comprises a delay unit, an AND gate and an OR gate, wherein a second input signal VIN is connected with a first input end of the AND gate, a first input signal VIP is connected with a second input end of the AND gate after passing through the delay unit, and a signal output by an output end of the AND gate is a control signal VPD; the first input signal VIP is connected with the first input end of the OR gate, the second input signal VIN is connected with the second input end of the OR gate after passing through the delay unit, and the output signal of the output end of the OR gate is a control signal
Figure BDA0003471211370000079
FIG. 8 shows the control signals VPU,
Figure BDA00034712113700000710
VPD、
Figure BDA00034712113700000711
Fig. 9 shows a pre-emphasized output waveform, which is found to be a pulse signal having a pulse width beta T superimposed on an input signal and having an amplitude of IsRLWherein Is tail current, RLWhich is a load resistance, as shown in fig. 6.
In this embodiment, the output signal VOP/VON outputs an NRZ signal with a high level of 3/4VDD and a low level of 1/4VDD according to different high-low level combinations of the input signal VIP/VIN. A VPU,
Figure BDA0003471211370000081
VPD、
Figure BDA0003471211370000082
Which are pulse width-equal, adjustable control signals, which are generated in principle as shown in fig. 7, wherein the rising edge of VPU is aligned with the rising edge of the input signal VIP, the falling edge of VPD is aligned with the falling edge of the input signal VIP,
Figure BDA0003471211370000083
is aligned with the falling edge of the input signal VIN,
Figure BDA0003471211370000084
is aligned with the rising edge of the input signal VIN. The pulse width of the signal is controlled by the delay unit. Under the control of the above signals, the rising edge and the falling edge of the original output signal VOP/VON are respectively superposed with a pulse width identical to that of the control signal, and the amplitude Is obtained by a current source Is and a load resistor RLThe pre-emphasis is achieved by the controlled pulse. For example, when VIP rising edge and VIN falling edge arrive, VPU and VPD are high,
Figure BDA0003471211370000085
and
Figure BDA0003471211370000086
at low level, MOS transistors P1 and N2 are turned on, P2 and N1 are turned off, the Is current passes through load resistor 2RL from VOP, so that the output swing VOP-VON Is increased by RLIS。
The utility model obviously enhances the pre-emphasis only by high-frequency components without influencing low-frequency components, and solves the problem that the output swing is influenced by the balanced strength. Table 1 shows the relationship between the input and output signals of the voltage-mode pre-emphasis equalizing circuit (hereinafter, referred to as voltage-mode architecture FFE) provided in the embodiments shown in fig. 7 to 9 and the existing current-mode architecture FFE, respectively, and it can be found that when the outputs have the same swing, the power consumption of the circuit is about 1/4 of the existing current-mode architecture FFE, thereby achieving the purpose of saving power consumption.
TABLE 1 relationship between FFE input and output (NRZ) for voltage mode architecture and FFE for current mode architecture
Figure BDA0003471211370000087
In a multi-level modulation mode, the circuit can keep high-linearity output except the advantages of no influence on output swing of balanced strength and low power consumption. Referring to fig. 10 to 13, in another embodiment of the present invention, a voltage mode pre-emphasis equalization circuit is provided, which takes four-level Pulse Amplitude Modulation (PAM-4) as an example, and provides a circuit structure under multi-level Modulation, where the circuit is composed of a driving unit and a pre-emphasis unit.
The input signals comprise MSBP, MSBN, LSBP and LSBN, wherein the MSBP/MSBN is a high-bit input differential signal, and the LSBP/LSBN is a low-bit differential input signal.
Inverter I1, inverter I2, inverter I3, inverter I4, resistor R1, resistor R2, resistor R3, resistor R4 and load 2RL(100 ohms) constitute a driving unit for feeding input data onto the channel. The input ends of the inverter I1, the inverter I2, the inverter I3 and the inverter I4 are respectively used as the input ends of input signals MSBP, LSBP, MSBN and LSBN. Input signals MSBP, LSBP, MSBN and LSBN are input from input terminals of the inverter I1, the inverter I2, the inverter I3 and the inverter I4, respectively. The output resistance of the series branch of the inverter I1 and the resistor R1 is 75 ohms, the output resistance of the series branch of the inverter I2 and the resistor R2 is 150 ohms, the output resistance of the series branch of the inverter I3 and the resistor R3 is 75 ohms, and the output resistance of the series branch of the inverter I4 and the resistor R4 is 150 ohms, so that impedance matching is achieved.
Load 2RLThe first and second terminals of (1) are differential output terminals Vop, Von, respectively. The output end of the inverter I1 is connected with a load 2R after being connected with a resistor R1 in seriesLFirst end ofThe output end of the inverter I2 is connected in series with the resistor R2 and then connected to the load 2RLThe output end of the inverter I3 is connected in series with the resistor R3 and then connected with the load 2RLThe output end of the inverter I4 is connected in series with the resistor R4 and then connected with the load 2RLThe second end of (a).
The pre-emphasis unit consists of a MOS tube P1, a MOS tube P2, a MOS tube P3, a MOS tube P4, a MOS tube N1, a MOS tube N2, a MOS tube N3, a MOS tube N4, a current source 2Is and a current source Is, and Is used for enhancing high-frequency components on the premise of not compressing low-frequency components. Wherein 2Is and Is represent the current size, in the figure, the current size of four current sources, two current sources Is 2Is, the current size of the other two current sources Is, which Is intended to show that the current size of the first two current sources Is twice that of the second two current sources.
The grid of MOS transistor P1, the grid of MOS transistor P2, the grid of MOS transistor P3, the grid of MOS transistor P4, the grid of MOS transistor N1, the grid of MOS transistor N2, the grid of MOS transistor N3 and the grid of MOS transistor N4 are respectively used as control signals
Figure BDA0003471211370000101
MPD、LPD、
Figure BDA0003471211370000102
MPU、LPU、
Figure BDA0003471211370000103
To the input terminal of (1). One current source 2Is connected with the source electrode of the MOS transistor P1 and the source electrode of the MOS transistor P2, and the other current source 2Is connected with the source electrode of the MOS transistor N1 and the source electrode of the MOS transistor N2. One current source Is connected with the source electrode of the MOS transistor P3 and the source electrode of the MOS transistor P4, and the other current source Is connected with the source electrode of the MOS transistor N3 and the source electrode of the MOS transistor N4. The drain of MOS transistor P1 is connected to the drain of MOS transistor N1 and to load 2RLThe second end of (a). The drain of MOS transistor P2 is connected to the drain of MOS transistor N2 and to load 2RLA drain of the MOS transistor P3 is connected to a drain of the MOS transistor N3 and to a load 2RLA drain of the MOS transistor P4 is connected to a drain of the MOS transistor N4 and to a load 2RLThe second end of (a).
The generation circuit of the control signal of each MOS transistor is shown in fig 11,the MPU represents a rising edge signal of the input signal MSBP with a certain pulse width extracted from the arrival of the rising edge of the input signal MSBP, and the MPD represents a falling edge signal of the input signal MSBP with a certain pulse width extracted from the arrival of the falling edge of the input signal MSBP.
Figure BDA0003471211370000104
And
Figure BDA0003471211370000105
representing the inverse signals of the MPU and MPD, respectively. The LPU extracts a rising edge signal of the input signal LSBP having a certain pulse width from the arrival of a rising edge of the input signal LSBP, and the LPD represents a falling edge signal of the input signal LSBP having a certain pulse width from the arrival of a falling edge of the input signal LSBP.
Figure BDA0003471211370000106
And
Figure BDA0003471211370000107
representing the inverse of the LPU and LPD, respectively. Control signals MPU,
Figure BDA0003471211370000108
MPD、
Figure BDA0003471211370000109
LPU、
Figure BDA00034712113700001010
LPD and
Figure BDA00034712113700001011
the pulse width of (1) is beta T, which is generated by the delay unit, and the delay range can be adjusted by controlling the voltage.
The working principle of the embodiment is as follows: the output signal VOP/VON outputs PAM-4 signals with four levels of 3/12VDD, 5/12VDD, 7/12VDD and 9/12VDD according to different high-low level combinations of the input signal MSBP/N, LSBP/N.
Figure BDA00034712113700001012
MPD、LPD、
Figure BDA00034712113700001013
MPU、LPU、
Figure BDA00034712113700001014
The control signals, which are equal and adjustable in pulse width, are generated in the principle shown in fig. 11, where the MPU rising edge is aligned with the input signal MSBP rising edge, the MPD falling edge is aligned with the MSBP falling edge,
Figure BDA0003471211370000111
the falling edge is aligned with the MSBN falling edge,
Figure BDA0003471211370000112
the rising edge is aligned with the MSBN rising edge, the LPU rising edge is aligned with the input signal LSBP rising edge, the LPD falling edge is aligned with the LSBP falling edge,
Figure BDA0003471211370000113
the falling edge is aligned with the LSBN falling edge,
Figure BDA0003471211370000114
the rising edge is aligned with the LSBN rising edge, and the pulse width of the signals is controlled by the delay unit. Under the control of the above signals, the rising edge and the falling edge of the original output signal VOP/VON are respectively superposed with a pulse width identical to that of the control signal, and the amplitudes are obtained by current sources 2Is and a load resistor RLThe pre-emphasis is achieved by the controlled pulse. For example, when the rising edges of MSBP and LSBP and the falling edges of MSBN and LSBN come, MPU, MPD, LPU and LPD are in high level,
Figure BDA0003471211370000115
at low level, MOS transistors P1, P4, N2 and N3 are turned on, P2, P3, N1 and N4 are turned off, and 3Is current passes through load resistor 2RL from VOP, so that output swing VOP-VON Is increased by 3RLIS。
FIG. 12 is a timing waveform diagram of the control signals MPU, MPD, LPU, LPD,fig. 13 shows the output waveform after pre-emphasis. It can be seen that the output signal is a pulse signal with a pulse width beta T superimposed on the input signal, and the amplitude of the superimposed pulse is IsR according to the difference of the amplitudes of the signal jumpsL、2IsRLAnd 3IsRLAnd the superposition position is positioned at the jump edge of the input signal, so that the pre-emphasis obviously only enhances the high-frequency component but not influences the low-frequency component, and the problem that the output swing is influenced by the balanced strength is solved.
Table 2 shows the relationship between the input and output signals of the voltage-mode pre-emphasis equalization circuit (hereinafter, referred to as voltage-mode architecture FFE) provided in the embodiments shown in fig. 10 to 13 and the existing current-mode architecture FFE, respectively, and it can be found that when the outputs have the same swing, the power consumption of the circuit is about 1/4 of the CML architecture, thereby achieving the purpose of saving power consumption. In addition, it can be found from table 2 that the output level is determined only by the power supply voltage, so that high output linearity can be maintained, and the influence of the output swing on the linearity in the CML architecture is avoided.
TABLE 2 relationship between FFE and FFE (PAM-4) between voltage mode structure and current mode structure
Figure BDA0003471211370000116
Figure BDA0003471211370000121
Although specific embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these are merely examples and that many variations or modifications may be made to the embodiments without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims.

Claims (8)

1. Voltage mode pre-emphasis equalization circuit, characterized in that, the circuit adopts voltage mode framework, includes:
a driver circuit for delivering an input signal to a channel;
and the pre-emphasis circuit is used for enhancing the high-frequency component on the premise of not compressing the low-frequency component.
2. The voltage mode pre-emphasis equalization circuit according to claim 1, wherein the input signals comprise a first input signal and a second input signal, the first input signal and the second input signal are differential input signals, a driving unit is composed of a first inverter I1, a second inverter I2, a first resistor R1, a second resistor R2 and a load, and a differential output end is arranged at two ends of the load; the first input signal is input from a first inverter I1, the first inverter I1 is connected to a first terminal of a first resistor R1, a second terminal of the first resistor R1 is connected to a first terminal of a load, the second input signal is input from a second inverter I2, the second inverter I2 is connected to a first terminal of a second resistor R2, and a second terminal of the second resistor R2 is connected to a second terminal of the load.
3. The voltage mode pre-emphasis equalization circuit of claim 2, wherein the output resistance of the series branch of the first inverter I1 and the first resistor R1 is equal to the output resistance of the series branch of the second inverter I2 and the second resistor R2, so as to achieve impedance matching.
4. The voltage mode pre-emphasis equalization circuit according to claim 2 or 3, wherein the first MOS transistor P1, the second MOS transistor P2, the third MOS transistor N1, the fourth MOS transistor N2, the first current source and the second current source form a pre-emphasis unit, the source of the first MOS transistor P1 and the source of the second MOS transistor P2 are connected with the first current source, and the gate of the first MOS transistor P1 is used as a control signal
Figure FDA0003471211360000011
The gate of the second MOS transistor P2 is used as the input terminal of the control signal VPD, the drain of the first MOS transistor P1 is connected to the second end of the load, the drain of the second MOS transistor P2 is connected to the first end of the load, the source of the third MOS transistor N1 and the source of the fourth MOS transistor N2 are connected to the second current source, and the gate of the third MOS transistor N1 is used as the control signal VPD
Figure FDA0003471211360000012
The gate of the fourth MOS transistor N2 is used as the input terminal of the control signal VPU, the drain of the third MOS transistor N1 is connected to the second end of the load, and the drain of the fourth MOS transistor N2 is connected to the first end of the load; the control signal VPU is a rising edge signal of the first input signal Vip with a certain pulse width, which is extracted from the time when the rising edge of the first input signal Vip comes; the control signal VPD is a falling edge signal of the first input signal Vip having a certain pulse width extracted from the arrival of the falling edge of the first input signal Vip; control signal
Figure FDA0003471211360000021
And
Figure FDA0003471211360000022
inverted signals respectively representing the control signal VPU and the control signal VPD, the control signals VPU, VPD,
Figure FDA0003471211360000023
And
Figure FDA0003471211360000024
the pulse widths of (1) are all beta T, wherein beta is a pulse width modulation factor and has a value range of 0<Beta is less than or equal to 1, T is unit code element length and is the reciprocal of data stream baud rate.
5. The voltage-mode pre-emphasis equalization circuit of claim 4, wherein control signals VPU and VPU
Figure FDA0003471211360000025
The generating circuit comprises a delay unit, an AND gate and an OR gate, wherein a first input signal VIP is connected with a first input end of the AND gate, a second input signal VIN is connected with a second input end of the AND gate after passing through the delay unit, and a signal output by an output end of the AND gate is a control signal VPU; the second input signal VIN is connected with the first input end of the OR gate, and the first input signal VIP is connected with the second input end of the OR gate after passing through the delay unitThe signal output by the output end of the OR gate is a control signal
Figure FDA0003471211360000026
6. The voltage-mode pre-emphasis equalization circuit of claim 4, wherein control signals VPD and VPD
Figure FDA0003471211360000027
The generating circuit comprises a delay unit, an AND gate and an OR gate, wherein a second input signal VIN is connected with a first input end of the AND gate, a first input signal VIP is connected with a second input end of the AND gate after passing through the delay unit, and a signal output by an output end of the AND gate is a control signal VPD; the first input signal VIP is connected with the first input end of the OR gate, the second input signal VIN is connected with the second input end of the OR gate after passing through the delay unit, and the output signal of the output end of the OR gate is a control signal
Figure FDA0003471211360000028
7. A SerDes transmitter, comprising the voltage-mode pre-emphasis equalization circuit of claim 1, 2, 3, 5, or 6.
8. A chip comprising the voltage-mode pre-emphasis equalization circuit of claim 1, 2, 3, 5, or 6.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117375538A (en) * 2023-10-09 2024-01-09 新港海岸(北京)科技有限公司 Attenuation compensation method and attenuation compensation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117375538A (en) * 2023-10-09 2024-01-09 新港海岸(北京)科技有限公司 Attenuation compensation method and attenuation compensation circuit

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