CN216697198U - Startup and shutdown control circuit - Google Patents

Abstract

The utility model provides a startup and shutdown control circuit, which comprises a startup and shutdown control unit, a standby power supply unit and a controller, wherein the standby power supply unit is connected with the controller; the dial switch J1 is used as a power-on/off key, so that the power-on/off of a user can be facilitated; when a user dials the dial switch J1 and the dial switch J1 is placed at a shutdown position, the controller communicates with a CPU (central processing unit) of the equipment after detecting shutdown actions of the user through a signal input end, and judges the current storage condition of the equipment, if data are not stored in any CPU, the CPU stores the corresponding data, and feeds the data back to the controller after the storage of the CPU is completed, and the controller controls a switch control unit to cut off a power supply path from a power supply VS to a load through an output signal end of the controller to power off the equipment, so that the conditions that the shutdown cannot be performed through a system interface and the data are lost after hard power off due to the operation faults of an operating system are avoided.

Description

Startup and shutdown control circuit

Technical Field

The utility model belongs to the field of power management, and particularly relates to a startup and shutdown control circuit.

Background

The power system test equipment is generally controlled by an entity power-on key, the power system test equipment is generally controlled by a soft power-off function under an operating system, once the operating system fails, a user may face the option that the power system cannot be turned off and only can make a selection in the options of cutting off a power line, pulling out a battery or waiting for the test equipment to consume the battery power, and the problem can be solved by hard power-off based on the entity switch. On the other hand, because the power system test equipment usually has the storage requirements of storing the previous setting, storing the test result, generating the test report, and the like, if the user shuts down the equipment during the storage operation or directly shuts down the equipment without storing the data, the data storage of the equipment is affected, and therefore it is very important to research a power on/off control circuit which adopts an entity switch and is powered off after the data storage of the equipment is completed during the shutdown.

Disclosure of Invention

In order to solve the above problems, the present invention provides a power on/off control circuit, which has the following specific technical scheme:

a startup and shutdown control circuit comprises a startup and shutdown control unit, a standby power supply unit and a controller; the input end of the on-off control unit is connected with a power supply of the equipment, and the output end of the on-off control unit is connected with a CPU (central processing unit) and a storage unit of the equipment;

the input end of the standby power supply unit is connected with a power supply of the equipment, and the output end of the standby power supply unit is connected with the controller; the controller is respectively connected with the on-off control unit and the CPU unit of the equipment;

the on-off control unit is used for controlling the on-off of the equipment; the standby power supply unit is used for providing power supply for the controller; the controller is used for communicating with a CPU of the equipment when the user shuts down the equipment, and controlling the on-off control unit to shut down the equipment after the CPU of the equipment is stored.

Preferably, the on-off control unit comprises a MOS transistor N1, a MOS transistor N2, a MOS transistor Q1 and a dial switch J1;

the source electrode of the MOS tube Q1 is connected with a power supply VS of the equipment, and the drain electrode of the MOS tube Q1 is used as a power supply output VSYS for supplying power to a CPU unit and a storage unit of the equipment;

the grid electrode of the MOS transistor Q1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the anode of a diode D1 and one end of a resistor R2, and the cathode of a diode D1 is connected with the source electrode of the MOS transistor Q1;

the other end of the resistor R2 is connected with a pin 1 of a dial switch J1 and the drain electrode of a MOS transistor N1, a pin 2 of the dial switch J1 is grounded, a pin 3 of a dial switch J1 is connected with one end of a resistor R4 and the signal input end of the controller, and the other end of the resistor R4 is connected with the output end of the standby power supply unit;

the source electrode of the MOS transistor N1 is grounded, the grid electrode of the MOS transistor N1 is connected with one end of the resistor R3, one end of the resistor R5 and the drain electrode of the MOS transistor N2 respectively, the other end of the resistor R3 is connected with the output end of the standby power supply unit, the other end of the resistor R5 is grounded, the source electrode of the MOS transistor N2 is grounded, the grid electrode of the MOS transistor N2 is connected with one end of the resistor R7 and one end of the resistor R6 respectively, the other end of the resistor R7 is grounded, and the other end of the resistor R6 is connected with the signal output end of the controller.

Preferably, the MOS transistor N1 is an N-MOS transistor.

Preferably, the MOS transistor N2 is an N-MOS transistor.

Preferably, the MOS transistor Q1 is a P-MOS transistor.

Preferably, the standby power supply unit comprises a power management chip U1, a first pin of the power management chip U1 is connected with a cathode of a diode D2, and an anode of the diode D2 is connected with a power supply VS of the device;

the second pin of the power management chip U1 is grounded, and the third pin of the power management chip U1 is connected with one end of a capacitor C1 and one end of a capacitor C2 and serves as an output end of the standby power supply unit; the fourth pin of the power management chip U1, the other end of the capacitor C1, and the other end of the capacitor C2 are grounded.

Preferably, the power management chip U1 selects the TPS7B6933QDCYRQ1 chip.

The utility model has the beneficial effects that: the utility model provides a startup and shutdown control circuit, which comprises a startup and shutdown control unit, a standby power supply unit and a controller, wherein the standby power supply unit is connected with the controller; according to the utility model, the dial switch J1 is used as a switch key, so that the power-on and power-off of a user can be facilitated, when the user dials the dial switch J1 and places the dial switch J1 at the power-on position, the power supply VS is controlled by the switch control unit to supply power to a load, and the equipment is started; when a user toggles the dial switch J1 and places the dial switch J1 at a shutdown position, the controller detects shutdown actions of the user through a signal input end and then communicates with a CPU unit of the equipment, current storage conditions of the equipment are judged, if data are not stored in the CPU unit, the CPU unit stores corresponding data, the data are fed back to the controller after the storage of the CPU unit is completed, the controller controls a switch control unit to cut off a power supply path from a power supply VS to a load through an output signal end of the controller to power off the equipment, and therefore the situations that the shutdown cannot be realized through a system interface due to faults in operation of an operating system and the data are lost after hard power off are avoided.

Drawings

In order to more clearly illustrate the detailed description of the utility model or the technical solutions in the prior art, the drawings that are needed in the detailed description of the utility model or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.

FIG. 1 is a schematic diagram of the principles of the present invention;

FIG. 2 is a schematic circuit diagram of the on-off control unit of the present invention;

fig. 3 is a schematic circuit diagram of the standby power supply unit of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As shown in fig. 1, a switching on/off control circuit includes a switching on/off control unit, a standby power supply unit, and a controller; the input end of the on-off control unit is connected with a power supply of the equipment, and the output end of the on-off control unit is connected with a CPU (central processing unit) and a storage unit of the equipment;

the input end of the standby power supply unit is connected with a power supply of the equipment, and the output end of the standby power supply unit is connected with the controller; the controller is respectively connected with the on-off control unit and the CPU unit of the equipment;

the on-off control unit is used for controlling the on-off of the equipment; the standby power supply unit is used for providing power supply for the controller; the controller is used for communicating with a CPU of the equipment when the user shuts down the equipment, and controlling the on-off control unit to shut down the equipment after the CPU of the equipment is stored.

The working principle of the utility model is as follows: when a user shuts down through the on-off machine control unit, the controller detects the on-off action of the user, then the CPU unit of the equipment communicates to judge whether data are stored in the CPU unit, if the data are not stored in the CPU unit, the controller controls the on-off machine control unit to shut down after the data are stored in the CPU unit, if the data are not stored in the CPU unit, the controller directly controls the on-off machine control unit to shut down, and the current between a power supply and the load of the equipment is cut off.

As shown in fig. 2, the on/off control unit includes a MOS transistor N1, a MOS transistor N2, a MOS transistor Q1, and a dial switch J1;

the source electrode of the MOS tube Q1 is connected with a power supply VS of the equipment, and the drain electrode of the MOS tube Q1 is used as a power supply output VSYS for supplying power to a CPU unit and a storage unit of the equipment;

the grid of the MOS transistor Q1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the anode of a diode D1 and one end of a resistor R2, and the cathode of a diode D1 is connected with the source of the MOS transistor Q1;

the other end of the resistor R2 is connected with a pin 1 of a dial switch J1 and the drain electrode of a MOS transistor N1, a pin 2 of the dial switch J1 is grounded, a pin 3 of a dial switch J1 is connected with one end of a resistor R4 and the signal input end of the controller, and the other end of the resistor R4 is connected with the output end of the standby power supply unit;

the source of the MOS transistor N1 is grounded, the gate of the MOS transistor N1 is connected to one end of the resistor R3, one end of the resistor R5, and the drain of the MOS transistor N2, the other end of the resistor R3 is connected to the output end of the standby power supply unit, the other end of the resistor R5 is grounded, the source of the MOS transistor N2 is grounded, the gate of the MOS transistor N2 is connected to one end of the resistor R7 and one end of the resistor R6, the other end of the resistor R7 is grounded, and the other end of the resistor R6 is connected to the signal output end of the controller. The MOS transistor N1 is an N-MOS transistor. The MOS transistor N2 is an N-MOS transistor. The MOS transistor Q1 is a P-MOS transistor.

As shown in fig. 3, the standby power supply unit includes a power management chip U1, a first pin of the power management chip U1 is connected to a cathode of a diode D2, and an anode of the diode D2 is connected to a power supply VS of the device;

the second pin of the power management chip U1 is grounded, and the third pin of the power management chip U1 is connected with one end of a capacitor C1 and one end of a capacitor C2 and serves as an output end of the standby power supply unit; the fourth pin of the power management chip U1, the other end of the capacitor C1, and the other end of the capacitor C2 are grounded. The power management chip U1 selects the TPS7B6933QDCYRQ1 chip.

When a user operates the equipment, the dial switch J1 needs to be toggled, so that the 1 st pin and the 2 nd pin of the dial switch J1 are communicated, at the moment, the resistor R2 is grounded, and the current conduction of the input end VS of the equipment power supply, the voltage regulator tube D1 and the resistor R2 is formed, so that the voltage regulator tube D1 is conducted, the voltage regulator tube D1 is selected to have a proper voltage regulation value, so that when the voltage regulator tube D1 is conducted, the MOS tube Q1 is also conducted, at the moment, a power supply path from the input end VS of the equipment power supply to the power supply output end VSYS for supplying power to a load through the MOS tube Q1 is formed, and the equipment is powered on to work. The voltage regulation value of the voltage regulator tube D1 needs to be greater than the threshold voltage between the gate and the source required for the turn-on of the MOS tube Q1, and less than the maximum withstand voltage between the gate and the source of the MOS tube Q1.

When a user is powered on, the 2 nd pin of the dial switch J1 is connected with the 1 st pin from being connected with the 3 rd pin, at this time, the level state of the signal SHUTDOWN input to the controller is changed from low level to high level, the controller performs polling detection on the signal SHUTDOWN input to the controller, once the high level is detected, the device is judged to be powered on, at this time, the controller sets the control signal PWR _ CTRL at the signal output end to low level, under the driving of the control signal PWR _ CTRL, the gate of the N-MOS transistor N2 is at low level, so the MOS transistor N2 is not turned on, and through reasonable selection of the resistor R3 and the resistor R5, the resistor R5 can divide the voltage of the output voltage signal V3P3_ STB of the standby power supply unit to enable the MOS transistor N1 to be turned on, so that double pull-down of the resistor R2 is realized, that is pulled down through the switch and the MOS transistor N1.

When a user needs to shut down the equipment, the dial switch J1 needs to be toggled, so that the pin 1 and the pin 2 of the J1 are disconnected, at the moment, the resistor R2 is still grounded under the conducting action of the MOS tube N1, and the current conduction of the power VS at the input end of the equipment, the voltage regulator tube D1 and the resistor R2 is formed, so that the voltage regulator tube D1 is conducted, as described above, the MOS tube Q1 is also conducted at the moment, the power supply path from the input end VS of the power supply of the equipment to the power output end VSYS for supplying power to a load through the MOS tube Q1 is formed, and the equipment still obtains a working power supply.

However, when the user is powered off, the 2 nd pin and the 3 rd pin of the dial switch J1 are communicated, at this time, the level state of the signal SHUTDOWN input to the controller changes from high level to low level, the controller performs polling detection on the signal SHUTDOWN input by the controller, once the low level is detected, it is determined that the user needs to power off the device, at this time, the controller sends a state level to the CPU through an output pin connected with the CPU to inform the CPU of storing unsaved data, and after the CPU completes storing the related data, the CPU sends the state level to an input pin of the controller to inform the controller that the related data has been stored. At this time, the controller sets a control signal PWR _ CTRL at a signal output end to a high level, and under the drive of the control signal PWR _ CTRL, the gate of the N-MOS transistor N2 is a high level, so that the MOS transistor N2 is turned on, the gate of the MOS transistor N1 is a low level at this time, the MOS transistor N1 is turned off, and at this time, the resistor R2 cannot be pulled down to DGND, so that the MOS transistor Q1 is turned off, and the device is powered off and shut down.

In this embodiment, the power output VSYS that supplies power to the load through the MOS transistor Q1 also needs to supply a proper working voltage to the load CPU unit and the storage unit through the voltage conversion circuit, and may specifically pass through the DC-DC conversion circuit, which is the prior art and will not be described herein again.

Those of ordinary skill in the art will appreciate that the elements of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the components of the examples have been described above generally in terms of their functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present application, it should be understood that the division of a unit is only one logical function division, and in actual implementation, there may be another division manner, for example, multiple units may be combined into one unit, one unit may be split into multiple units, or some features may be omitted.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.

Claims (7)

1. A kind of switching on/off control circuit, characterized by that: the device comprises a switch machine control unit, a standby power supply unit and a controller; the input end of the on-off control unit is connected with a power supply of the equipment, and the output end of the on-off control unit is connected with a CPU (central processing unit) and a storage unit of the equipment;

the input end of the standby power supply unit is connected with a power supply of the equipment, and the output end of the standby power supply unit is connected with the controller; the controller is respectively connected with the on-off control unit and the CPU unit of the equipment;

the on-off control unit is used for controlling the on-off of the equipment; the standby power supply unit is used for providing power supply for the controller; the controller is used for communicating with a CPU of the equipment when the user shuts down the equipment, and controlling the on-off control unit to shut down the equipment after the CPU of the equipment is stored.

2. The on/off control circuit as claimed in claim 1, wherein: the on-off control unit comprises an MOS tube N1, an MOS tube N2, an MOS tube Q1 and a dial switch J1;

the source electrode of the MOS tube Q1 is connected with a power supply VS of the equipment, and the drain electrode of the MOS tube Q1 is used as a power supply output VSYS for supplying power to a CPU unit and a storage unit of the equipment;

the grid of the MOS transistor Q1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the anode of a diode D1 and one end of a resistor R2, and the cathode of a diode D1 is connected with the source of the MOS transistor Q1;

the other end of the resistor R2 is connected with a pin 1 of a dial switch J1 and the drain electrode of a MOS transistor N1, a pin 2 of the dial switch J1 is grounded, a pin 3 of a dial switch J1 is connected with one end of a resistor R4 and the signal input end of the controller, and the other end of the resistor R4 is connected with the output end of the standby power supply unit;

the source of the MOS transistor N1 is grounded, the gate of the MOS transistor N1 is connected to one end of the resistor R3, one end of the resistor R5, and the drain of the MOS transistor N2, the other end of the resistor R3 is connected to the output end of the standby power supply unit, the other end of the resistor R5 is grounded, the source of the MOS transistor N2 is grounded, the gate of the MOS transistor N2 is connected to one end of the resistor R7 and one end of the resistor R6, the other end of the resistor R7 is grounded, and the other end of the resistor R6 is connected to the signal output end of the controller.

3. The on/off control circuit as claimed in claim 2, wherein: the MOS transistor N1 is an N-MOS transistor.

4. The on/off control circuit as claimed in claim 2, wherein: the MOS transistor N2 is an N-MOS transistor.

5. The on/off control circuit as claimed in claim 2, wherein: the MOS transistor Q1 is a P-MOS transistor.

6. The on/off control circuit as claimed in claim 1, wherein: the standby power supply unit comprises a power management chip U1, wherein a first pin of the power management chip U1 is connected with a cathode of a diode D2, and an anode of the diode D2 is connected with a power supply VS of equipment;

the second pin of the power management chip U1 is grounded, and the third pin of the power management chip U1 is connected with one end of a capacitor C1 and one end of a capacitor C2 and serves as an output end of the standby power supply unit; the fourth pin of the power management chip U1, the other end of the capacitor C1, and the other end of the capacitor C2 are grounded.

7. The on/off control circuit as claimed in claim 6, wherein: the power management chip U1 selects the TPS7B6933QDCYRQ1 chip.

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