CN216671172U - Control device of liquid crystal display of systematized chip - Google Patents
Control device of liquid crystal display of systematized chip Download PDFInfo
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- CN216671172U CN216671172U CN202122998703.6U CN202122998703U CN216671172U CN 216671172 U CN216671172 U CN 216671172U CN 202122998703 U CN202122998703 U CN 202122998703U CN 216671172 U CN216671172 U CN 216671172U
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Abstract
The embodiment of the utility model provides a control device of a liquid crystal display of a systematic chip, which comprises: a liquid crystal display; the main control central processing unit is electrically connected with the liquid crystal display through a signal line; the master control central processing unit is provided with a flash memory module and an input/output module. The embodiment of the utility model solves the problem of image display tearing caused by the fact that part of low-cost SOC does not support a parallel interface control LCD and a serial SPI bus control LCD, and effectively improves the display effect of the low-cost SOC control LCD.
Description
Technical Field
The present invention relates to the field of systematic chip technology, and more particularly to a control device for a liquid crystal display of a systematic chip.
Background
The SOC, also called a system on chip, mainly includes a main control CPU (Central Processing Unit) and some peripheral controllers, such as an LCD (Liquid Crystal Display) controller. A general high-cost SOC is internally provided with a GPU, and can support LCDs with interfaces such as MIPI (Mobile Industry Processor Interface) and RGB (color system), and the resolutions of these LCDs are generally large; however, the low-cost SOC has no GPU, and is mainly based on a general Peripheral Interface (SPI) controller to control the LCD, which has a relatively low resolution and a low cost; a common LCD based on a parallel bus controller is arranged on a common singlechip system, and the resolution ratio of the LCDs is generally low, so that the cost is low;
when the SOC without the CPU is used for controlling the LCD, the serial SPI bus is used for controlling the LCD, so that the data rate is low, the data transmission speed cannot keep up with the refreshing speed of the LCD, and the image display is torn; and parallel SPI bus control LCD, parallel bus equipment pin occupies than many, moreover, SOC does not support the parallel interface yet mostly, leads to low-cost SOC can't pass through the parallel interface control LCD.
SUMMERY OF THE UTILITY MODEL
The utility model provides a control device of a liquid crystal display of a systematized chip. The problem of some low-cost SOCs do not support the tearing of image display that parallel interface control LCD and serial SPI bus control LCD lead to is solved, low-cost SOCs control LCD's display effect has been promoted effectively.
To solve the above technical problem, an embodiment of the present invention provides the following solutions:
a control device of a liquid crystal display of a systematized chip, comprising:
a liquid crystal display;
the main control central processing unit is electrically connected with the liquid crystal display through a signal line; the master control central processing unit is provided with a flash memory module and an input/output module.
Optionally, a first data signal line interface is arranged on the liquid crystal display;
the flash memory module is provided with a second data signal line interface;
the first data signal line interface is electrically connected with the second data signal line interface through a data signal line.
Optionally, a first write enable signal line interface is arranged on the liquid crystal display;
a second write enable signal line interface is arranged on the flash memory module;
the first write enable signal line interface is electrically connected with the second write enable signal line interface through a write enable signal line.
Optionally, a first chip select signal line interface is arranged on the liquid crystal display;
the flash memory module is provided with an address latch enabling signal line interface and a command latch enabling signal line interface;
the input/output module is provided with a second chip selection signal line interface;
the first chip selection signal line interface is connected with the second chip selection signal line interface, the address latch enabling signal line interface and the command latch enabling signal line interface through a logic circuit.
Optionally, the logic circuit includes:
a first OR gate logic element;
a second OR gate logic element electrically connected to an output of the first OR gate logic element.
Optionally, the first or gate logic element is provided with a first input end, a second input end and a first output end; the first or gate logic element is configured to perform or gate processing on the input signal at the first input end and the input signal at the second input end to obtain a first result signal, and use the first result signal as an output signal at a first output end;
the second OR gate logic element is provided with a third input end, a fourth input end and a second output end; and the second or gate logic element is used for performing or gate processing on the input signal of the third input end and the input signal of the fourth input end to obtain a second result signal, and taking the second result signal as an output signal of a second output end.
Optionally, the address latch enable signal line interface is electrically connected to the first input terminal of the first or gate logic element through an address latch enable signal line;
the command latch enable signal line interface is electrically connected with the second input end of the first OR gate logic element through a command latch enable signal line;
the first output end of the first OR gate logic element and the third input end of the second OR gate logic element are electrically connected through a result signal line;
the second chip selection signal line interface is electrically connected with the fourth input end of the second OR gate logic element through a second chip selection signal line;
the second output end of the second OR gate logic element is electrically connected with the first chip selection signal line interface through a first chip selection signal line.
Optionally, a first signal line interface for distinguishing data and commands is arranged on the liquid crystal display;
the input/output module is provided with a second signal line interface for distinguishing data and commands;
the first signal line interface for distinguishing data and commands and the second signal line interface for distinguishing data and commands are electrically connected through distinguishing data and command signal lines.
Optionally, a first reset signal line interface is arranged on the liquid crystal display;
the input/output module is provided with a second reset signal line interface;
the first reset signal line interface and the second reset signal line interface are electrically connected through a reset signal line.
Optionally, the control device of the lcd of the system chip further includes:
a direct memory access module electrically connected to the main control central processor 2;
and the driving butt joint module is electrically connected with the main control central processing unit 2.
The scheme of the utility model at least comprises the following beneficial effects:
the scheme of the utility model adopts a liquid crystal display; the main control central processing unit is electrically connected with the liquid crystal display through a signal line; the master control central processing unit is provided with a flash memory module and an input/output module. The problem of some low-cost SOCs do not support the tearing of image display that parallel interface control LCD and serial SPI bus control LCD lead to is solved, low-cost SOCs control LCD's display effect has been promoted effectively.
Drawings
FIG. 1 is a schematic structural diagram of a control device of a liquid crystal display of a system on a chip according to an embodiment of the present invention;
FIG. 2 is a timing diagram of an LCD according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a flash memory module according to an embodiment of the present invention;
description of reference numerals:
1-liquid crystal display; 11-first data signal line interface; 12-first write enable signal line interface; 13-first chip select signal line interface; 14-a first data and command distinguishing signal line interface; 15-first reset signal line interface; 2-a main control central processing unit; 21-a flash memory module; 211-second data signal line interface; 212-second write enable signal line interface; 213-address latch enable signal line interface; 214-command latch enable signal line interface; 22-an input-output module; 221-a second chip select signal line interface; 222-a second signal line interface to distinguish between data and commands; 223-second reset signal line interface; 3-a first or gate logic element; 4-second or gate logic element.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the utility model are shown in the drawings, it should be understood that the utility model may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art.
As shown in fig. 1, the present invention provides a control device for a liquid crystal display of a system-on-chip, comprising:
a liquid crystal display 1;
a main control central processor 2 electrically connected with the liquid crystal display 1 through a signal line; the main control central processing unit 2 is provided with a flash memory module 21 and an input/output module 22.
In this embodiment, a Liquid Crystal Display (LCD) 1 is electrically connected to a main control Central Processing Unit (CPU) 2 through at least one signal line, and the main control Central Processing Unit 2 is configured to control the Liquid Crystal Display 1 through the at least one signal line, so that the problem of image Display tearing caused by that a part of low-cost SOCs do not support a parallel interface control LCD and a serial SPI bus control LCD is solved, and the Display effect of the low-cost SOC control LCD is effectively improved;
the liquid crystal display 1 is used for receiving data transmitted by the main control central processing unit 2 and displaying images according to the data;
the main control central processing unit 2 is provided with a flash memory module 21(NANDFLASH) and an input/output module 22(General-purpose input/output, GPIO for short), the flash memory module 21 is used for simulating an interface control module of the liquid crystal display 1, the input/output module 22 is used for inputting and outputting signals, and the main control central processing unit 2 can control the liquid crystal display 1 through the flash memory module 21 and the input/output module 22.
In an optional embodiment of the present invention, the liquid crystal display 1 is provided with a first data signal line interface 11;
the flash memory module 21 is provided with a second data signal line interface 211;
the first data signal line interface 11 is electrically connected to the second data signal line interface 211 through a data signal line.
As shown in fig. 1, in this embodiment, the first data signal line interface 11 and the second data signal line interface 211 are preferably 8-bit data signal interfaces, and the first data signal line interface 11 and the second data signal line interface 211 are electrically connected through a data signal line and are used for transmitting data of the main control central processing unit 2 to the liquid crystal display 1;
it should be noted that, the data signal line transmits data according to the second data and command distinguishing signal line interface 222 of the input/output module 22, when the second data and command distinguishing signal line interface 222 outputs a low level, the data signal line transmits data as command data, and when the second data and command distinguishing signal line interface 222 outputs a high level, the data signal line transmits data as color-related data.
In an optional embodiment of the present invention, the liquid crystal display 1 is provided with a first write enable signal line interface 12;
a second write enable signal line interface 212 is arranged on the flash memory module 21;
the first write enable signal line interface 12 is electrically connected to the second write enable signal line interface 212 via a write enable signal line.
As shown in fig. 1, in the present embodiment, the first write enable signal line interface 12 and the second write enable signal line interface 212 are electrically connected by a write enable signal line, and the flash memory module 21 transmits a write enable signal to the liquid crystal display 1 through the write enable signal line.
In an optional embodiment of the present invention, the liquid crystal display 1 is provided with a first chip select signal line interface 13;
the flash memory module 21 is provided with an address latch enabling signal line interface 213 and a command latch enabling signal line interface 214;
the input/output module 22 is provided with a second chip selection signal line interface 221;
the first chip select signal line interface 13 is connected to the second chip select signal line interface 221, the address latch enable signal line interface 213, and the command latch enable signal line interface 214 through a logic circuit.
In this embodiment, since the data transmission of the Flash memory module 21 is based on the Flash timing sequence, each operation of the Flash memory module 21 involves issuing command data, issuing address data, and issuing data, and sending the command data and the address data to the liquid crystal display 1 causes the image display to be disordered; the command data, the address data and the data are preferably sent through an 8-bit signal line;
therefore, the first chip select signal line interface 13 and the second chip select signal line interface 221, the address latch enable signal line interface 213, and the command latch enable signal line interface 214 of the liquid crystal display 1 are connected through a logic circuit to exclude address data and command data during the data transmission from the flash memory module 21 to the liquid crystal display 1;
specifically, the logic circuit includes:
a first or gate logic element 3;
a second or gate logic element 4 electrically connected to an output of the first or gate logic element 3.
The first or gate logic element 3 is provided with a first input terminal, a second input terminal and a first output terminal; the first or gate logic element 3 is configured to perform or gate processing on the input signal at the first input end and the input signal at the second input end to obtain a first result signal, and use the first result signal as an output signal at a first output end;
the second or gate logic element 4 is provided with a third input terminal, a fourth input terminal and a second output terminal; the second or gate logic element 4 is configured to perform or gate processing on the input signal at the third input end and the input signal at the fourth input end to obtain a second result signal, and use the second result signal as an output signal at a second output end.
The address latch enable signal line interface 213 and the first input terminal of the first or gate logic element 3 are electrically connected through an address latch enable signal line;
the command latch enable signal line interface 214 and the second input terminal of the first or gate logic element 3 are electrically connected through a command latch enable signal line;
the first output terminal of the first or gate logic element 3 and the third input terminal of the second or gate logic element 4 are electrically connected through a result signal line;
the second chip selection signal line interface 221 is electrically connected to the fourth input terminal of the second or gate logic element 4 through a second chip selection signal line;
the second output terminal of the second or gate logic element 4 is electrically connected to the first chip select signal line interface 13 through a first chip select signal line.
In this embodiment, the first or gate logic element 3 and the second or gate logic element 4 connected approximately in series perform a first-stage or gate process on the address data output by the address latch enable signal line interface 213 and the command data output by the command latch enable signal line interface 214 to obtain a first result signal, and further perform a second-stage or gate process on the first chip select signal output by the second chip select signal line interface 221 and the first result signal obtained by the first-stage or gate process to obtain a second result signal, where the second result signal is used as a second chip select signal of the liquid crystal display 1 and is input to the liquid crystal display 1 through the first chip select signal line interface 13; wherein, the first chip select signal represents a data signal that the flash memory module 21 has issued data;
by the two-stage or gate processing, the address data output from the address latch enable signal line interface 213, the command data output from the command latch enable signal line interface 214, and the address data and the command data in the first chip select signal output from the second chip select signal line interface 221 can be ignored.
In an optional embodiment of the present invention, a first signal line interface 14 for distinguishing data and commands is disposed on the liquid crystal display 1;
the input/output module 22 is provided with a second signal line interface 222 for distinguishing data and commands;
the first data-and-command distinguishing signal line interface 14 and the second data-and-command distinguishing signal line interface 222 are electrically connected to each other through data-and-command distinguishing signal lines.
As shown in fig. 1, in the present embodiment, the first data and command distinguishing signal line interface 14 and the second data and command distinguishing signal line interface 222 are electrically connected through the data and command distinguishing signal line, and the main control cpu 2 transmits the data and command distinguishing signal to the first data and command distinguishing signal line interface 14 of the lcd 1 through the second data and command distinguishing signal line interface 222 of the input/output module 22.
In an optional embodiment of the present invention, the liquid crystal display 1 is provided with a first reset signal line interface 15;
the input/output module 22 is provided with a second reset signal line interface 223;
the first reset signal line interface 15 and the second reset signal line interface 223 are electrically connected through a reset signal line.
In this embodiment, the first reset signal line interface 15 and the second reset signal line interface 223 are electrically connected through a reset signal line, and the second reset signal line interface 223 of the input/output module 22 inputs the reset signal into the liquid crystal display 1, so as to ensure that the reset signals of the liquid crystal display 1 and the main control cpu 2 are consistent.
As shown in fig. 2 and fig. 3, in a specific embodiment, the timing sequence of the liquid crystal display 1 is as shown in fig. 2, the timing sequence of the flash memory module 21 in the main control central processing unit 2 is as shown in fig. 3, and the timing sequence of the liquid crystal display 1 is implemented by matching the timing sequence of the flash memory module 21 with the input/output module 22, as can be seen:
a is a reset signal RESX; b is a chip select signal CSX; c is a signal D/CX that distinguishes between data and commands; d is a write enable signal WRX; e is a read enable signal RDX; D7-D0 are data signals; f is a command latch enable signal CLE; g is a chip enable signal CE #; h is a write enable signal WE #; i is an address latch enable signal ALE; j is a second chip selection signal I/Ox; k is an 8bit data signal;
in the time sequence of the flash memory module 21 in the main control central processing unit 2, the level of the chip enable signal CE # is initially set to a high level state, when the level of the chip enable signal CE # is changed to a low level, the command latch enable signal CLE is changed from the low level state to the high level state, command data is output, and when the address latch enable signal ALE is in the high level state, address data is output;
as shown in fig. 3, in the timing diagram of the flash memory module 21 in the main control central processing unit 2, when the second chip select signal is at a high level, and when the CLE is at a high level and the ALE is at a low level, the signal output by the 8-bit data signal is the command data 05h of the flash memory module 21; when CLE is at low level and ALE is at high level, the signals output by the 8-bit data signal are the address data of Cold 1 and Cold 2 in sequence; when CLE changes to high level and ALE changes to low level, the signal output by the 8-bit data signal is the command data E0h of the flash memory module 21;
when the second chip selection signal changes from high level to low level, the CLE is low level, and the ALE is low level, the signals output by the 8-bit data signal are sequentially 26h, R1, G1, B1, R2, G2, etc., and the CLE signal and the ALE signal are processed through two-stage or gates by a logic circuit shown in fig. 1, so that the command data when the CLE is high level and the address data when the ALE is high level are ignored by the data received by the liquid crystal display 1; 26h is a first 8-bit signal output when the second chip selection signal changes from high level to low level, and the first 8-bit signal is used as a command signal of the liquid crystal display 1;
in the time sequence of the liquid crystal display 1, the reset signal RESX is always set in the state of high level "1", if the reset is needed, the reset signal is pulled down, that is, the reset signal RESX is set in the state of low level "0" to perform the reset;
when the first chip select signal CSX changes from high level to low level, the second data signal line interface 211 on the main control cpu 2 outputs command data, i.e., "00101100" in fig. 2, and when the signal D/CX for distinguishing data and command changes from low level to high level, the second data signal line interface 211 outputs color-related data, i.e., "R1, Bit 5", "G1, Bit 5" and "B1, Bit 5" of the pixel n in fig. 2, and "R1, Bit 5", "R1, Bit 4" of the pixel n +1, etc.; wherein, the data signals "00101100" of D7 to D0 in fig. 2 correspond to 26h in fig. 3, the pixel n in fig. 2 corresponds to R1, G1 and B1 in fig. 3, and the pixel n +1 and the like in fig. 2 corresponds to R2, G2 and the like in fig. 3;
it should be noted that the output command data of the second data signal line interface 211 may be picture turning, data writing, etc.;
the write enable signal WRX is always set in a time sequence change state, and when the write enable signal is at a high level, write-once data is acquired, and the read enable signal is always set in a high level "1" state.
In an optional embodiment of the present invention, the control device of the lcd of the system-on-chip further includes:
a direct memory access module electrically connected to the main control central processor 2;
and the driving butt joint module is electrically connected with the main control central processing unit 2.
In this embodiment, the dma module allows hardware devices of different speeds to interact without relying on a large amount of interrupt load of the main control cpu 2, and the load of the main control cpu 2 can be reduced by the dma module; the drive docking module is preferably used for docking with a frame buffer Framebuffer drive under the LINUX standard of an operating system;
it should be noted that, the main control central processing unit 2 preferably runs a gui interactive program for processing an image to be displayed on the liquid crystal display 1, where the processing is preferably based on Framebuffer.
The embodiment of the present invention is implemented by a liquid crystal display 1; a main control central processor 2 electrically connected with the liquid crystal display 1 through a signal line; the master control central processing unit 2 is provided with a flash memory module 21 and an input/output module 22; the problem of some low-cost SOCs do not support the tearing of image display that parallel interface control LCD and serial SPI bus control LCD lead to is solved, low-cost SOCs control LCD's display effect has been promoted effectively.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the utility model as defined in the appended claims.
Claims (10)
1. A control apparatus for a liquid crystal display of a systematized chip, comprising:
a liquid crystal display (1);
a main control central processor (2) electrically connected with the liquid crystal display (1) through a signal line; the master control central processing unit (2) is provided with a flash memory module (21) and an input/output module (22).
2. The control device of the liquid crystal display of the systematized chip according to claim 1, wherein a first data signal line interface (11) is provided on the liquid crystal display (1);
a second data signal line interface (211) is arranged on the flash memory module (21);
the first data signal line interface (11) and the second data signal line interface (211) are electrically connected through a data signal line.
3. The control device of the liquid crystal display of the systemized chip according to claim 1, wherein a first write enable signal line interface (12) is provided on the liquid crystal display (1);
a second write enable signal line interface (212) is arranged on the flash memory module (21);
the first write enable signal line interface (12) and the second write enable signal line interface (212) are electrically connected through a write enable signal line.
4. The control device of the liquid crystal display of the systemized chip according to claim 1, wherein a first chip select signal line interface (13) is disposed on the liquid crystal display (1);
the flash memory module (21) is provided with an address latch enabling signal line interface (213) and a command latch enabling signal line interface (214);
a second chip selection signal line interface (221) is arranged on the input/output module (22);
the first chip selection signal line interface (13) is connected with the second chip selection signal line interface (221), the address latch enable signal line interface (213) and the command latch enable signal line interface (214) through a logic circuit.
5. The apparatus for controlling the LCDs of the system on chip of claim 4, wherein the logic circuit comprises:
a first or gate logic element (3);
a second OR gate logic element (4) electrically connected to an output of the first OR gate logic element (3).
6. The control device of the liquid crystal display of the systematized chip according to claim 5, wherein the first or gate logic element (3) is provided with a first input terminal, a second input terminal and a first output terminal; the first or gate logic element (3) is configured to perform or gate processing on the input signal at the first input end and the input signal at the second input end to obtain a first result signal, and use the first result signal as an output signal at a first output end;
the second OR gate logic element (4) is provided with a third input end, a fourth input end and a second output end; and the second OR gate logic element (4) is used for carrying out OR gate processing on the input signal of the third input end and the input signal of the fourth input end to obtain a second result signal, and the second result signal is used as an output signal of a second output end.
7. The control device of the liquid crystal display of the systematized chip according to claim 6, wherein the address latch enable signal line interface (213) and the first input terminal of the first or gate logic element (3) are electrically connected through an address latch enable signal line;
the command latch enable signal line interface (214) and the second input end of the first OR gate logic element (3) are electrically connected through a command latch enable signal line;
a first output end of the first OR gate logic element (3) and a third input end of the second OR gate logic element (4) are electrically connected through a result signal line;
the second chip selection signal line interface (221) is electrically connected with a fourth input end of the second OR gate logic element (4) through a second chip selection signal line;
the second output end of the second OR gate logic element (4) is electrically connected with the first chip selection signal line interface (13) through a first chip selection signal line.
8. The control device of the liquid crystal display of the systematized chip according to claim 1, wherein a first signal line interface (14) for distinguishing data and commands is provided on the liquid crystal display (1);
a second signal line interface (222) for distinguishing data and commands is arranged on the input/output module (22);
the first data and command distinguishing signal line interface (14) and the second data and command distinguishing signal line interface (222) are electrically connected through data and command distinguishing signal lines.
9. The control device of the liquid crystal display of the systematized chip according to claim 1, wherein a first reset signal line interface (15) is provided on the liquid crystal display (1);
a second reset signal line interface (223) is arranged on the input/output module (22);
the first reset signal line interface (15) and the second reset signal line interface (223) are electrically connected through a reset signal line.
10. The apparatus for controlling a liquid crystal display of a systematized chip according to claim 1, further comprising:
the direct memory access module is electrically connected with the master control central processor (2);
and the driving butt joint module is electrically connected with the main control central processing unit (2).
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