CN216649833U - Pixel reading circuit and image sensor - Google Patents

Abstract

The utility model discloses a pixel reading circuit and an image sensor. The pixel readout circuit comprises a pixel sensing module, a plurality of voltage-to-current modules and a mirror module. The pixel sensing module comprises a plurality of pixel sub-sensing modules, and each pixel sub-sensing module correspondingly generates a sensing voltage; the pixel sensing module is connected with the pixel sensing module and used for correspondingly converting a plurality of sensing voltages into a plurality of sensing currents; and the mirror image module is connected with the voltage-to-current conversion module and outputs the sum of all the induction currents. According to the pixel reading circuit and the image sensor, when the plurality of pixel sub-sensing modules read out, the corresponding plurality of sensing voltages are generated firstly, then the plurality of sensing voltages are converted into the corresponding plurality of sensing currents, the plurality of sensing currents are combined to obtain the total sensing current, and the total sensing current is quantized based on the total sensing current, so that quantization errors of sensing signals of pixels are improved, and the cost is reduced.

Description

Pixel reading circuit and image sensor

Technical Field

The present invention relates to the field of image sensors, and in particular, to a pixel readout circuit and an image sensor.

Background

With the development of technology, computing devices are increasingly being used in various levels of modern society and make great contributions to the development of modern society, including, but not limited to, digital cameras, video cameras, smart phones, navigation systems, and the like. In particular, in recent years, apparatuses having a function of capturing images, such as digital cameras, have become increasingly popular, and imaging quality thereof is increasingly demanded.

In a conventional image sensor, one or more pixels correspond to a pixel readout circuit, and the pixel readout circuit is configured to read out an induced signal of each pixel, and perform quantization, amplification, and other processes according to the induced signal (such as voltage) to obtain image data. Different quantization methods can be adopted according to different application scenes. However, there are many problems in the quantization process of voltages, particularly the process of voltage merging quantization.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a pixel reading circuit and an image sensor, which can solve the problems of error quantization of sensing signals of pixels, high cost and the like.

The utility model provides a pixel reading circuit, which comprises a pixel sensing module, a plurality of voltage-to-current conversion modules and a mirror image module, wherein the pixel sensing module is used for sensing a pixel voltage; the pixel sensing module comprises a plurality of pixel sub-sensing modules, and each pixel sub-sensing module correspondingly generates a sensing voltage; the pixel sensing module is connected with the pixel sensing module, and the pixel sensing module is connected with the pixel sensing module and used for converting a plurality of sensing voltages into a plurality of sensing currents; the mirror image module and the voltage-to-current conversion module are connected in series and output the sum of the induction currents.

In one embodiment, the voltage-to-current module includes a first voltage input unit and a first resistor; the first voltage input unit comprises a first path end, a second path end and a first output connecting end, the first output connecting end is connected with the mirror image module, the first path end receives the corresponding induction voltage, the second path end is connected with the first end of the first resistor, and the second end of the first resistor is grounded.

In one embodiment, the first voltage input unit is an NMOS transistor, and a gate of the NMOS transistor is used as the first pass end; or, the first voltage input unit includes an operational amplifier and an NMOS transistor connected to each other, and an anode of the operational amplifier serves as the first path terminal.

In one embodiment, the first resistor is a controllable resistor.

In an embodiment, the pixel readout circuit further includes a regulator, and the regulator is connected to the plurality of first resistors, and sends corresponding regulation signals to the plurality of first resistors according to the weight signals to control the magnitudes of the resistances of the plurality of first resistors, so as to control the magnitudes of the currents of the induced currents generated by the plurality of voltage-to-current modules.

In one embodiment, the regulator includes a plurality of sub-regulation circuits corresponding to the first resistors, the input ends of the sub-regulation circuits are configured to receive resistance control signals, and the output ends of the sub-regulation circuits are connected to the corresponding first resistors to control the resistance of the corresponding first resistors, where the sub-regulation circuits include DAC conversion circuits.

In one embodiment, the mirror module includes at least a summing sub-module and an output sub-module.

In one embodiment, the summing submodule at least comprises a second voltage input unit and a third voltage input unit; the second voltage input unit comprises a third path end, a fourth path end and a second control end, and the third path end of the second voltage input unit is connected with the first power supply; the third voltage input unit comprises a fifth path end, a sixth path end and a third control end, the fifth path end of the third voltage input unit is connected with the fourth path end of the second voltage input unit, the sixth path end of the third voltage input unit is connected with the output connection end of the voltage-to-current conversion module and the second control end of the second voltage input unit, and the third control end of the third voltage input unit receives the bias voltage signal.

In one embodiment, the output submodule at least comprises a fourth voltage input unit and a fifth voltage input unit; the fourth voltage input unit comprises a seventh path end, an eighth path end and a fourth control end, the seventh path end of the fourth voltage input unit is connected with the first power supply, and the fourth control end of the fourth voltage input unit is connected with the second control end of the second voltage input unit; the fifth voltage input unit comprises a ninth path end, a tenth path end and a fifth control end, the ninth path end of the fifth voltage input unit is connected with the eighth path end of the fourth voltage input unit, the tenth path end of the fifth voltage input unit outputs a pixel signal, and the fifth control end of the fifth voltage input unit receives the bias voltage signal.

In one embodiment, the exposure control device further comprises a current determination unit, the current determination unit is connected with each voltage-to-current module, and the current determination unit determines that an exposure trigger signal is generated when a total induced current obtained by combining the induced currents is greater than a current set value.

In one embodiment, the pixel sub-sensing module includes at least one set of photoelectric conversion unit and a sixth voltage input unit; the first end of the photoelectric conversion unit is connected with a first reference voltage; the sixth voltage input unit comprises an eleventh channel end, a tenth channel end and a sixth control end, the eleventh channel end is correspondingly connected with the signal input end of the voltage-to-current conversion module, the tenth channel end is correspondingly connected with the second end of the photoelectric conversion unit, and the sixth control end receives the timing control signal.

The utility model also discloses an image sensor comprising the pixel readout circuit.

The embodiment of the utility model discloses a pixel reading circuit and an image sensor, when a plurality of pixel sub-sensing modules read out, a plurality of corresponding sensing voltages are generated firstly, then the sensing voltages are converted into a plurality of corresponding sensing currents, the sensing currents are combined to obtain a total sensing current, and quantization is carried out based on the total sensing current, so that quantization errors of sensing signals of pixels are improved, and the cost is reduced.

Drawings

Fig. 1 is a schematic diagram of a partial structure of a pixel readout circuit of the prior art.

Fig. 2 is a schematic diagram of circuit connections of a pixel readout circuit according to an embodiment of the utility model.

Fig. 3 is a schematic diagram of circuit connections of a pixel readout circuit according to another embodiment of the utility model.

Fig. 4 is a schematic diagram of circuit connections of a pixel readout circuit according to another embodiment of the utility model.

Fig. 5 is a schematic diagram of circuit connections of a pixel readout circuit according to another embodiment of the utility model.

Detailed Description

To further illustrate the technical means and effects of the present invention for achieving the intended purpose of the utility model, the following detailed description is given to the specific embodiments, structures, features and effects of the present invention in conjunction with the accompanying drawings and examples. Before describing the technical solutions provided by the present invention, the present invention first describes the problems existing in the prior art.

In some applications with low requirements on images, such as applications that only the motion of a related behavior needs to be captured, the quantization method is to combine the sensing signals and then perform analog-to-digital conversion, and accordingly, there are two circuit structures for pixel readout. The first circuit structure is a direct short circuit, for example, the sensing signal is directly transmitted to the control terminal of the same transistor unit, but when the RGB component signals of one or two of the RGB component signals are too small, the RGB component signals may not be read out, and the quantized image may become dark or even black, that is, the quantization is wrong. The second circuit structure is a linear addition of capacitors, for example, sensing signals are respectively transmitted to first ends of four capacitors, second ends of the four capacitors are connected to control ends of the same transistor unit, fig. 1 is a schematic diagram of a partial structure of a pixel readout circuit in the prior art, as shown in fig. 1, sensing signals corresponding to R sub-pixels, B sub-pixels, GR sub-pixels, and GB sub-pixels are respectively transmitted to first ends of the four capacitors, and second ends of the four capacitors are connected to control ends of the same transistor unit in the pixel readout circuit.

Fig. 2 is a schematic diagram of circuit connections of a pixel readout circuit according to an embodiment of the utility model. Referring to fig. 2, in the present embodiment, the pixel readout circuit includes a pixel sensing module 100, a plurality of voltage-to-current modules 200, and a mirror module 300. The pixel sensing module 100 includes a plurality of pixel sub-sensing modules 110, and generates a plurality of sensing voltages corresponding to the plurality of pixel sub-sensing modules 110 one to one. The voltage-to-current modules 200 are connected in parallel and are all connected to the pixel sensing module 100 to convert the plurality of sensing voltages into a plurality of corresponding sensing currents. The mirror module 300 is connected to the plurality of voltage-to-current modules 200, and outputs the sum of the plurality of induced currents.

Specifically, in the present embodiment, the sensing signals of one or more pixels are read out by one pixel readout circuit, so that the image can be read out entirely by a plurality of pixel readout circuits. First, the pixel sensing module 100 may include a plurality of pixel sub-sensing modules 110, and generate a plurality of sensing voltages corresponding to the plurality of pixel sub-sensing modules 110 one to one. In one embodiment, each of the pixel sub-sensing modules 110 corresponds to a plurality of pixels, and the plurality of pixels output a sensing voltage correspondingly. In another embodiment, each pixel sub-sensing module 110 corresponds to one pixel.

Then, the pixel sensing module 100 inputs the plurality of sensing voltages to the corresponding plurality of voltage-to-current modules 200, and the plurality of voltage-to-current modules 200 are configured to receive the plurality of sensing voltages and convert the received plurality of sensing voltages into a corresponding plurality of sensing currents. The mirror module 300 is connected to the plurality of voltage-to-current modules 200, and the plurality of voltage-to-current modules 200 are connected in parallel, and a total induced current is output according to the principle that the total current in the parallel circuit is equal to the sum of the currents of the branches, so that the mirror module 300 can obtain the total induced current corresponding to the sum of the plurality of induced currents and correspondingly output according to the total induced current. Because the total induced current is the sum of the induced currents, and the induced currents are obtained by converting the induced voltages, the total induced current is obtained by converting and combining the induced voltages, and the quantization can be completed by performing analog-to-digital conversion on the total induced current or the converted signal of the total induced current, so that corresponding image data can be obtained. Because the magnitude of the total induced current is related to the magnitude of the induced voltage of the corresponding sub-pixel, even if the brightness of one or more pixels is too small, the brightness of the pixel can be obtained by data processing of quantized image data, and the image brightness restoration degree is higher.

Fig. 3 is a schematic diagram of circuit connections of a pixel readout circuit according to another embodiment of the utility model. As shown in fig. 3, each voltage-to-current conversion module 200 includes a first voltage input unit T1 and a first resistor R1, and the first voltage input unit T1 is connected to the pixel sensing module 100 and is configured to receive a corresponding sensing voltage output by the pixel sensing module 100, where the sensing voltage is converted into a corresponding sensing current through the voltage-to-current conversion module 200 having the first resistor R1. The first voltage input unit T1 includes a first path end, a second path end, and a first output connection end, the first output connection end of the first voltage input unit T1 is connected to the mirror module 300, the first path end of the first voltage input unit T1 receives a corresponding induced voltage of the plurality of induced voltages, the second path end of the first voltage input unit T1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the first end of the first resistor R1. In this example, the first output connections of the plurality of first voltage input units T1 are connected to form the output connections of the plurality of voltage-to-current modules 200; the first path terminal of the first voltage input unit T1 serves as a signal input terminal of the voltage-to-current module 200.

However, the specific connection manner of the present embodiment is not limited, for example, in fig. 3, the first output connection terminal of the first voltage input unit T1 is connected to the mirror module 300, the second path terminal of the first voltage input unit T1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded, or the first terminal of the first resistor R1 is connected to the mirror module 300, the second terminal of the first resistor R1 is connected to the first output connection terminal of the first voltage input unit T1, and the second path terminal of the first voltage input unit T1 is grounded. In the embodiment shown in fig. 3, the first voltage input unit T1 may be an NMOS transistor, that is, the first pass terminal of the first voltage input unit T1 is a gate of the NMOS transistor, the first output connection terminal of the first voltage input unit T1 is a drain of the NMOS transistor, and the second pass terminal of the first voltage input unit T1 is a source of the NMOS transistor; alternatively, the first voltage input unit T1 may also include an operational amplifier and an NMOS transistor, wherein the first path terminal of the first voltage input unit is the first input terminal (i.e., positive terminal) of the operational amplifier, the output terminal of the operational amplifier is connected to the gate terminal of the NMOS transistor, the drain terminal of the NMOS transistor is the first output connection terminal of the first voltage input unit T1 and is connected to the mirror module 300, and the source terminal of the NMOS transistor and the second input terminal (i.e., negative terminal) of the operational amplifier together form the second path terminal of the first voltage input unit T1 and are connected to the first resistor R1. It will be appreciated that the operational amplifier may be a unity gain operational amplifier.

In an embodiment, as shown in fig. 3, the pixel sub-sensing module 110 may include at least one photoelectric conversion unit PD and at least one sixth voltage input unit T6; the first terminal of the photoelectric conversion unit PD is connected to a first reference voltage, for example, ground; the sixth voltage input unit T6 includes an eleventh path terminal, a tenth path terminal, and a sixth control terminal, the tenth path terminal of the sixth voltage input unit T6 is connected to the second terminal of the photoelectric conversion unit PD, the eleventh path terminal of the sixth voltage input unit T6 is connected to the corresponding signal input terminal (the first path terminal of the first voltage input unit T1 in the embodiment) of the voltage-to-current module 200, and the sixth control terminal of the sixth voltage input unit T6 receives the timing control signal. The photoelectric conversion unit PD corresponds to the corresponding sub-pixel, and generates charges after receiving light. When the sixth voltage input unit T6 is in a turn-on state by receiving a corresponding timing control signal, the charges accumulated in the photoelectric conversion unit PD are transferred to the floating diffusion region of the connecting voltage-to-current block 200, and an induced voltage corresponding to the sub-pixel is generated. In an embodiment, the sixth voltage input unit T6 may be an NMOS transistor, but the utility model is not limited thereto. Of course, the pixel sub-sensing module 110 may further include a reset transistor, a source follower transistor, and the like.

In an embodiment, at least one pixel sub-sensing module 110 corresponds to sensing voltages in at least two photoelectric conversion units PD. That is, one pixel sub-sensing module 110 may sum the sensing voltages in at least two photoelectric conversion units PD for quantization and subsequent data processing of image data.

Therefore, when one or more pixels are read out simultaneously, the pixel reading circuit of the embodiment generates a plurality of induction voltages corresponding to the plurality of pixel sub-induction modules one to one, converts the plurality of induction voltages into a plurality of corresponding induction currents, and obtains corresponding pixel image data through quantization and other processing, so that the pixels have higher image brightness reduction degree, image blackening caused by undersize brightness values of one or two pixels can be avoided, namely quantization errors of induction signals of the pixels are improved, and cost is reduced because capacitors are not used.

In an embodiment, the pixel sensing module 100 includes four pixel sub-sensing modules 110, and the four pixel sub-sensing modules 110 respectively generate four sensing voltages corresponding to a red sub-pixel (R), a blue sub-pixel (B), a green-red sub-pixel (Gr), and a green-blue sub-pixel (Gb), that is, one pixel may be divided into one red sub-pixel, one blue sub-pixel, one green-red sub-pixel, and one green-blue sub-pixel according to colors, so as to adapt to the more sensitive characteristic of human eyes to green light, so that a user obtains a better color experience. It is understood that in some embodiments, the four-pixel sub-sensing module 110 may generate four sensing voltages corresponding to four same-color sub-pixels (e.g., red sub-pixel R). Of course, in other embodiments, one pixel sub-sensing module 110 may generate one sensing voltage corresponding to a plurality of sub-pixels (e.g., red sub-pixel R) of the same color. The four induced voltages are converted into corresponding four induced currents by the scheme of the utility model, and the sum of the four induced currents, namely the total induced current, is obtained, so that the quantization is carried out based on the total induced current.

In one embodiment, as shown in FIG. 3, the mirror module 300 may include a summing submodule 310 and an output submodule 320. The summing sub-module 310 may obtain a total induced current based on kirchhoff effect, for example, the summing sub-module 310 may be configured to generate a total induced current having a magnitude that is a sum of magnitudes of induced currents generated by the connected voltage-to-current modules 200 upon receiving a control signal, such as a bias voltage signal. The output sub-module 320 and the summing sub-module 310 may form a mirror circuit for outputting the total induced current to represent the pixel signal to be acquired, and the pixel signal may be sent to the analog-to-digital conversion module for analog-to-digital conversion to complete quantization.

In an embodiment, as shown in fig. 3, the summing sub-module 310 may include at least a second voltage input unit T2 and a third voltage input unit T3. The second voltage input unit T2 includes a third path end, a fourth path end, and a second control end, and the third path end of the second voltage input unit T2 is connected to the first power supply VDD 1; the third voltage input unit T3 includes a fifth path terminal, a sixth path terminal and a third control terminal, the fifth terminal of the third voltage input unit T3 is connected to the fourth terminal of the second voltage input unit T2, the sixth path terminal of the third voltage input unit T3 is connected to the output connection terminals (the first output connection terminals of the plurality of first voltage input units T1 in one embodiment) of the plurality of voltage-to-current conversion modules 200 and the second control terminal of the second voltage input unit T2, and the third control terminal of the third voltage input unit T3 receives the bias voltage signal. In an embodiment, the second voltage input unit T2 and the third unit may be PMOS transistors, but the utility model is not limited thereto.

In an embodiment, as shown in fig. 3, the output sub module 320 may include at least a fourth voltage input unit T4 and a fifth voltage input unit T5. The fourth voltage input unit T4 includes a seventh path terminal, an eighth path terminal, and a fourth control terminal, the seventh path terminal of the fourth voltage input unit T4 is connected to the first power supply VDD1, and the fourth control terminal of the fourth voltage input unit T4 is connected to the second control terminal of the second voltage input unit. The fifth voltage input unit T5 includes a ninth path terminal, a tenth path terminal, and a fifth control terminal, the ninth path terminal of the fifth voltage input unit T5 is connected to the eighth path terminal of the fourth voltage input unit T4, the tenth path terminal of the fifth voltage input unit T5 outputs a pixel signal, and the fifth control terminal of the fifth voltage input unit T5 receives a bias voltage signal.

Fig. 4 is a schematic diagram of circuit connections of a pixel readout circuit according to another embodiment of the utility model. The present embodiment is substantially the same as the previous embodiments, except that the pixel readout circuit may further include a regulator 400, each of the first resistors R1 is a controllable resistor, the regulator 400 is connected to the first resistors R1, and sends a corresponding adjustment signal to the first resistors R1 according to the weight signal to control the resistance of the first resistors R1, so as to control the current of the induced currents generated by the voltage-to-current modules 200. For example, when a user needs to make an image display green brighter, the brightness of the green G needs to be increased, and then the corresponding weight signal is sent to the adjuster 400, so that the adjuster 400 adjusts the resistance value of the first resistor R1 corresponding to the green sub-pixel, for example, the resistance value of the first resistor R1 is reduced, so that the induced current generated by the voltage-to-current module 200 is increased, the green data corresponding to the quantized image data is increased, and the green brighter when the image is displayed.

In one embodiment, the regulator 400 may include a sub-regulation circuit corresponding to the first resistor R1, an input terminal of the sub-regulation circuit being configured to receive a resistance control signal, and an output terminal of the sub-regulation circuit being connected to the corresponding first resistor R1 to control the resistance of the corresponding first resistor R1. The sub-regulation circuit comprises a DAC (digital-to-analog converter) circuit, and is used for performing digital-to-analog conversion on the resistance control signal and outputting the resistance control signal to control the resistance of the corresponding first resistor R1. The resistance control signal may be a sub-signal of the weight signal.

Fig. 5 is a schematic diagram of circuit connections of a pixel readout circuit according to another embodiment of the utility model. As shown in fig. 5, the present embodiment is substantially the same as the embodiment of fig. 2, except that the pixel readout circuit may further include a current determination unit 500, the current determination unit 500 is connected to the plurality of voltage-to-current modules 200, and the current determination unit 500 is configured to determine that the total induced current obtained by combining the plurality of induced currents is greater than a current setting value, and generate an exposure trigger signal, so that the sampling and quantization may be automatically performed when the image exposure brightness reaches a threshold value, so that the generated image is not too bright or too dark. In an embodiment, the exposure trigger signal may be configured to activate a plurality of sample-and-hold units, the plurality of sample-and-hold units are configured to sample respective induced voltages or corresponding induced currents, and the image data quantized by sampling is the brightness data of the corresponding pixel. In one embodiment, the exposure trigger signal may be used to activate an analog-to-digital converter to quantize the total induced current, and the quantized image data may be used to process the image data to obtain the brightness data of each pixel.

Specifically, the pixel readout circuit of this embodiment may further have an automatic exposure sampling function, the multiple voltage-to-current modules 200 are connected in parallel to enable the multiple induced currents to be linearly added to obtain a total induced current, the current determination unit 500 may determine that the light collected by the corresponding sub-pixel has satisfied the brightness requirement of the image sub-pixel according to that the total induced current is greater than the current set value, at this time, an exposure trigger signal should be generated to sample each induced current, so as to obtain image data for determining the brightness of the corresponding sub-pixel according to the quantization and other processing of the multiple induced currents at this time. In an embodiment, the current determination unit 500 may include one or more comparators. In an embodiment, this embodiment may be applied to global automatic exposure of an image, where a plurality of pixel readout circuits operate simultaneously, for example, each column of pixels may correspond to one pixel readout circuit, and as long as the current determination unit 500 in any one of the pixel readout circuits generates an exposure trigger signal when determining that the total induced current is greater than the current set value, all the pixel readout circuits perform sampling and quantization simultaneously, thereby implementing global automatic exposure of an image.

An embodiment of the present invention further provides an image sensor, which includes the pixel readout circuit according to any one of the above embodiments. Please refer to the foregoing embodiments, and repeated descriptions are omitted herein for implementing the image sensor of this embodiment.

According to the image sensor provided by the embodiment of the utility model, when one or more pixels are read out simultaneously, a plurality of induction voltages corresponding to a plurality of sub-pixels one by one are generated, and then the induction voltages are converted into a plurality of corresponding induction currents, so that quantization can be carried out according to the induction currents, the quantization error of induction signals of the pixels can be improved, and the cost can be reduced.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the utility model as defined by the appended claims.

Claims (12)

1. A pixel readout circuit, comprising:

the pixel sensing module comprises a plurality of pixel sub-sensing modules, and each pixel sub-sensing module correspondingly generates a sensing voltage;

the pixel sensing module is connected with the pixel sensing module, and the pixel sensing module is connected with the pixel sensing module and used for converting a plurality of sensing voltages into a plurality of sensing currents;

and the mirror image module is connected with the voltage-to-current conversion module and outputs the sum of the induction currents.

2. A pixel readout circuit according to claim 1, wherein the voltage to current block comprises a first voltage input unit and a first resistor;

the first voltage input unit is provided with a first path end, a second path end and a first output connection end, the first output connection end is connected with the mirror image module, the first path end receives the corresponding induction voltage, the second path end is connected with the first end of the first resistor, and the second end of the first resistor is grounded.

3. The pixel readout circuit of claim 2, wherein the first voltage input unit is an NMOS transistor, a gate of the NMOS transistor serving as the first pass terminal; or, the first voltage input unit includes an operational amplifier and an NMOS transistor connected to each other, and an anode of the operational amplifier serves as the first path terminal.

4. A pixel readout circuit according to claim 2, wherein the first resistance is a controllable resistance.

5. The pixel readout circuit of claim 4, further comprising a regulator, the regulator being connected to each of the plurality of first resistors and sending a corresponding regulation signal to the plurality of first resistors according to the weighting signal to control the magnitudes of the resistances of the plurality of first resistors, thereby controlling the magnitudes of currents induced by the plurality of voltage-to-current modules.

6. The pixel readout circuit of claim 5, wherein the regulator comprises a plurality of sub-regulation circuits corresponding to the first resistors, the input terminals of the sub-regulation circuits being configured to receive resistance control signals, the output terminals of the sub-regulation circuits being coupled to the corresponding first resistors to control the resistance of the corresponding first resistors, and wherein the sub-regulation circuits comprise DAC conversion circuits.

7. A pixel readout circuit according to claim 1, wherein the mirroring module comprises at least a summing sub-module and an output sub-module.

8. A pixel readout circuit according to claim 7, wherein the summing sub-module comprises a second voltage input unit and a third voltage input unit;

the second voltage input unit comprises a third path end, a fourth path end and a second control end, and the third path end of the second voltage input unit is connected with the first power supply;

the third voltage input unit comprises a fifth path end, a sixth path end and a third control end, the fifth path end of the third voltage input unit is connected with the fourth path end of the second voltage input unit, the sixth path end of the third voltage input unit is connected with the output connection end of the voltage-to-current conversion module and the second control end of the second voltage input unit, and the third control end of the third voltage input unit receives the bias voltage signal.

9. A pixel readout circuit according to claim 8, wherein the output submodule includes a fourth voltage input unit and a fifth voltage input unit;

the fourth voltage input unit comprises a seventh path end, an eighth path end and a fourth control end, the seventh path end of the fourth voltage input unit is connected with the first power supply, and the fourth control end of the fourth voltage input unit is connected with the second control end of the second voltage input unit;

the fifth voltage input unit comprises a ninth path end, a tenth path end and a fifth control end, the ninth path end of the fifth voltage input unit is connected with the eighth path end of the fourth voltage input unit, the tenth path end of the fifth voltage input unit outputs a pixel signal, and the fifth control end of the fifth voltage input unit receives the bias voltage signal.

10. The pixel readout circuit of claim 1, further comprising a current determination unit coupled to each of the voltage-to-current modules, the current determination unit configured to generate an exposure trigger signal when a total induced current resulting from a combination of the induced currents is greater than a current set value.

11. The pixel readout circuit of any of claims 1-10, wherein the pixel sub-sensing module comprises at least one set of a photoelectric conversion unit and a sixth voltage input unit;

the first end of the photoelectric conversion unit is connected with a first reference voltage;

the sixth voltage input unit comprises an eleventh channel end, a tenth channel end and a sixth control end, the eleventh channel end is correspondingly connected with the signal input end of the voltage-to-current conversion module, the tenth channel end is correspondingly connected with the second end of the photoelectric conversion unit, and the sixth control end receives the timing control signal.

12. An image sensor comprising a pixel readout circuit according to any of claims 1-11.

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