CN113301279A

CN113301279A - Image sensor and imaging apparatus including the same

Info

Publication number: CN113301279A
Application number: CN202110183993.0A
Authority: CN
Inventors: 郑演焕; 高京民
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2020-02-24
Filing date: 2021-02-10
Publication date: 2021-08-24
Also published as: US20210266477A1; US11503229B2; KR20210107957A

Abstract

An image forming apparatus includes: a pixel array having a plurality of pixels, each pixel configured to generate a reset signal and an image signal; a sampling circuit including a plurality of samplers connected to the column lines, wherein each sampler generates a first comparison signal by comparing the reset signal with the ramp signal, and generates a second comparison signal by comparing the image signal with the ramp signal. The ADC converts each of the first comparison signal and the second comparison signal into a digital signal. Each sampler performs an auto-zero operation for initializing itself before performing a comparison for the reset signal in the first mode, and performs a corresponding auto-zero operation before performing a comparison for each of the reset signal and the image signal in the second mode.

Description

Image sensor and imaging apparatus including the same

Cross Reference to Related Applications

This application claims priority to korean patent application No. 10-2020-0022363, filed 24.2.2020 in the korean intellectual property office, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Example embodiments of the present disclosure generally relate to an image sensor and an imaging apparatus including the same, and more particularly, to a high dynamic range image sensor.

Background

Image sensors are semiconductor-based sensors that generate electrical signals in response to light. The image sensor may include: a pixel array having a plurality of pixels; and a logic circuit configured to drive the pixel array and generate an image. Each pixel may include: a photodiode configured to generate an electric charge in response to light; and a pixel circuit configured to convert the electric charge generated by the photodiode into an electric signal. Image sensors may be widely applied to cameras that obtain still images or video, where the camera may be a standalone camera, or part of a smartphone, tablet PC, laptop, television, vehicle, or the like.

In a High Dynamic Range (HDR) image sensor, the illuminance (illumiance) sensed by each pixel may be determined to be in a low illuminance range or a high illuminance range. With this approach, an analog-to-digital converter (ADC) used to digitize luminance values with a fixed number of bits can distinguish luminance values with a higher overall dynamic range. Thus, changes within the area of the image frame can be more accurately captured with the representative gray values, which would otherwise be indistinguishable because the area is too bright or too dark.

Disclosure of Invention

Example embodiments of the present disclosure provide an imaging device and an image sensor including a sampler that may perform an auto-zero operation in a different manner in a high-gain sampling operation than in a low-gain sampling operation, so that reset noise may be removed and power consumption may be significantly reduced.

According to an example embodiment of the present disclosure, an image forming apparatus includes: a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels is configured to generate a reset signal and an image signal. The sampling circuit may include a plurality of sampling circuits connected to a plurality of column lines. Each of the sampling circuits is configured to generate a first comparison signal by comparing the reset signal with the ramp signal, and generate a second comparison signal by comparing the image signal with the ramp signal. The analog-to-digital converter is configured to convert each of the first and second comparison signals to a respective digital signal. The column driver is configured to generate image data based on the first comparison signal and the second comparison signal converted into digital signals. Each of the sampling circuits performs an auto-zero operation for initializing itself before performing comparison for the reset signal in the first mode, and performs a corresponding auto-zero operation before performing comparison for each of the reset signal and the image signal in the second mode.

According to an example embodiment of the present disclosure, an image sensor includes: a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels is configured to generate a pixel signal; a plurality of samplers connected to the plurality of column lines and configured to output a comparison signal by comparing the pixel signal with the ramp signal; and an analog-to-digital converter configured to generate image data by converting the comparison signal into a digital signal, wherein each of the plurality of samplers includes: a comparator; a first auto-zero switch configured to be connected between a first input node and a first output node of the comparator; a second auto-zero switch configured to be connected between a second input node and a second output node of the comparator; a first capacitor configured to be connected between a first input node and a first node; a second capacitor connected between the second input node and the second node; a first switch connected between a first node and an input terminal of the ramp signal; a second switch connected between the first node and an input terminal of the pixel signal; and a third switch and a fourth switch connected in parallel between the second node and the input terminal of the pixel signal.

According to an example embodiment of the inventive concepts, an image sensor includes: a plurality of pixels connected to a plurality of row lines and a plurality of column lines and configured to generate a reset signal, a first image signal, and a second image signal; a plurality of sampling circuits connected to the plurality of column lines and configured to generate comparison signals by sequentially comparing each of the reset signal, the first image signal, and the second image signal with the up-ramp signal or the down-ramp signal; and an analog-to-digital converter configured to generate image data by converting the comparison signal into a digital signal. Each sampling circuit operates at a first amplification gain and generates a comparison signal using the down-ramp signal in the first mode, and operates at a second amplification gain smaller than the first amplification gain and generates the comparison signal using the up-ramp signal in the second mode.

Drawings

The foregoing and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a diagram illustrating an imaging apparatus according to an example embodiment of the present disclosure;

fig. 2 is a diagram illustrating an image sensor according to an example embodiment of the present disclosure;

fig. 3 is a circuit diagram illustrating a ramp signal generator included in an image sensor according to an example embodiment of the present disclosure;

fig. 4 is a diagram showing a layout of an image sensor according to an example embodiment of the present disclosure;

fig. 5 is a circuit diagram illustrating a pixel included in an image sensor according to an example embodiment of the present disclosure;

fig. 6 is a circuit diagram illustrating a sampling circuit included in an image sensor according to an example embodiment of the present disclosure;

fig. 7 is a circuit diagram showing a comparator and a first peripheral circuit of the sampling circuit shown in fig. 6;

fig. 8 is a diagram illustrating a method of operation of a sampling circuit according to an example embodiment of the present disclosure;

fig. 9 is a timing diagram showing an example of the sampling circuit operating in the first mode;

fig. 10A is a diagram illustrating a state of a sampling circuit in an auto-zero (auto-zero) period when the sampling circuit operates in a first mode according to an example embodiment of the present disclosure, and fig. 10B is a diagram illustrating a state of the sampling circuit in a comparison period when the sampling circuit operates in the first mode according to an example embodiment of the present disclosure;

fig. 11 is a timing diagram showing an example of the sampling circuit operating in the second mode;

fig. 12A is a diagram illustrating a state of a sampling circuit in an auto-zero period when the sampling circuit operates in a second mode according to an example embodiment of the present disclosure;

fig. 12B is a diagram illustrating a state of a sampling circuit in a comparison period when the sampling circuit operates in a second mode according to an example embodiment of the present disclosure;

fig. 13 is a circuit diagram illustrating a pixel included in an image sensor according to an example embodiment of the present disclosure;

fig. 14 is a sectional view showing a vertical structure of a 2PD pixel;

fig. 15A and 15B are diagrams of a method of operation of a sampling circuit according to an example embodiment of the present disclosure;

fig. 16 is a timing diagram illustrating an example of a sampling circuit operating in a first mode according to an example embodiment of the present disclosure;

fig. 17 is a timing diagram illustrating an example of a sampling circuit operating in a second mode according to an example embodiment of the present disclosure; and

fig. 18 is a block diagram illustrating an electronic device including an image sensor according to an example embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

Fig. 1 is a diagram illustrating an image forming apparatus 10 according to an example embodiment. The imaging apparatus 10 may include an image sensor 100 and an Image Signal Processor (ISP) 200. The image sensor 100 may sense light from the scene (such as light reflected from an object) to represent an image of the scene. Image sensor 100 may include a pixel array 110, a row driver 120, a readout circuit 130, a column driver 140, and a timing controller 150.

The pixel array 110 may include a plurality of pixels PX arranged in an array along a plurality of row lines and a plurality of column lines. (the following discussion regarding the pixels PX applies to any one of the plurality of pixels PX.) the pixels PX may include a photoelectric conversion element configured to generate electric charges in response to incident light, such as a photodiode, a phototransistor, a pinned (pinned) photodiode, or the like. The pixel PX may include at least two photoelectric conversion elements. The pixel PX may include two or more photoelectric conversion elements to generate pixel signals corresponding to various colors of light or to provide an auto-focusing function.

The pixels PX may sense light in a specific spectral range using a photoelectric conversion element. For example, the plurality of pixels PX may include a red pixel for sensing light in a red spectral range, a green pixel for sensing light in a green spectral range, and a blue pixel for sensing light in a blue spectral range. In other embodiments, additional or alternative color pixels, such as white, are included. A color filter for transmitting light in a specific spectral range may be disposed on any pixel PX. The illuminance measurement method and circuit of the present disclosure can be applied to pixels of different colors individually.

Depending on the intensity of light incident on the photoelectric conversion element, the pixel PX may be in a high illuminance state corresponding to a sensed illuminance in a high illuminance range, for example, higher than a threshold value, or in a low illuminance state corresponding to a sensed illuminance in a low illuminance range, for example, lower than a threshold value. Embodiments herein may make a luminance measurement for each pixel PX, under the assumption that the pixel PX may be in either state at any given time. Hereinafter, the term "high luminance pixel" may be used to refer to the pixel PX considered or determined to be in a high luminance state, and "low luminance pixel" may be used to refer to the pixel PX considered or determined to be in a low luminance state. In an embodiment, current measurement for two states is performed for each pixel PX in each frame, and each pixel PX is determined to be in a low-illuminance or high-illuminance state based on the result of the current measurement. Then, the analog value associated with one range or another may be used to more accurately perform overall a/D conversion with respect to all the pixels PX. With this capability, the image sensor 100 can be understood as a High Dynamic Range (HDR) image sensor.

In another embodiment, the high-luminance pixels and the low-luminance pixels may be distinguished from each other based on the pixel values of the previous frame. For example, among the plurality of pixels PX, a pixel in the previous frame, the pixel value of which is equal to or higher than a certain threshold value, may be defined as a high-luminance pixel, and a pixel in the previous frame, the pixel value of which is lower than the certain threshold value, may be defined as a low-luminance pixel. Information related to the illuminance value, the classification of the pixel, and the like may be stored in an internal memory or an external memory of the image sensor 100, and may be used to perform a sampling operation and the like.

The pixel PX may include a pixel circuit for generating a pixel signal. The pixel circuit may include a transfer transistor, a driving (source follower) transistor, a selection transistor, and a reset transistor. The pixel signal may be an analog signal, and may include a reset signal and an image signal. The reset signal may be a voltage signal corresponding to a specific power supply voltage, and the image signal may be a voltage signal corresponding to electric charges generated by the photoelectric conversion element.

The row driver 120 may drive the pixel array 110 by row line cells. For example, the pixel array 110 may generate a transfer control signal for controlling a transfer transistor of a pixel signal, a reset control signal for controlling a reset transistor, or a selection control signal for controlling a selection transistor. In an example embodiment, the row driver 120 may sequentially drive a plurality of row lines of the pixel array 110. The pixel array 110 may generate pixel signals in response to control signals generated by the row driver 120.

The readout circuit 130 may convert a pixel signal generated by the pixel array 110 into a digital signal, and may output the digital signal. The readout circuit 130 may include a sampling circuit and an analog-to-digital converter (ADC).

The sampling circuit may include a plurality of sampler circuits (hereinafter, "samplers"). In an example embodiment, the sampler may be a Correlated Double Sampler (CDS). The sampler may be selectively connected to the pixels PX included in the row selected by the row driver 120 through column lines, and may detect a reset signal and an image signal from the pixels PX of the selected row. The sampler may compare each of the reset signal and the image signal with a specific ramp signal, and may output a comparison signal as a result of the comparison. By performing this process row by row for the remaining rows of the pixel array, the image data for the entire image frame can be sampled.

The sampler may be initialized by performing an auto-zero operation prior to performing the comparison operation. In example embodiments, the multiple samplers may perform auto-zero operations on the high and low luminance pixels in different ways. For example, the sampler may perform an auto-zero operation for low-luminance pixels before performing the first comparison operation. Also, the sampler may perform an auto-zero operation for high luminance pixels before performing each comparison operation.

With respect to low-luminance pixels, since the amplification gain (interchangeably, just "gain") may be relatively high in the comparison operation of the sampler, it may be beneficial to significantly reduce the reset noise (or kT/C noise) generated during initialization. Thus, the sampler can perform a single auto-zero operation for all comparison operations for low luminance pixels. Regarding the high-illuminance pixel, since the gain may be relatively low in the comparison operation of the sampler, the effect of the reset noise generated during the initialization process of the sampler, which affects the comparison operation, may be relatively low, but it may be desirable to reduce the headroom voltage corresponding to the drive current of the sampler in terms of driving at low power. Thus, the sampler can perform another auto-zero operation (multiple auto-zero operations) for each comparison operation for high luminance pixels.

The analog-to-digital converter (ADC) may be configured as a single-slope analog-to-digital converter. The ADC may include a plurality of counters. In example embodiments, the plurality of counters may be up/down counters or bit-wise inversion counters. The plurality of counters may be respectively connected to the plurality of samplers, may count comparison signals output from the samplers, and may output digital signals. For example, the plurality of counters may convert the reset signal into the digital signal by counting a time period corresponding to a result of comparison between the reset signal and the ramp signal in the comparison signals, and may output the digital signal. In addition, the plurality of counters may convert the image signal into a digital signal by counting a period corresponding to a result of comparison between the image signal and the ramp signal in the comparison signal, and may output the digital signal.

The column driver 140 may include a latch or a buffer that may temporarily store the digital signal. The column driver 140 may process the digital signal received from the readout circuit 130 and may output image data. For example, the column driver 140 may generate image data based on a difference between a count value generated from the reset signal and a count value generated from the image signal, and may output the generated image data to the image signal processor 200.

The timing controller 150 may control the operation or timing of the row driver 120, the readout circuitry 130, and the column driver 140.

The image signal processor 200 may generate an image by processing the image data output from the column driver 140. For example, the image signal processor 200 may generate an image by performing signal processing operations such as color interpolation, color correction, gamma correction, color space conversion, edge correction, and the like.

Since the imaging device 10 in the exemplary embodiment includes the image sensor 100 having the sampler configured to perform the single auto-zero operation on the low-illuminance pixels and the multiple auto-zero operation on the high-illuminance pixels, the quality of the image can be improved and the power consumption can be reduced.

Fig. 2 is a diagram illustrating an image sensor according to an example embodiment.

Referring to fig. 2, the image sensor 300 may include a pixel array 310, a row driver 320, and a readout circuit 330.

The pixel array 310 may include a plurality of pixels PX11 to PXMN disposed at intersections of a plurality of row lines RL and a plurality of column lines CL.

The row driver 320 may input signals required to control the plurality of pixels PX11 to PXMN through the plurality of row lines RL. For example, the row driver 320 may provide a reset control signal RG, a transmission control signal TG, or a selection control signal SEL to the plurality of pixels PX11 to PXMN through the plurality of row lines RL. The row driver 320 may sequentially select each of a plurality of row lines RL. The row driver 320 may select one of a plurality of row lines RL during a specific horizontal period.

The readout circuit 330 may include a ramp signal generator 331, a sampling circuit 332, and an analog-to-digital converter 333. The DATA output by the analog-to-digital converter 333 may be input to the column driver.

The ramp signal generator 331 may generate the ramp signal RMP in response to the ramp control signal. The ramp signal RMP may include an up-ramp signal having a voltage that increases with time and a down-ramp signal having a voltage that decreases with time. In an example embodiment, the ramp signal generator 331 may generate a down ramp signal to perform a sampling operation on the low-luminance pixels. Also, the ramp signal generator 331 may generate an up-ramp signal to perform a sampling operation on the high-luminance pixels. A specific example of the ramp signal generator 331 is shown in fig. 3.

Referring to fig. 3, the ramp signal generator 331 may include a variable current source Iramp and a resistor Rramp connected in series between a first power supply voltage VDD node and a second power supply voltage VSS node. When a ramp current generated by the variable current source Iramp flows in the resistor Rramp, a ramp voltage Vramp may be generated. The ramp signal generator 331 may generate the up-ramp signal Vup _ ramp or the down-ramp signal Vdn _ ramp by adjusting the magnitude of the ramp current (magnitude) in response to the ramp control signal CSramp. Fig. 3 shows an example in which the ramp signal generator 331 includes a variable current source Iramp and a resistor Rramp, but example embodiments thereof are not limited thereto. The ramp signal generator 331 may include a constant current source and a variable resistor. In addition, unlike the example shown in fig. 3, the waveform of the up-ramp signal Vup _ ramp or the down-ramp signal Vdn _ ramp may be changed.

Referring back to fig. 2, the sampling circuit 332 may obtain a reset signal and an image signal from the plurality of pixels PX11 to PXMN. The sampling circuit 332 may include a plurality of samplers SA, and the plurality of samplers SA may be correlated double samplers CDS. Each of the plurality of samplers SA may receive the ramp signal RMP from the ramp signal generator 331 through the first node, and may receive the reset signal and the image signal from the plurality of pixels PX11 to PXMN through the second node. Each of the plurality of samplers SA may compare each of the reset signal and the image signal with the ramp signal RMP, and may output a comparison signal as a result of the comparison.

The analog-to-digital converter 333 may output the image DATA by converting the comparison signal output from the sampling circuit 332 into a digital signal.

Fig. 4 is a diagram illustrating a layout of an image sensor according to an example embodiment.

Referring to fig. 4, the image sensor 400 may be a stack-type image sensor 400 including a first substrate SUB1 and a second substrate SUB2 stacked in a vertical direction. The first substrate SUB1 may include a sensing region SR and a first pad (pad) region PA1, and the second substrate SUB2 may include a circuit region CA and a second pad region PA 2.

The sensing region SR may include a plurality of pixels PX arranged along a plurality of row lines and a plurality of column lines. The plurality of first PADs PAD1 may be included in the first PAD region PA1, and the plurality of first PADs PAD1 may be configured to transmit and receive electrical signals to and from the circuit region CA and the second PAD region PA2 of the second substrate SUB 2.

The circuit area CA may include the logic circuit block LC, and may include a plurality of circuit devices included in a row driver, a readout circuit, a column driver, and the like. The circuit region CA may provide a plurality of control signals to the sensing region SR, and may control outputs from the plurality of pixels PX. The plurality of first PAD PADs 1 disposed in the first PAD area PA1 may be electrically connected to the second PAD PADs 2 disposed in the second PAD area PA2 through connection portions CV.

The layout of the image sensor 400 is not limited to the example shown in fig. 4 and may be changed in an example embodiment. For example, the image sensor 400 may further include at least one substrate disposed below the second substrate SUB2 and including memory chips such as DRAM, SRAM, and the like.

Fig. 5 is a circuit diagram illustrating an example pixel PX included in an image sensor according to an example embodiment. An example pixel PX may include a photodiode PD and a pixel circuit. The pixel circuit may include a floating diffusion region FD, a reset transistor RX, a driving transistor DX, a selection transistor SX, and a transfer transistor TX.

The photodiode PD may generate electric charges in response to incident light. The charges generated by the photodiode PD may be accumulated in the floating diffusion region FD.

When the reset transistor RX is turned on by the reset control signal RG, the voltage of the floating diffusion region FD may be reset to the power supply voltage VDD. When the voltage of the floating diffusion region FD is reset, the selection transistor SX may be turned on by a selection control signal SEL, and a reset signal may be output to the column line COL through the pixel node PN.

When the transfer transistor TX is turned on by the transfer control signal TG after the reset voltage is output to the column line COL, the charge generated by the photodiode PD may move to the floating diffusion region FD.

The driving transistor DX may operate as a source follower amplifier to amplify the voltage of the floating diffusion region FD. When the selection transistor SX is turned on by a selection control signal SEL, an image signal corresponding to the electric charge generated by the photodiode PD may be output to the column line COL through the pixel node PN. Each of the reset signal and the image signal may be detected by a sampling circuit connected to the column line COL.

Fig. 6 is a circuit diagram illustrating a sampling circuit included in an image sensor according to an example embodiment.

Referring to fig. 6, the sampling circuit 500 may include a comparator 510, a first peripheral circuit 530, and a second peripheral circuit 550. The first peripheral circuit 530 may include first and second auto-zero switches AZ1 and AZ2 and first and second capacitors C1 and C2. The second peripheral circuit 550 may include first to fourth switches SW1 to SW 4.

The first switch SW1 may be connected between the input terminal of the ramp signal RMP and the first node N1. The second switch SW2 may be connected to the input terminal of the pixel signal PIX and the first node N1. The third switch SW3 and the fourth switch SW4 may be connected in parallel between the input terminal of the pixel signal PIX and the second node N2. The first switch SW1 and the third switch SW3 may be switched in response to the first control signal S1. The second switch SW2 and the fourth switch SW4 may be switched in response to the second control signal S2.

The sampling circuit 500 may receive the ramp signal RMP and the pixel signal PIX according to the switching operations of the first to fourth switches SW1 to SW4, and may perform a sampling operation and may output a result of comparison between the ramp signal RMP and the pixel signal PIX. In an example embodiment, the sampling circuit 500 may perform a correlated double sampling operation and may output a result of comparison between the ramp signal RMP and the pixel signal PIX.

The ramp signal RMP may include a down-ramp signal having a voltage that decreases with time and an up-ramp signal having a voltage that increases with time. In an example embodiment, the down-ramp signal may be input to the comparator 510 to perform a sampling operation on the low illumination pixels. Also, the up-ramp signal may be input to the comparator 510 to perform a sampling operation on the high-illuminance pixel.

The pixel signal PIX may be an analog signal output through a column line of the pixel array, and may include a reset signal corresponding to a specific power supply voltage and an image signal corresponding to charges generated by the photoelectric conversion element.

Various combinations of signals may be input to the comparator 410 depending on the switching states of the first to fourth switches SW1 to SW 4. In an example embodiment, the ramp signal RMP and the pixel signal PIX may be input to the comparator 510 to perform a sampling operation on the low-illuminance pixel. In addition, in order to perform a sampling operation on the high-illuminance pixel, only the pixel signal PIX may be input to the comparator 510 within the auto-zero period, and the ramp signal RMP and the pixel signal PIX may be input to the comparator 510 within a comparison period (hereinafter, only "period" or "interval").

The first capacitor C1 may be connected between the first node N1 and the first input node IN1 of the comparator 510, and the second capacitor C2 may be connected between the second node N2 and the second input node IN2 of the comparator 510. The ramp signal RMP or the pixel signal PIX may be input to the first input node IN1 of the comparator 510 through the first capacitor C1. Also, the pixel signal PIX may be input to the second input node IN2 of the comparator 510 through the second capacitor C2.

The comparator 510 may compare the ramp signal RMP with the pixel signal PIX input through the first and second capacitors C1 and C2, and may output a comparison signal CMP through the second output node OUT2 as a result of the comparison. In an example embodiment, the comparator 410 may be a differential amplifier and may be implemented by an Operational Transconductance Amplifier (OTA), an operational amplifier, or the like.

The first auto-zero switch AZ1 may be connected between the first input node IN1 and the first output node OUT1 of the comparator 510. The second auto-zero switch AZ2 may be connected between the second input node IN2 and the second output node OUT2 of the comparator 510. The first and second auto-zero switches AZ1 and AZ2 may be switched in response to the auto-zero control signal AZS. The comparator 510 may be initialized when the first and second auto-zero switches AZ1 and AZ2 are turned on in the auto-zero period in which the comparator 510 operates.

The sampling circuit 500 may operate in a first mode for low-illumination pixels and may perform a single (single) initialization process. In calculating the difference between the count value obtained from the reset signal and the count value obtained from the image signal, the reset noise generated in the initialization process may be removed. The sampling circuit 500 may operate in the second mode with respect to the high-luminance pixels and may perform a plurality of initialization processes. Although it is not possible to remove the reset noise generated during the multiple initialization processes, since the gain (e.g., x1) applied to the high-illuminance pixel may be relatively low, its effect on the comparison result may be insignificant and negligible. An example of the comparator 510 and the first peripheral circuit 530 is shown in fig. 7.

Fig. 7 is a circuit diagram showing a comparator and a first peripheral circuit of the sampling circuit shown in fig. 6. Here, the comparator 610 may include first to fifth transistors M1 to M5.

The first transistor M1 may be connected between the first output node OUT1 and the common node CN, and the gate of the first transistor M1 may be connected to the first input node IN 1. The second transistor M2 may be connected between the second output node OUT2 and the common node CN, and the gate of the second transistor M2 may be connected to the second input node IN 2. The third transistor M3 may be connected between the first power supply voltage VDDA node and the first output node OUT 1. The fourth transistor M4 may be connected between the first power supply voltage VDDA node and the second output node OUT 2.

A gate of the third transistor M3 and a gate of the fourth transistor M4 may be connected to the first output node OUT 1. The third transistor M3 and the fourth transistor M4 may be included in a current mirror circuit.

In example embodiments, the first and second transistors M1 and M2 may be implemented as NMOS transistors, and the third and fourth transistors M3 and M4 may be implemented as PMOS transistors. Alternatively, the first transistor M1 and the second transistor M2 may be implemented as PMOS transistors, and the third transistor M3 and the fourth transistor M4 may be implemented as NMOS transistors.

The fifth transistor M5 may be connected between the common node CN and the second power voltage VSSA node. The second power voltage VSSA may be a voltage having a voltage level lower than that of the first power voltage VDDA, for example, a ground voltage.

The fifth transistor M5 may operate as a current source of the comparator 510. For example, the fifth transistor M5 may receive a certain bias voltage VBIAS through a gate, and may generate a driving current Idrive corresponding to a sum of first and second currents respectively flowing through the first and second transistors M1 and M2.

The first peripheral circuit 630 may include first and second auto-zero switches AZl and AZ2 and first and second capacitors C1 and C2.

The first auto-zero switch AZ1 may be connected between the first output node OUT1 and the first input node IN 1. The second auto-zero switch AZ2 may be connected between the second output node OUT2 and the second input node IN 2. The first and second auto-zero switches AZl and AZ2 may be implemented as transistors that turn on in response to an auto-zero control signal AZs input through each gate. For example, the first auto-zero switch AZl and the second auto-zero switch AZ2 may be implemented as PMOS transistors.

The first capacitor C1 may be connected between the first node N1, to which the ramp signal RMP or the pixel signal PIX is selectively input, and the first input node IN 1. The second capacitor C2 may be connected between the second node N2 to which the pixel signal PIX is input and the second input node IN 2.

As a result of comparing the ramp signal RMP with the pixel signal PIX, the comparison signal CMP may be output through the second output node OUT 2.

When the second power supply voltage VSSA is the ground voltage, the first power supply voltage VDDA may have a voltage level equal to or higher than the sum of the first to third voltages V1 to V3 and the swing (swing width) Vsig of the pixel signal PIX to drive the comparator 610. The first voltage V1 may be a source-gate voltage (Vsg, M3, and M4) of each of the third transistor M3 and the fourth transistor M4 to allow current to flow in the fifth transistor M5. The second voltage V2 may be a source-gate voltage (Vsg, M1, and M2) of each of the first transistor M1 and the second transistor M2 to allow current to flow in the fifth transistor M5. The third voltage V3 may be a drain-source voltage (Vds, M5) of the fifth transistor M5 to maintain the fifth transistor M5 in a saturation state. For example, when the first voltage V1 is 0.8V, the second voltage V2 is 0.5V, the third voltage V3 is 0.3V, and the swing Vsig of the pixel signal PIX is 1V, the first power supply voltage VDDA may have a voltage level equal to or higher than 2.6V to drive the comparator 510.

IN the auto-zero period IN which the first and second auto-zero switches AZ1 and AZ2 are turned on, the voltage levels of the first input node IN1, the second input node IN2, the first output node OUT1, and the second output node OUT2 may be initialized to a specific value. For example, IN an example where the first power supply voltage VDDA has a voltage level of 2.6V or higher, the voltage level of the first input node IN1 may be initialized to VDDA-0.8V through an auto-zero operation. Since the auto-zero control signal AZS has the same voltage level as the first power supply voltage VDDA, a charge overflow phenomenon in which charges accumulated in the first capacitor C1 move to the first output node OUT1 may occur when the ramp signal RMP increases by 1V, which is the same as the swing Vsig of the pixel signal PIX. This may hinder the implementation of High Frame Rate (HFR) video capture, since the charge overflow phenomenon may increase random noise and pixel settling time. In order to solve the above-described problem, the image sensor in the example embodiment may perform an auto-zero operation for each of the reset signal and the image signal in the sampling operation for the high illuminance pixel, so that the charge overflow phenomenon may be prevented and a headroom voltage corresponding to the driving current flowing in the fifth transistor M5 may be reduced, thereby reducing power consumption.

IN the auto-zero period IN which the first and second auto-zero switches AZ1 and AZ2 are turned on, the voltage levels of the first input node IN1, the second input node IN2, the first output node OUT1, and the second output node OUT2 may be the same. IN this case, the voltages of the first input node IN1, the second input node IN2, the first output node OUT1, and the second output node OUT2 may be referred to as auto-zero voltages. In addition, in the auto-zero period, the voltage of the common node CN may be referred to as a saturation voltage and may vary depending on the characteristics of the fifth transistor M5. The input range of comparator 610 may be determined from the auto-zero voltage and the saturation voltage.

Fig. 8 is a diagram illustrating an operation method of a sampling circuit according to an example embodiment.

Referring to fig. 8 and 6, the sampling circuit 500 may sequentially perform a sampling operation on the reset signal and the image signal. For example, the sampling circuit 500 may perform a first sampling operation on the reset signal and may perform a second sampling operation on the image signal.

In an example embodiment, the sampling circuit 500 may perform sampling operations with different gains for high and low luminance pixels. The sampling circuit 500 may perform a first sampling operation at a first gain for a low-gain pixel in a first mode. The sampling circuit 500 may perform a second sampling operation at a second gain lower than the first gain for the high illuminance pixel in the second mode. In other words, the first mode may be a mode for measuring the illuminance of the pixel PX in a first range corresponding to a low illuminance state of the pixel PX, and the second mode may be a mode for measuring the illuminance of the pixel PX in a second range corresponding to a high illuminance state of the pixel PX.

The sampling circuit 500 may control the auto-zero operation AZ differently depending on the operation mode. In an example embodiment, the sampling circuit 500 may perform the auto-zero operation AZ only once before performing the first sampling operation in the first mode. Further, in the second mode, the sampling circuit 500 may perform the auto-zero operation AZ twice by performing the auto-zero operation AZ before performing the first sampling operation and before performing the second sampling operation. Since the auto-zero operation AZ may be performed once in the first mode, the auto-zero operation AZ may be referred to as a single auto-zero operation. In addition, since the auto-zero operation AZ is performed twice in the second mode, the auto-zero operation AZ may be referred to as a double auto-zero operation.

The sampling circuit 500 may ensure the accuracy of the result of the comparison between the ramp signal and the pixel signal by performing a single auto-zero operation in the first mode in which the sampling circuit 500 operates at a relatively high first gain. Further, the sampling circuit 500 may reduce power consumption by performing a dual auto-zero operation to reduce a headroom voltage corresponding to the driving current in a second mode in which the sampling circuit 500 operates at a second gain smaller than the first gain.

Fig. 9 is a timing chart showing an example in which the sampling circuit operates in the first mode.

Referring to fig. 9 and 6, when the first control signal S1 is activated and the second control signal S2 is deactivated, the first switch SW1 and the third switch SW3 may be turned on, and the second switch SW2 and the fourth switch SW4 may be turned off. In an example embodiment, the first and second control signals S1 and S2 may be activated when having a high logic value H and may be deactivated when having a low logic value L. When the first switch SW1 and the third switch SW3 are turned on, the ramp signal RMP may be input to the first input node IN1 of the comparator 510 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2.

When the auto-zero control signal AZS is activated in the first period Tl, the sampling circuit 500 may perform an auto-zero operation. In an example embodiment, the auto-zero control signal AZS may be activated when having a high logic value H and may be deactivated when having a low logic value L. The sampling circuit 500 may be initialized by performing an auto-zero operation.

The voltage VIN1 of the first input node IN1 of the comparator 510 may be the same as the voltage of the ramp signal RMP. IN addition, the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX. The pixel signal PIX input to the comparator 510 in the first period T1 may be a reset signal and may have the same voltage level as the initial voltage of the ramp signal RMP.

In the second period T2, an offset may be added to the ramp signal RMP. Thereafter, the ramp signal RMP may be decreased to have a certain slope. By counting the third period T3 from the point of time when the ramp signal RMP decreases to the point of time when the ramp signal RMP is lower than the pixel signal PIX using a specific clock signal, analog-to-digital conversion for the reset signal can be performed.

In the fourth period T4, the ramp signal RMP may have the same voltage level as that of the voltage in the second period T2. The image signal may be input to the comparator 410 as the pixel signal PIX, and may have a voltage level lower than the initial voltage of the ramp signal RMP. A voltage difference between the initial voltages of the image signal and the ramp signal RMP may correspond to an amount of charge generated by the photodiode.

Thereafter, the ramp signal RMP may be decreased to have a certain slope. By counting the fifth period T5 from the point of time when the ramp signal RMP decreases to the point of time when the ramp signal RMP is lower than the pixel signal PIX using a certain clock signal, analog-to-digital conversion for the image signal can be performed. Further, in the sixth period T6, the ramp signal RMP may be initialized for a subsequent sampling operation.

The image sensor in the example embodiment may generate the image data by calculating a difference between a count value of the fifth period T5 corresponding to a digital value of the image signal and a count value of the second period T2 corresponding to a digital value of the reset signal.

Meanwhile, the first period T1 may be referred to as an auto-zero period, and the second to sixth periods T2 to T6 may be referred to as comparison periods. In the following description, the connection relationship in the sampling circuit 500 in the auto-zero period and the comparison period in the first mode will be described.

Fig. 10A is a diagram illustrating a state of a sampling circuit in an auto-zero period when the sampling circuit operates in a first mode according to an example embodiment. Fig. 10B is a diagram illustrating a state of the sampling circuit in the comparison period when the sampling circuit operates in the first mode according to an example embodiment. The configuration and function of the sampling circuit 700A in fig. 10A and the sampling circuit 700B in fig. 10B may be the same as those of the sampling circuit 500 in fig. 6, and thus a repetitive description will not be provided.

Referring to fig. 10A, when the first switch SW1 and the third switch SW3 are turned on IN the auto-zero period IN the first mode, the ramp signal RMP may be input to the first input node IN1 of the comparator 710 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2. Also, the comparator 710 may be initialized when the first and second auto-zero switches AZ1 and AZ2 are turned on.

Referring to fig. 10B, when the first switch SW1 and the third switch SW3 are turned on IN the comparison period IN the first mode, the ramp signal RMP may be input to the first input node IN1 of the comparator 710 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2. In addition, when the first and second auto-zero switches AZ1 and AZ2 are turned off, the comparator 710 may output a comparison signal CMP obtained by comparing the ramp signal RMP and the pixel signal PIX through the second output node OUT 2.

Fig. 11 is a timing chart showing an example in which the sampling circuit operates in the second mode.

Referring to fig. 11 and 6, when the auto-zero control signal AZS is activated in the first period T1, the sampling circuit 500 may perform a first auto-zero operation. The sampling circuit 500 may be initialized by a first auto-zero operation.

In addition, when the first control signal S1 is deactivated and the second control signal S2 is activated, the first switch SW1 and the third switch SW3 may be turned off, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second and fourth switches SW2 and SW4 are turned on, the pixel signal PIX may be input to the first and second input nodes IN1 and IN2 of the comparator 510 through the first and second capacitors C1 and C2. Accordingly, the voltage VIN1 of the first input node IN1 and the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX. The pixel signal PIX input to the comparator 510 in the first period T1 may be a reset signal and may have a voltage level higher than the ramp signal RMP. The voltage difference between the pixel signal PIX and the ramp signal RMP may be considered as an offset of the ramp signal RMP.

In the second period T2, when the first control signal S1 is activated and the second control signal S2 is deactivated, the first switch SW1 and the third switch SW3 may be turned on, and the second switch SW2 and the fourth switch SW4 may be turned off. When the first switch SW1 and the third switch SW3 are turned on, the ramp signal RMP may be input to the first input node IN1 of the comparator 710 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2. Accordingly, the voltage VIN1 of the first input node IN1 of the comparator 510 may become the same as the voltage of the ramp signal RMP, and the voltage VIN2 of the second input node IN2 may become the same as the voltage of the pixel signal PIX.

Thereafter, the ramp signal RMP may be increased to have a specific slope. By counting the third period T3 from the point of time when the ramp signal RMP increases to the point of time when the ramp signal RMP is greater than the pixel signal PIX using a specific clock signal, analog-to-digital conversion for the reset signal can be performed.

When the auto-zero control signal AZS is activated in the fourth period T4, the sampling circuit 400 may perform a second auto-zero operation. The sampling circuit 500 may be reinitialized by a second auto-zero operation. Also, when the first control signal S1 is deactivated and the second control signal S2 is activated, the first switch SW1 and the third switch SW3 may be turned off, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second and fourth switches SW2 and SW4 are turned on, the pixel signal PIX may be input to the first and second input nodes IN1 and IN2 of the comparator 510 through the first and second capacitors C1 and C2. In the fourth period T4, the ramp signal RMP may have a voltage level lower than the initial voltage. The image signal may be input to the comparator 510 as the pixel signal PIX, and a decrease in voltage of the pixel signal PIX caused by the input of the image signal may be regarded as an offset of the ramp signal RMP.

Thereafter, the ramp signal RMP may increase again to have a certain slope. By counting the fifth period T5 from the point of time when the ramp signal RMP increases to the point of time when the ramp signal RMP is greater than the pixel signal PIX using a certain clock signal, analog-to-digital conversion for the image signal can be performed. In addition, in the sixth period T6, the ramp signal RMP may be initialized for a subsequent sampling operation.

The image sensor in the example embodiment may generate the image data by calculating a difference between a count value of the fifth period T5 corresponding to a digital value of the image signal and a count value of the third period T3 corresponding to a digital value of the reset signal. When the sampling circuit 500 performs the sampling operation using the up-ramp signal, in an example embodiment, the image data may be generated by subtracting a difference between a count value corresponding to the image signal and a count value corresponding to the reset signal from 2n (n is a resolution of the analog-to-digital converter).

The first and fourth periods Tl and T4 may be referred to as auto-zero periods, and the second, third, fifth, and sixth periods T2, T3, T5, and T6 may be referred to as comparison periods. In the following description, the connection relationship in the sampling circuit 500 in the auto-zero period and the comparison period in the second mode will be described.

Fig. 12A is a diagram showing a state of the sampling circuit in the auto-zero period when the sampling circuit operates in the second mode according to an example embodiment, and fig. 12B is a diagram showing a state of the sampling circuit in the comparison period when the sampling circuit operates in the second mode according to an example embodiment. The configuration and function of the sampling circuit 800a in fig. 12A and the sampling circuit 800B in fig. 12B may be the same as those of the sampling circuit 500 of fig. 6, and thus a repetitive description will not be provided.

Referring to fig. 12A, when the first control signal S1 is deactivated and the second control signal S2 is activated in the auto-zero period in the second mode, the first switch SW1 and the third switch SW3 may be turned off, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second and fourth switches SW2 and SW4 are turned on, the pixel signal PIX may be input to the first and second input nodes IN1 and IN2 of the comparator 810 through the first and second capacitors C1 and C2. Also, the comparator 810 may be initialized when the first and second auto-zero switches AZ1 and AZ2 are turned on.

Referring to fig. 12B, when the first switch SW1 and the third switch SW3 are turned on IN the comparison period IN the second mode, the ramp signal RMP may be input to the first input node IN1 of the comparator 810 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2. Also, when the first and second auto-zero switches AZ1 and AZ2 are turned off, the comparator 810 may output a comparison signal CMP obtained by comparing between the ramp signal RMP and the pixel signal PIX.

The image sensor described in the foregoing example embodiments can remove reset noise and can ensure the accuracy of the comparison operation by performing a single auto-zero operation in the sampling operation (first mode) for the low-illuminance pixel. The image sensor can also reduce power consumption by performing a dual auto-zero operation to reduce a headroom voltage corresponding to a driving current in a sampling operation (second mode) for a high-illuminance pixel. In the following description, an example embodiment in which each pixel in the image sensor includes two photodiodes will be described in more detail.

Fig. 13 is a circuit diagram illustrating a pixel included in an image sensor according to an example embodiment. Here, the pixel PX' in the image sensor 100 may include two photodiodes PD1 and PD2 and a pixel circuit (other components shown in fig. 13). The pixel circuit may process charges generated by the two photodiodes PD1 and PD2, and may output an electrical signal at a node PN. The pixel circuit may include two transfer transistors TX1 and TX2, a reset transistor RX, a driving transistor DX, and a selection transistor SX. The first transfer transistor TX1 may be connected to the first photodiode PD1, and the second transfer transistor TX2 may be connected to the second photodiode PD 2. In the following description, a pixel PX' including two photodiodes PD1 and PD2 may be referred to as a 2PD pixel. In various embodiments, two photodiodes PD1 and PD2 may be used for autofocus during autofocus mode. During the imaging mode, photo-charges from both photodiodes PD1 and PD2 may be used to achieve HDR resolution or for other purposes using the methods disclosed herein.

The reset transistor RX may be turned on and off by a reset control signal RG, and when the reset transistor RX is turned on, the voltage of the floating diffusion region FD may be reset to the power supply voltage VDD. When the voltage of the floating diffusion region FD is reset, the selection transistor SX may be turned on by a selection control signal SEL, and a reset signal may be output to the column line COL.

When the first transfer transistor TX1 is turned on after the reset voltage is output to the column line COL, the charge generated by the first photodiode PD1 exposed to light may move to the floating diffusion region FD. The driving transistor DX may operate as a source follower amplifier for amplifying the voltage of the floating diffusion region FD, and when the selection transistor SX is turned on by a selection control signal SEL, a first image signal corresponding to the electric charge generated by the photodiode PD may be output to the column line COL.

When the second transfer transistor TX2 is turned on after the first image signal is output to the column line COL, the charges generated by the second photodiode PD2 exposed to light may move to the floating diffusion region FD. When the selection transistor SX is turned on by the selection control signal SEL, a second image signal corresponding to the electric charge generated by the photodiode PD may be output to the column line COL.

The reset signal and each of the first and second image signals may be detected by a sampling circuit connected to the column line COL. The sampling circuit may include a plurality of samplers, each of the samplers having a first input terminal for receiving the ramp signal and a second input terminal for receiving the reset signal and the first and second image signals.

The sampler may compare the reset signal and each of the first and second image signals with the ramp signal. An analog-to-digital converter (ADC) may be connected to an output terminal of the sampler. The analog-to-digital converter may output the first image data based on a count value corresponding to the first image signal and a count value corresponding to the reset signal. The analog-to-digital converter may further output the second image data based on a count value corresponding to the second image signal and a count value corresponding to the reset signal. Also, an Image Signal Processor (ISP) may generate an image using the first image data and the second image data.

Fig. 14 is a sectional view showing a vertical structure of a 2PD pixel.

Referring to fig. 14, each of the pixels PX1 and PX2 of the pixel array PXA may include two photodiodes PD1 and PD2 and PD1 'and PD 2'.

Each of the pixels PX1 and PX2 may include a color filter and a microlens disposed on the two photodiodes PD1 and PD2 and PD1 'and PD2', respectively.

Two photodiodes PD1 and PD2 and PD1 'and PD2' may be formed in a silicon substrate, and deep trench isolation DTI may be formed between the two photodiodes PD1 and PD2 and PD1 'and PD 2'. For example, an intra-pixel DTI may be formed between two photodiodes PD1 and PD2 and PD1 'and PD2', and an inter-pixel DTI may be formed between pixels PX1 and PX 2.

Metal wiring, multilayer wiring, or wiring layers may be formed in the circuit regions formed between the two photodiodes PD1 and PD2 and PD1 'and PD2' and the color filters. A lens buffer or planarization layer may be formed between the microlens and the color filter.

An image sensor including the 2PD pixel described with reference to fig. 13 and 14 may include a sampling circuit equivalent to the sampling circuit shown in fig. 6. In the following description, the sampling operation for the 2PD pixel will be described in detail.

Fig. 15A and 15B are diagrams illustrating a method of operating a sampling circuit according to an example embodiment.

Referring to fig. 15A and 6, the sampling circuit 500 may sequentially perform a sampling operation on a plurality of pixel signals of the 2PD pixels, such as a reset signal, a first image signal, and a second image signal. For example, the sampling circuit 500 may perform a first sampling operation on a first reset signal and may perform a second sampling operation on a second reset signal. Further, the sampling circuit 500 may perform a third sampling operation on the first image signal and may perform a fourth sampling operation on the second image signal. The comparison signals generated in response to the sampling operation of the sampling circuit 500 may be monitored using a counting method to determine the analog level of each sampled signal. The analog levels may be converted to digital signals and may be stored in latches or buffers. The column driver may generate image data by performing differential calculation using the count value as a digital signal stored in a latch or a buffer.

In an example embodiment, the sampling circuit 500 may perform sampling operations on low-luminance pixels and high-luminance pixels with different gains. In the first mode, the sampling circuit 500 may perform a first sampling operation on the low-illumination pixels with a first gain. The sampling circuit 500 may perform a second sampling operation on the high-illuminance pixel with a second gain smaller than the first gain.

The sampling circuit 500 may perform the auto-zero operation AZ differently depending on the operation mode. In an example embodiment, the sampling circuit 500 may perform the auto-zero operation AZ only once before performing the first sampling operation in the first mode. Since the auto-zero operation AZ is performed only once in the first mode, the auto-zero operation AZ may be referred to as a single auto-zero operation. In contrast to the above-described example, the sampling circuit 500 may perform the auto-zero operation AZ before performing the first to fourth sampling operations in the second mode. Since the auto-zero operation AZ may be performed four times in the second mode, the auto-zero operation AZ may be referred to as a multiple auto-zero operation.

Referring to fig. 15B, the sampling circuit 500 may sequentially perform a sampling operation on the reset signal, the first image signal, and the second image signal of the 2PD pixel. Also, the sampling circuit 500 may perform a sampling operation on the reset signal only once for each pixel luminance measurement. For example, the sampling circuit 500 may perform a first sampling operation on the reset signal, perform a second operation on the first image signal, and perform a third sampling operation on the second image signal.

The sampling circuit 500 may perform the auto-zero operation AZ differently depending on the operation mode. In an example embodiment, the sampling circuit 500 may perform the auto-zero operation AZ only once before performing the first sampling operation in the first mode. Unlike the above-described example, the sampling circuit 500 may perform the auto-zero operation AZ before performing the first to third sampling operations, so that the sampling circuit 500 may perform the auto-zero operation AZ three times.

Referring to fig. 15A and 15B, since the sampling circuit 500 performs the single auto-zero operation in the first mode in which the sampling circuit 500 has the relatively high first gain, the accuracy of the result of the comparison between the ramp signal and the pixel signal can be ensured. In addition, since the sampling circuit 500 performs the multi-auto-zero operation in the second mode in which the sampling circuit 500 has the second gain smaller than the first gain, the headroom voltage corresponding to the driving current may be reduced, so that power consumption may be reduced.

In the following description, the first mode and the second mode of the sampling circuit will be described in more detail based on the sampling method shown in fig. 15B according to an example embodiment.

Fig. 16 is a timing diagram illustrating an example of a sampling circuit operating in a first mode according to an example embodiment.

Referring to fig. 16 and 6, when the first control signal S1 is activated (e.g., activated to a high logic value) and the second control signal S2 is deactivated (e.g., deactivated to a low logic value), the first switch SW1 and the third switch SW3 may be turned on, and the second switch SW2 and the fourth switch SW4 may be turned off. When the first switch SW1 and the third switch SW3 are turned on, the ramp signal RMP may be input to the first input node IN1 of the comparator 510 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2.

When the auto-zero control signal AZS is activated (e.g., activated to a high logic value) in the first period Tl, the sampling circuit 500 may perform an auto-zero operation. The sampling circuit 500 may be initialized by an auto-zero operation.

The voltage VIN1 of the first input node IN1 of the comparator 510 may be the same as the voltage of the ramp signal RMP. IN addition, the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX. The pixel signal PIX input to the comparator 510 in the first period T1 may be a reset signal and may have a voltage level equal to an initial voltage of the ramp signal RMP.

In the fourth period T4, the ramp signal RMP may have a voltage level equal to the level of the voltage in the second period T2. The first image signal may be input to the comparator 510 as the pixel signal PIX. The first image signal may be an electric signal corresponding to electric charges generated by the first photodiode of the pixel, and may have a first voltage level lower than an initial voltage of the ramp signal RMP. The difference between the initial voltages between the first image signal and the ramp signal RMP may correspond to the amount of charge generated by the first photodiode.

Thereafter, the ramp signal RMP may be decreased to have a certain slope. By counting the fifth period T5 from the point in time when the ramp signal RMP decreases to the point in time when the ramp signal RMP is lower than the pixel signal PIX using a certain clock signal, analog-to-digital conversion for the first image signal can be performed.

In the sixth period T6, the ramp signal RMP may have a voltage level equal to that in the second period T2. The second image signal may be input to the comparator 510 as the pixel signal PIX. The second image signal may be an electrical signal corresponding to charges generated by a second photodiode of the pixel, and may have a second voltage level lower than an initial voltage of the ramp signal RMP. The difference between the initial voltages of the second image signal and the ramp signal RMP may correspond to the amount of charge generated by the second photodiode.

Thereafter, the ramp signal RMP may be decreased to have a certain slope. By counting the seventh period T7 from the point in time when the ramp signal RMP decreases to the point in time when the ramp signal RMP is lower than the pixel signal PIX using a certain clock signal, analog-to-digital conversion for the second image signal can be performed. Also, in the eighth period T8, the ramp signal RMP may be initialized for a subsequent sampling operation.

The image sensor in the example embodiment may generate the first image data by calculating a difference between a count value of the fifth period T5 corresponding to the digital value of the first image signal and a count value of the second period T2 corresponding to the digital value of the reset signal. Further, the image sensor in the example embodiment may generate the second image data by calculating a difference between the count value of the seventh period T7 corresponding to the digital value of the second image signal and the count value of the second period T2 corresponding to the digital value of the reset signal. Thereafter, the image signal processor ISP may generate an image using the first image data and the second image data.

Fig. 17 is a timing diagram illustrating an example of a sampling circuit operating in a second mode according to an example embodiment.

Referring to fig. 17 and 6, when the auto-zero control signal AZS is activated (e.g., activated to a high logic value) in the first period T1, the sampling circuit 500 may perform a first auto-zero operation. The sampling circuit 500 may be initialized by a first auto-zero operation.

In addition, when the first control signal S1 is deactivated (e.g., activated to a low logic value) and the second control signal S2 is activated (e.g., activated to a high logic value), the first switch SW1 and the third switch SW3 may be turned off, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second and fourth switches SW2 and SW4 are turned on, the pixel signal PIX may be input to the first and second input nodes IN1 and IN2 of the comparator 510 through the first and second capacitors C1 and C2. Accordingly, the voltage VIN1 of the first input node IN1 and the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX. The pixel signal PIX input to the comparator 510 in the first period T1 may be a reset signal and may have a voltage level higher than that of the ramp signal RMP. The voltage difference between the pixel signal PIX and the ramp signal RMP may be considered as an offset of the ramp signal RMP.

When the first control signal S1 is activated and the second control signal S2 is deactivated in the second period T2, the first switch SW1 and the third switch SW3 may be turned on, and the second switch SW2 and the fourth switch SW4 may be turned off. When the first switch SW1 and the third switch SW3 are turned on, the ramp signal RMP may be input to the first input node IN1 of the comparator 510 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2. Accordingly, the voltage VIN1 of the first input node IN1 of the comparator 510 may become the same as the voltage of the ramp signal RMP, and the voltage VIN2 of the second input node IN2 may become the same as the voltage of the pixel signal PIX.

When the auto-zero control signal AZS is activated again in the fourth period T4, the sampling circuit 500 may perform a second auto-zero operation. The sampling circuit 500 may be reinitialized by a second auto-zero operation. Also, when the first control signal S1 is deactivated and the second control signal S2 is activated, the first switch SW1 and the third switch SW3 may be turned off, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second and fourth switches SW2 and SW4 are turned on, the pixel signal PIX may be input to the first and second input nodes IN1 and IN2 of the comparator 510 through the first and second capacitors C1 and C2. Accordingly, the voltage VIN1 of the first input node IN1 and the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX.

In the fourth period T4, the ramp signal RMP may have a voltage level lower than its initial voltage. The first image signal may be input to the comparator 510 as the pixel signal PIX, and a decrease in voltage of the pixel signal PIX caused by the input of the first image signal may be regarded as an offset of the ramp signal RMP.

Thereafter, the ramp signal RMP may increase again to have a certain slope. The analog-to-digital conversion for the image signal may be performed by counting a fifth period T5 from the point of time when the ramp signal RMP increases to the point of time when the ramp signal RMP is greater than the pixel signal PIX using a specific clock signal.

When the auto-zero control signal AZS is activated in the sixth period T6, the sampling circuit 500 may perform a third auto-zero operation. The sampling circuit 500 may be reinitialized by a third auto-zero operation. Also, when the first control signal S1 is deactivated and the second control signal S2 is activated, the first switch SW1 and the third switch SW3 may be turned off, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second and fourth switches SW2 and SW4 are turned on, the pixel signal PIX may be input to the first and second input nodes IN1 and IN2 of the comparator 510 through the first and second capacitors C1 and C2. Accordingly, the voltage VIN1 of the first input node IN1 and the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX.

The pixel signal PIX input to the comparator 510 in the seventh period T7 may be the second image signal and may have a voltage level higher than that of the ramp signal RMP. The voltage difference between the pixel signal PIX and the ramp signal RMP may be considered as an offset of the ramp signal RMP.

Thereafter, the ramp signal RMP may increase again to have a certain slope. By counting the eighth period T8 from the point of time when the ramp signal RMP increases to the point of time when the ramp signal RMP is greater than the pixel signal PIX using a specific clock signal, analog-to-digital conversion for the image signal can be performed. In the ninth period T9, the ramp signal RMP may be initialized for a subsequent sampling operation.

The image sensor in the example embodiment may generate the first image data by calculating a difference between a count value of the fifth period T5 corresponding to the digital value of the first image signal and a count value of the third period T3 corresponding to the digital value of the reset signal. Further, the image sensor in the example embodiment may generate the second image data by calculating a difference between the count value of the eighth period T8 corresponding to the digital value of the second image signal and the count value of the third period T3 corresponding to the digital value of the reset signal.

When the sampling circuit 500 performs the sampling operation using the up-ramp signal, the first image data and the second image data may be generated by subtracting a difference between a count value corresponding to the first image signal and the second image signal and a count value corresponding to the reset signal from 2n (n is a resolution of the analog-to-digital converter).

Thereafter, the image signal processor ISP may generate an image using the first image data and the second image data.

Fig. 18 is a block diagram illustrating an electronic device including an image sensor according to an example embodiment.

Referring to fig. 18, the electronic device 1000 may include a memory 1010, an imaging device 1020, a processor 1030, a communication module 1040, and the like.

Among the elements shown in fig. 18, the electronic device 1000 may be provided with a communication module 1040 to communicate with a video card, a sound card, a memory card, a USB device, or the like. The electronic device 1000 may include general purpose desktop and laptop computers, and may also include smart phones, tablet PCs, smart wearable devices, and the like.

The memory 1010 may be implemented by a storage medium for storing data, multimedia data, etc., required for the operation of the electronic device 1000. The memory 1010 may include storage devices based on a non-volatile memory device configuration. Also, the memory 1010 may include at least one of a Solid State Drive (SSD), a Hard Disk Drive (HDD), and an Optical Disk Drive (ODD) as a storage device.

Processor 1030 may perform certain computations or may process commands and tasks. The processor 1030 may be implemented by a Central Processing Unit (CPU) or microprocessor unit (MCU), a system on a chip (SoC), etc., and may communicate with the memory 1010 and the image sensor 1020 through the bus 1050 and also with other devices connected to the electronic apparatus 1000 through the communication module 1040.

The imaging device 1020 included in the electronic device 1000 shown in fig. 18 may include the image sensor described in the foregoing example embodiment. As an example, the imaging device 1020 may operate according to the foregoing example embodiments described with reference to fig. 1 to 17.

According to the foregoing example embodiments, the image sensor may perform a single auto-zero operation in a high gain mode, so that reset noise may be removed and image quality may be improved.

Further, the image sensor can perform a multi-auto-zero operation in a sampling operation for a high-illuminance pixel, so that a headroom voltage corresponding to a driving current can be reduced, and thus power consumption can be reduced.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. An image forming apparatus comprising:

a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels is configured to generate a reset signal and an image signal;

a sampling circuit including a plurality of sampler circuits connected to a plurality of column lines, wherein each of the plurality of sampler circuits is configured to generate a first comparison signal by comparing a reset signal with a ramp signal, and to generate a second comparison signal by comparing an image signal with the ramp signal;

an analog-to-digital converter configured to convert each of the first and second comparison signals into a respective digital signal; and

a column driver configured to generate image data based on the first comparison signal and the second comparison signal converted into digital signals,

wherein each of the plurality of sampler circuits performs an auto-zero operation for initializing itself before performing a comparison for the reset signal in the first mode, and performs a corresponding auto-zero operation before performing a comparison for each of the reset signal and the image signal in the second mode.

2. The imaging apparatus according to claim 1, wherein the first mode is a mode for measuring the illuminance of the pixel in a first range corresponding to a low illuminance state of the pixel, and the second mode is a mode for measuring the illuminance of the pixel in a second range corresponding to a high illuminance state of the pixel.

3. The imaging device of claim 1, wherein an amplification gain of each of the plurality of sampler circuits is higher in the first mode than in the second mode.

4. The imaging apparatus of claim 1, further comprising:

a ramp signal generator configured to generate a ramp signal and output the ramp signal to the sampling circuit under the control of the timing controller;

wherein the ramp signal includes an up-ramp signal and a down-ramp signal.

5. The imaging device of claim 4, wherein each of the plurality of sampler circuits performs a comparison operation using a down-ramp signal in the first mode.

6. The imaging device of claim 4, wherein each of the plurality of sampler circuits performs a comparison operation using an up-ramp signal in the second mode.

7. The imaging apparatus according to claim 1, wherein the analog-to-digital converter generates a first count value by counting a first comparison signal, and generates a second count value by counting a second comparison signal.

8. The imaging apparatus according to claim 7, wherein the column driver generates the image data by a differential calculation of the first count value and the second count value.

9. The imaging device of claim 1, wherein each of the plurality of sampler circuits performs an auto-zero operation using a ramp signal and a reset signal in the first mode.

10. The imaging device of claim 1, wherein each of the plurality of sampler circuits performs an auto-zero operation using a reset signal and an image signal in the second mode.

11. An image sensor, comprising:

a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels is configured to generate a pixel signal;

a plurality of sampler circuits connected to the plurality of column lines and configured to output a comparison signal by comparing the pixel signal with the ramp signal; and

an analog-to-digital converter configured to generate image data by converting the comparison signal into a digital signal,

wherein each of the plurality of sampler circuits comprises:

a comparator;

a first auto-zero switch connected between a first input node and a first output node of the comparator;

a second auto-zero switch connected between the second input node and the second output node of the comparator;

a first capacitor connected between the first input node and the first node;

a second capacitor connected between the second input node and the second node;

a first switch connected between a first node and an input terminal of the ramp signal;

a second switch connected between the first node and an input terminal of the pixel signal; and

and a third switch and a fourth switch connected in parallel between the second node and the input terminal of the pixel signal.

12. The image sensor of claim 11, wherein the first switch and the third switch operate in response to a first control signal, and the second switch and the fourth switch operate in response to a second control signal.

13. The image sensor of claim 12, wherein the first switch and the third switch operate alternately with the second switch and the fourth switch.

14. The image sensor of claim 11, wherein the first auto-zero switch and the second auto-zero switch operate in response to an auto-zero control signal.

15. The image sensor of claim 11, wherein each of the plurality of sampler circuits outputs a comparison signal through a second output node.

16. An image sensor, comprising:

a plurality of pixels connected to a plurality of row lines and a plurality of column lines and configured to generate a reset signal, a first image signal, and a second image signal;

a plurality of sampler circuits connected to the plurality of column lines and configured to generate a comparison signal by sequentially comparing each of a reset signal, a first image signal, and a second image signal with an up-ramp signal or a down-ramp signal; and

wherein each of the plurality of sampler circuits operates at a first amplification gain and generates a comparison signal using a down-ramp signal in a first mode, and each of the plurality of sampler circuits operates at a second amplification gain that is less than the first amplification gain and generates a comparison signal using an up-ramp signal in a second mode.

17. The image sensor of claim 16, wherein, in the first mode, each of the plurality of sampler circuits performs an auto-zero operation to initialize the input voltage and the output voltage of each of the plurality of sampler circuits prior to performing the comparison operation on the reset signal.

18. The image sensor of claim 17, wherein each of the plurality of sampler circuits performs an auto-zero operation using an up-ramp signal or a down-ramp signal and a reset signal.

19. The image sensor of claim 16, wherein in the second mode, each of the plurality of sampler circuits performs an auto-zero operation to initialize the input voltage and the output voltage of each of the plurality of sampler circuits prior to performing each comparison operation on the reset signal, the first image signal, and the second image signal.

20. The image sensor of claim 19, wherein each of the plurality of sampler circuits performs an auto-zero operation using a reset signal, a first image signal, and a second image signal.