CN216647354U - Storage system - Google Patents
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- CN216647354U CN216647354U CN202122450336.6U CN202122450336U CN216647354U CN 216647354 U CN216647354 U CN 216647354U CN 202122450336 U CN202122450336 U CN 202122450336U CN 216647354 U CN216647354 U CN 216647354U
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Abstract
The present disclosure relates to a storage system comprising: the system comprises a mainboard module and a backboard module, wherein the backboard module comprises a logic control unit, and the logic control unit comprises an I2C interface; the logic control unit is in communication connection with the mainboard module through the I2C interface, acquires state information corresponding to each hard disk in the backboard module and indication information corresponding to each hard disk, and transmits the acquired state information corresponding to each hard disk in the backboard module and the indication information corresponding to each hard disk to the mainboard module through the I2C interface, so that the mainboard module can remotely monitor the state information corresponding to each hard disk in the backboard module and the indication information corresponding to each hard disk.
Description
Technical Field
The present disclosure relates to the field of server design technologies, and in particular, to a storage system.
Background
With the development of cloud computing and application of big data, informatization gradually covers various fields of society. The number of hard disks of the container-node server as information data is also increasing.
In the prior art, a hard disk backplane compatible with a Serial ATA (Serial ATA) hard disk and an NVMe (nonvolatile memory host controller interface specification) is used to implement communications between the NVMe and a motherboard and communications between the SATA hard disk and the motherboard.
The existing storage system can not realize the remote monitoring of the state of the hard disk in the hard disk backboard.
SUMMERY OF THE UTILITY MODEL
In order to solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a storage system, which implements a motherboard module to remotely monitor status information corresponding to each hard disk in a backplane module and indication information corresponding to each hard disk.
An embodiment of the present disclosure provides a storage system, including: the system comprises a mainboard module and a backplane module, wherein the backplane module comprises a logic control unit, and the logic control unit comprises an I2C interface;
the logic control unit is in communication connection with the mainboard module through the I2C interface, acquires state information corresponding to each hard disk in the backboard module and indication information corresponding to each hard disk, and transmits the acquired state information corresponding to each hard disk in the backboard module and the indication information corresponding to each hard disk to the mainboard module through the I2C interface.
Optionally, the motherboard module includes a management unit;
the logic control unit is in communication connection with the management unit of the mainboard module through the I2C interface.
Optionally, the motherboard module further includes a first processing unit and a second processing unit, and the logic control unit further includes a first logic interface and a second logic interface;
the first end of the first processing unit is in communication connection with the first end of the first logic interface, and the first end of the second processing unit is in communication connection with the first end of the second logic interface.
Optionally, the backplane module further includes a first storage unit and a second storage unit;
the first storage unit is in communication connection with the second end of the first processing unit, and the second storage unit is in communication connection with the second end of the second processing unit.
Optionally, the logic control unit further includes a control chip;
the first end of the control chip is in communication connection with the second end of the first logic interface, the second end of the control chip is in communication connection with the second end of the second logic interface, and the third end of the control chip is in communication connection with the I2C interface.
Optionally, the backplane module further includes a first indicating unit and a second indicating unit;
the first indicating unit is in communication connection with a fifth end of the control chip, and the second indicating unit is in communication connection with a sixth end of the control chip.
Optionally, the first indication unit and the second indication unit respectively include a first indication lamp, a second indication lamp and a third indication lamp;
the first indicator light is used for indicating that the storage unit is in a normal state, the second indicator light is used for indicating that the storage unit is in an abnormal state, and the third indicator light is used for indicating the position information of the storage unit.
Optionally, the first processing unit comprises an X86 processor and the second processing unit comprises a bridge piece.
Optionally, the first processing unit and the first logic interface communicate through a PCIe protocol, and the second processing unit and the second logic interface communicate through a SATA protocol.
Optionally, the first storage unit includes an NVMe hard disk, and the second storage unit includes a SATA hard disk.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
the storage system provided by the embodiment of the disclosure, a backplane module in the storage system includes a logic control unit, the logic control unit includes an I2C interface, the logic control unit is in communication connection with a motherboard module through an I2C interface, the logic control unit acquires state information corresponding to each hard disk in the backplane module and indication information corresponding to each hard disk, and transmits the acquired state information corresponding to each hard disk in the backplane module and indication information corresponding to each hard disk to the motherboard module through an I2C interface, thereby ensuring that the motherboard module can remotely monitor the state information corresponding to each hard disk in the backplane module and the indication information corresponding to each hard disk.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
FIG. 1 is a schematic structural diagram of a storage system according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of another storage system provided by the embodiments of the present disclosure;
FIG. 3 is a schematic structural diagram of another storage system provided by the embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another storage system provided in the embodiment of the present disclosure.
Wherein: 10. a motherboard module; 20. a backplane module; 100. a management unit; 101. a first processing unit; 102. a second processing unit; 200. a logic control unit; 201. an I2C interface; 202. a first logical interface; 203. a second logical interface; 204. a control chip; 210. a first storage unit; 220. a second storage unit; 230. a first indicating unit; 240. a second indicating unit; 231. a first indicator light; 232. a second indicator light; 233. and a third indicator light.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
Fig. 1 is a schematic structural diagram of a storage system provided in an embodiment of the present disclosure, as shown in fig. 1, the storage system includes a motherboard module 10 and a backplane module 20, the backplane module 20 includes a logic control unit 200, where the logic control unit 200 includes an I2C interface, the logic control unit 200 is in communication connection with the motherboard module 10 through an I2C interface 201, and the logic control unit 200 acquires state information corresponding to each hard disk in the backplane module 20 and indication information corresponding to each hard disk, and transmits the acquired state information corresponding to each hard disk in the backplane module 20 and the indication information corresponding to each hard disk to the motherboard module 10 through the I2C interface 201.
As shown in fig. 1, in the storage system provided in the embodiment of the present disclosure, the logic control unit 200 in the backplane module 20 includes an I2C interface 201, the logic control unit 200 in the backplane module 20 outputs the state information corresponding to each hard disk in the backplane module 20 and the indication information corresponding to each hard disk through the I2C interface 201, and the motherboard module 10 receives the state information corresponding to each hard disk in the backplane module 20 and the indication information corresponding to each hard disk, so as to ensure that the motherboard module 10 can remotely monitor the state information corresponding to each hard disk in the backplane module 20 and the indication information corresponding to each hard disk.
Specifically, the I2C interface 201 mainly sends status information corresponding to each hard disk in the backplane module 20 and indication information corresponding to each hard disk, which are acquired by the logic control unit 200.
The storage system provided by the embodiment of the disclosure, a backplane module in the storage system includes a logic control unit, the logic control unit includes an I2C interface, the logic control unit is in communication connection with a motherboard module through an I2C interface, the logic control unit acquires state information corresponding to each hard disk in the backplane module and indication information corresponding to each hard disk, and transmits the acquired state information corresponding to each hard disk in the backplane module and indication information corresponding to each hard disk to the motherboard module through an I2C interface, thereby ensuring that the motherboard module can remotely monitor the state information corresponding to each hard disk in the backplane module and the indication information corresponding to each hard disk.
Fig. 2 is a schematic structural diagram of another storage system provided by an embodiment of the present disclosure, and based on the foregoing embodiment, as shown in fig. 2, a main board module of the storage system includes a management unit, and a logic control unit is communicatively connected to the management unit of the main board module through an I2C interface.
As shown in fig. 2, the motherboard module 10 includes a management unit 100, the logic control unit 200 is in communication connection with the management unit 100 of the motherboard module 10 through an I2C interface, the management unit 100 acquires, through an I2C interface 201, status information corresponding to each hard disk and indication information corresponding to each hard disk acquired by the logic control unit 200 of the backplane module 20, and the management unit 100 monitors the status information corresponding to each hard disk and the indication information corresponding to each hard disk in the backplane module 20 according to the acquired status information corresponding to each hard disk and the indication information corresponding to each hard disk.
Fig. 3 is a schematic structural diagram of another storage system provided by an embodiment of the present disclosure, and in the embodiment of the present disclosure, as shown in fig. 3, the motherboard module 10 further includes a first processing unit 101 and a second processing unit 102, and the logic control unit 200 further includes a first logic interface 202 and a second logic interface 203, a first end of the first processing unit 101 is communicatively connected to a first end of the first logic interface 202, and a first end of the second processing unit 102 is communicatively connected to a first end of the second logic interface 203.
The backplane module 20 further comprises a first storage unit 210 and a second storage unit 220, wherein the first storage unit 210 is communicatively connected to the second end of the first processing unit 101, and the second storage unit 220 is communicatively connected to the second end of the second processing unit 102.
As shown in fig. 3, by setting the first end of the first processing unit 101 to be in communication connection with the first logic interface 202, the first end of the second processing unit 102 to be in communication connection with the second logic interface 203, the first storage unit 210 to be in communication connection with the second end of the first processing unit 101, and the second storage unit 220 to be in communication connection with the second end of the second processing unit 102, the first processing unit 101 obtains the status information of the first storage unit 210 in the backplane module 20, and the second processing unit 102 obtains the status information of the second storage unit 220 in the backplane module 20. The first processing unit 101 controls the first processing unit 101 to be in communication connection with the first logical interface 202 according to the acquired state information of the first storage unit 210 in the backplane module 20, or the second processing unit 102 controls the second processing unit 102 to be in communication connection with the second logical interface 203 according to the acquired state information of the second storage unit 220 in the backplane module 20.
For example, when the state information of the first storage unit 210 in the backplane module 20, acquired by the first processing unit 101 in the motherboard module 10, is the access of the first storage unit 210, the first processing unit 101 in the motherboard module 10 is in communication connection with the first logic interface 202 of the logic control unit 200, so that the first processing unit 101 in the motherboard module 10 outputs the indication information corresponding to the first storage unit 210 to the logic control unit 200. When the state information of the second storage unit 220 in the backplane module 20, acquired by the second processing unit 102 in the motherboard module 10, is the second storage unit 220 is accessed, the second processing unit 102 in the motherboard module 10 is in communication connection with the second logic interface 203 of the logic control unit 200, so that the second processing unit 102 in the motherboard module 10 outputs the indication information corresponding to the second storage unit 220 to the logic control unit 200.
The storage system provided by the embodiment of the disclosure, the motherboard module includes a first processing unit and a second processing unit, the logic control unit includes a first logic interface and a second logic interface, the first processing unit of the motherboard module acquires state information corresponding to the first storage unit, the second processing unit of the motherboard module acquires state information corresponding to the second storage unit, when the state information of the first storage unit acquired by the first processing unit in the motherboard module is access, the first processing unit is in communication connection with the first logic interface of the logic control unit, so that the first processing unit in the motherboard module outputs indication information corresponding to the first storage unit to the logic control unit, and when the state information of the second storage unit acquired by the second processing unit in the motherboard module is access, the second processing unit is in communication connection with the second logic interface of the logic control unit, and the second processing unit in the main board module outputs the indication information corresponding to the second storage unit to the logic control unit.
Fig. 4 is a schematic structural diagram of another memory system provided by an embodiment of the present disclosure, and in the embodiment of the present disclosure, on the basis of the above-mentioned embodiment, as shown in fig. 4, the logic control unit 200 further includes a control chip 204, a first end of the control chip 204 is communicatively connected to a second end of the first logic interface 202, a second end of the control chip 204 is communicatively connected to a second end of the second logic interface 203, and a third end of the control chip 204 is communicatively connected to the I2C interface 201.
As shown in fig. 4, the first end of the control chip 204 is communicatively connected to the second end of the first logic interface 202, the second end of the control chip 204 is communicatively connected to the second end of the second logic interface 203, the third end of the control chip 204 is communicatively connected to the I2C interface 201, when the state information of the first storage unit 210 in the backplane module 20, acquired by the first processing unit 101 in the motherboard module 10, is the access of the first storage unit 210, the first processing unit 101 in the motherboard module 10 is communicatively connected to the first logic interface 202 of the logic control unit 200, and the control chip 204 acquires the indication information, received by the first logic interface 202, corresponding to the first storage unit 210 output by the first processing unit 101 in the motherboard module 10. When the state information of the second storage unit 220 in the backplane module 20, acquired by the second processing unit 102 in the motherboard module 10, is the second storage unit 220 is accessed, the second processing unit 102 in the motherboard module 10 is in communication connection with the second logic interface 203 of the logic control unit 200, and the control chip 204 acquires the indication information, received by the second logic interface 203, corresponding to the second storage unit 220 output by the second processing unit 102 in the motherboard module 10, of the second storage unit 220.
Illustratively, the indication information corresponding to the first storage unit 210 output by the first processing unit 101 in the motherboard module 10 is an I2C instruction output by the first processing unit 101, and the indication information corresponding to the second storage unit 220 output by the second processing unit 102 in the motherboard module 10 is an SGPIO instruction output by the second processing unit 102.
In addition, a third terminal of the control chip 204 is configured to be communicatively connected to the I2C interface 201, and the control chip 204 transmits the acquired status information corresponding to each hard disk in the backplane module 20 and the acquired indication information corresponding to each hard disk to the motherboard module 10 through the I2C interface 201. Specifically, when the state information of the first storage unit 210 in the backplane module 20, acquired by the first processing unit 104 in the motherboard module 10, is that the first storage unit 210 is accessed, the first processing unit 101 in the motherboard module 10 outputs the indication information corresponding to the first storage unit 210 to the control chip 204, and the control chip 204 outputs the acquired state information and indication information corresponding to the first storage unit 210 to the management unit 100 in the motherboard module 10. When the state information of the second storage unit 220 in the backplane module 20, acquired by the second processing unit 102 in the motherboard module 10, is the second storage unit 220 accessed, the second processing unit 102 in the motherboard module 10 outputs the indication information corresponding to the second storage unit 220 to the control chip 204, and the control chip 204 outputs the acquired state information and indication information corresponding to the second storage unit 220 to the management unit 100 in the motherboard module 10.
Optionally, the backplane module 20 further includes a first indication unit 230 and a second indication unit 240, where the first indication unit is connected to the fifth end of the control chip in a communication manner, and the second indication unit is connected to the sixth end of the control chip in a communication manner.
With continued reference to fig. 4, the backplane module further includes a first indication unit 230 and a second indication unit 240, the first indication unit 230 is used to indicate the status information corresponding to the first storage unit 210, and the second indication unit 240 is used to indicate the status information corresponding to the second storage unit 220.
Specifically, when the state information of the first storage unit 210 in the backplane module 20, acquired by the first processing unit 101 in the motherboard module 10, is the access of the first storage unit 210, the first processing unit 101 in the motherboard module 10 is in communication connection with the first logic interface 202 of the logic control unit 200, the control chip 204 acquires the indication information, received by the first logic interface 202, corresponding to the first storage unit 210 output by the first processing unit 101 in the motherboard module 10, and outputs the indication information corresponding to the first storage unit 210 to the first indication unit 230, and the first indication unit 230 indicates the state of the first indication unit 230 according to the indication information corresponding to the first storage unit 210. When the state information of the second storage unit 220 in the backplane module 20, acquired by the second processing unit 102 in the motherboard module 10, is the second storage unit 220 access, the second processing unit 102 in the motherboard module 10 is in communication connection with the second logic interface 203 of the logic control unit 200, the control chip 204 acquires the indication information, received by the second logic interface 203, corresponding to the second storage unit 220 output by the second processing unit 102 in the motherboard module 10, and outputs the indication information corresponding to the second storage unit 220 to the second indication unit 240, and the second indication unit 240 indicates the state of the second indication unit 240 according to the indication information corresponding to the second storage unit 220.
Optionally, the first indication unit 230 and the second indication unit 240 respectively include a first indication lamp, a second indication lamp and a third indication lamp, the first indication lamp is used for indicating that the storage unit is in a normal state, the second indication lamp is used for indicating that the storage unit is in an abnormal state, and the third indication lamp is used for indicating the location information of the storage unit.
Specifically, with continued reference to fig. 4, the first indication unit 230 includes a first indicator light 231, a second indicator light 232, and a third indicator light 233. When the state information of the first storage unit 210 in the backplane module 20, acquired by the first processing unit 101 in the motherboard module 10, is the access of the first storage unit 210, the first processing unit 101 in the motherboard module 10 is in communication connection with the first logic interface 202 of the logic control unit 200, the control chip 204 acquires the indication information, received by the first logic interface 202, corresponding to the first storage unit 210 output by the first processing unit 101 in the motherboard module 10, and outputs the indication information corresponding to the first storage unit 210 to the first indication unit 230, and the first indication unit 230 indicates the state of the first indication unit 230 according to the indication information corresponding to the first storage unit 210. For example, if the first processing unit 101 outputs the indication information that the first storage unit 210 is in the normal state to the control chip 204, at this time, the control chip 204 outputs the indication information that the first storage unit 210 is in the normal state to the first indicator 231 to realize that the first indicator 231 is on, if the first processing unit 101 outputs the indication information that the first storage unit 210 is in the abnormal state to the control chip 204, at this time, the control chip 204 outputs the indication information that the first storage unit 210 is in the abnormal state to the second indicator 232 to realize that the second indicator 232 is on, and/or if the first processing unit 101 outputs the indication information that the first storage unit 210 is in the normal state to the control chip 204, at this time, the control chip 204 outputs the indication information that the first storage unit 210 is in the normal state to the third indicator 233 to realize that the third indicator is on.
It should be noted that, after the first processing unit outputs the indication information that the first storage unit is in the normal state to the control chip, if the control chip outputs the indication information that the first storage unit is in the normal state to the first indicator light, it can only be stated that the state information of the first storage unit is normal at this time, after the first processing unit outputs the indication information that the first storage unit is in the normal state to the control chip, if the control chip outputs the indication information that the first storage unit is in the normal state to the third indicator light, it can be stated that the state information of the first storage unit is in the normal state and the position information corresponding to the first storage unit at this time, in another possible implementation, after the first processing unit outputs the indication information that the first storage unit is in the normal state to the control chip, the control chip outputs the indication information that the first storage unit is in the normal state to the first indicator light and the third indicator light, at this time, the first indicator light indicates that the state information of the first storage unit is normal, and the third indicator light indicates the position information of the first storage unit.
In addition, the second indicating unit 240 includes a first indicating lamp 241, a second indicating lamp 242 and a third indicating lamp 243, and the logic of the control chip 204 controlling the second indicating unit 240 is the same as the logic of the control chip 204 controlling the first indicating unit 230, which is not described again.
Optionally, the first processing unit 101 comprises an X86 processor and the second processing unit 102 comprises a bridge piece.
Optionally, the first processing unit 101 and the first logical interface 202 communicate through PCIe protocol, and the second processing unit 102 and the second logical interface 203 communicate through SATA protocol.
Optionally, the first storage unit 210 includes NVMe hard disks, and the second storage unit 220 includes SATA hard disks.
Specifically, when the first storage unit 210 includes an NVMe hard disk, the second storage unit 220 includes an SATA hard disk, the first processing unit 101 includes an X86 processor, and the second processing unit 102 includes a bridge chip, the first processing unit 101 communicates with the first logic interface 202 through a PCIe protocol, the second processing unit 102 communicates with the second logic interface 203 through a SATA protocol, the logic implementation logic control unit X86 processor communicates with a logic implementation logic control unit X9555 recommended by Intel, and the logic implementation logic control unit communicates with the bridge chip using SGPIO logic.
In addition, according to the storage system provided by the embodiment of the present disclosure, the communication portion between the logic control unit 200 and the management unit 100 in the motherboard module 10 is optimized in the backplane module 20, and a logic communication module for converting I2C to 8IO based on the function of the TCA6408 chip is designed, that is, an I2C interface in the logic control unit can implement logic for converting I2C to 8 IO.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A storage system, comprising: the system comprises a mainboard module and a backplane module, wherein the backplane module comprises a logic control unit, and the logic control unit comprises an I2C interface;
the logic control unit is in communication connection with the mainboard module through the I2C interface, acquires state information corresponding to each hard disk in the backboard module and indication information corresponding to each hard disk, and transmits the acquired state information corresponding to each hard disk in the backboard module and the indication information corresponding to each hard disk to the mainboard module through the I2C interface.
2. The system of claim 1, wherein the motherboard module comprises a management unit;
the logic control unit is in communication connection with the management unit of the mainboard module through the I2C interface.
3. The system of claim 1 or 2, wherein the motherboard module further comprises a first processing unit and a second processing unit, the logic control unit further comprises a first logic interface and a second logic interface;
the first end of the first processing unit is in communication connection with the first end of the first logic interface, and the first end of the second processing unit is in communication connection with the first end of the second logic interface.
4. The system of claim 3, wherein the backplane module further comprises a first storage unit and a second storage unit;
the first storage unit is in communication connection with the second end of the first processing unit, and the second storage unit is in communication connection with the second end of the second processing unit.
5. The system of claim 4, wherein the logic control unit further comprises a control chip;
the first end of the control chip is in communication connection with the second end of the first logic interface, the second end of the control chip is in communication connection with the second end of the second logic interface, and the third end of the control chip is in communication connection with the I2C interface.
6. The system of claim 5, wherein the backplane module further comprises a first indication unit and a second indication unit;
the first indicating unit is in communication connection with a fifth end of the control chip, and the second indicating unit is in communication connection with a sixth end of the control chip.
7. The system of claim 6, wherein the first and second indication units comprise first, second, and third indication lights, respectively;
the first indicator light is used for indicating that the storage unit is in a normal state, the second indicator light is used for indicating that the storage unit is in an abnormal state, and the third indicator light is used for indicating the position information of the storage unit.
8. The system of claim 4, wherein the first processing unit comprises an X86 processor and the second processing unit comprises a bridge piece.
9. The system of claim 8, wherein the first storage unit comprises NVMe hard disks and the second storage unit comprises SATA hard disks.
10. The system of claim 9, wherein the first processing unit and the first logical interface communicate via a PCIe protocol and the second processing unit and the second logical interface communicate via a SATA protocol.
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