CN216624287U - Shielded gate trench transistor - Google Patents
Shielded gate trench transistor Download PDFInfo
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- CN216624287U CN216624287U CN202120521945.3U CN202120521945U CN216624287U CN 216624287 U CN216624287 U CN 216624287U CN 202120521945 U CN202120521945 U CN 202120521945U CN 216624287 U CN216624287 U CN 216624287U
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- insulating layer
- interlayer insulating
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Abstract
A shielded gate type trench transistor comprises a substrate with a trench, a lower electrode arranged at the lower part of the trench, an upper electrode arranged at the upper part of the trench, and an interlayer insulating layer, wherein the upper surface of the upper electrode is formed by a chemical mechanical polishing process, so that the upper electrode has a flat upper surface, and the interlayer insulating layer is formed by a chemical vapor deposition process, so that the interlayer insulating layer has a flat upper surface. The interlayer insulating layer is formed by a chemical vapor deposition process, so that the interlayer insulating layer is thicker than the interlayer insulating layer in the prior art and has a flat upper surface, and the lower surface of the upper electrode is flat due to the fact that the lower surface of the upper electrode is formed on the upper surface of the interlayer insulating layer; after the upper electrode is formed, the upper surface of the upper electrode is subjected to chemical mechanical polishing, so that the upper electrode etching-back process can be uniformly etched, and the upper electrode has a flat upper surface; the improved upper electrode has flat upper and lower surfaces, thereby achieving the effect of improving the reliability of the product.
Description
Technical Field
The present invention relates to transistors, and more particularly, to a shielded gate trench transistor.
Background
A shielded gate trench transistor (SGT) includes a single trench electrode structure including an upper electrode, an interlayer insulating layer, and a lower electrode, the upper electrode being isolated from a substrate by an upper dielectric layer, and the lower electrode being isolated from the substrate by a lower dielectric layer. Typically, the upper electrode is electrically connected to the gate of the device, the lower electrode is electrically connected to the source of the device, and the substrate is electrically connected to the drain of the device. The interlayer insulating layer in the prior art is formed by only one thermal oxidation process, the thickness of the interlayer insulating layer is thin, the thermal oxidation process is conformal, if the previous etched structure is uneven, the surface of the subsequently formed interlayer insulating layer is easy to form an uneven structure, so that the lower surface of the upper electrode is uneven, a V-shaped recess appears on the top surface of the upper electrode, and the point discharge occurs at the concave-convex part of the electrode; in addition, the thickness of the interlayer insulating layer is not uniform, so that the capacitance of the device is not uniform, and the reliability of the device is not good.
SUMMERY OF THE UTILITY MODEL
The technical problem to be solved by the present invention is to provide a shielded gate trench transistor, which solves the technical problems existing in the prior art.
In order to solve the technical problems, the technical scheme of the utility model is as follows: a shielded grid type groove transistor comprises a substrate with a groove, a lower electrode arranged at the lower part of the groove, an upper electrode arranged at the upper part of the groove and an interlayer insulating layer, wherein the upper surface of the upper electrode is formed by a chemical mechanical polishing process, so that the upper electrode has a flat upper surface, and the interlayer insulating layer is formed by a chemical vapor deposition process, so that the interlayer insulating layer has a flat upper surface.
The principle of the utility model is as follows: the interlayer insulating layer is formed by a chemical vapor deposition process, so that the interlayer insulating layer is thicker than the interlayer insulating layer in the prior art and has a flat upper surface, and the lower surface of the upper electrode is flat due to the fact that the lower surface of the upper electrode is formed on the upper surface of the interlayer insulating layer; after the upper electrode is formed, the upper surface of the upper electrode is subjected to chemical mechanical polishing, so that the upper electrode etching-back process can be uniformly etched, and the upper electrode has a flat upper surface; the improved upper electrode has flat upper and lower surfaces, thereby achieving the effect of improving the reliability of the product.
As a modified chemical mechanical polishing process, is polished together with the upper electrode and the substrate surface to form the upper surface of the upper electrode.
As a modification, after the chemical mechanical polishing process, an etching process is also performed to form an upper surface of the upper electrode.
As an improvement, the interlayer insulating layer has an upper surface and a lower surface, wherein the upper surface is larger than the lower surface.
As an improvement, the thickness of the interlayer insulating layer is 1200A-1500A.
As an improvement, the shielded gate type trench transistor further comprises a lower dielectric layer arranged at the lower part of the trench and used for isolating the lower electrode from the substrate.
As an improvement, the shielded gate type trench transistor further comprises an upper dielectric layer arranged on the upper part of the trench and used for isolating the upper electrode from the substrate.
Compared with the prior art, the utility model has the following beneficial effects:
the interlayer insulating layer is formed by a chemical vapor deposition process, so that the interlayer insulating layer is thicker than the interlayer insulating layer in the prior art and has a flat upper surface, and the lower surface of the upper electrode is flat due to the fact that the lower surface of the upper electrode is formed on the upper surface of the interlayer insulating layer; after the upper electrode is formed, the upper surface of the upper electrode is subjected to chemical mechanical polishing, so that the upper electrode etching-back process can be uniformly etched, and the upper electrode has a flat upper surface; the improved upper electrode has flat upper and lower surfaces, thereby achieving the effect of improving the reliability of the product.
Drawings
FIG. 1 is a schematic view of the structure of the present invention.
Detailed Description
The utility model is further described below with reference to the accompanying drawings.
As shown in fig. 1, a shielded gate trench transistor includes a substrate 4 having a trench, a lower electrode 3 provided in a lower portion of the trench, an upper electrode 1 provided in an upper portion of the trench, and an interlayer insulating layer 2 provided between the lower electrode 3 and the upper electrode 1. The shielded gate type trench transistor further comprises a lower dielectric layer 6 arranged at the lower part of the trench and isolating the lower electrode from the substrate; the shielded gate trench transistor further includes an upper dielectric layer disposed on the upper portion of the trench to isolate the upper electrode from the substrate.
The interlayer insulating layer is formed by a chemical vapor deposition process, so that the interlayer insulating layer 2 has flat upper and lower surfaces, the thickness of the interlayer insulating layer is 1200A-1500A, and the upper surface of the interlayer insulating layer 2 is larger than the lower surface; since the lower surface of the upper electrode is formed on the upper surface of the interlayer insulating layer, the lower surface of the upper electrode becomes flat. After the upper electrode is formed, the upper surface of the upper electrode is ground together with the upper electrode and the surface of the substrate through chemical mechanical grinding to form the upper surface of the upper electrode, so that the subsequent upper electrode etch-back process can evenly etch, and the upper electrode has a flat upper surface. The improved upper electrode has flat upper and lower surfaces, thereby achieving the effect of improving the reliability of the product.
Claims (6)
1. A shielded gate trench transistor comprising:
a substrate having a trench;
a lower electrode disposed at a lower portion of the trench;
the upper electrode is arranged at the upper part of the groove, wherein the upper surface of the upper electrode is formed by a chemical mechanical polishing process, so that the upper electrode has a flat upper surface;
and
an interlayer insulating layer disposed between the lower electrode and the upper electrode,
the interlayer insulating layer is formed through a chemical vapor deposition process, so that the interlayer insulating layer has a flat upper surface;
the lower surface of the upper electrode is formed on the upper surface of the interlayer insulating layer so that the lower surface of the upper electrode becomes flat.
2. The shielded gate trench transistor of claim 1 wherein: the chemical mechanical polishing process is polished along with the upper electrode and the substrate surface to form the upper surface of the upper electrode.
3. The shielded gate trench transistor of claim 1 wherein: the interlayer insulating layer has the upper surface and a lower surface, wherein the upper surface is larger than the lower surface.
4. The shielded gate trench transistor of claim 1 wherein: the thickness of the interlayer insulating layer is 1200A-1500A.
5. The shielded gate trench transistor of claim 1 wherein: the shielded gate trench transistor further includes a lower dielectric layer disposed at a lower portion of the trench to isolate the lower electrode from the substrate.
6. The shielded gate trench transistor of claim 1 wherein: the shielded gate trench transistor further includes an upper dielectric layer disposed on the upper portion of the trench to isolate the upper electrode from the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120521945.3U CN216624287U (en) | 2021-03-12 | 2021-03-12 | Shielded gate trench transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120521945.3U CN216624287U (en) | 2021-03-12 | 2021-03-12 | Shielded gate trench transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216624287U true CN216624287U (en) | 2022-05-27 |
Family
ID=81681083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120521945.3U Active CN216624287U (en) | 2021-03-12 | 2021-03-12 | Shielded gate trench transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216624287U (en) |
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2021
- 2021-03-12 CN CN202120521945.3U patent/CN216624287U/en active Active
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