CN216623243U - Connection circuit and electronic device - Google Patents
Connection circuit and electronic device Download PDFInfo
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- CN216623243U CN216623243U CN202122984239.5U CN202122984239U CN216623243U CN 216623243 U CN216623243 U CN 216623243U CN 202122984239 U CN202122984239 U CN 202122984239U CN 216623243 U CN216623243 U CN 216623243U
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Abstract
The embodiment of the utility model provides a connecting circuit and electronic equipment. The method comprises the following steps: a main board chip and an image chip; the mainboard chip is provided with a first protocol transmission pin, a second protocol transmission pin, a third protocol transmission pin, a first signal transmission pin, a second signal transmission pin and a first reset pin; the image chip is provided with a fourth protocol transmission pin, a fifth protocol transmission pin, a sixth protocol transmission pin, a third signal transmission pin, a fourth signal transmission pin and a second reset pin; the first protocol transmission pin is electrically connected with the fourth protocol transmission pin, the second protocol transmission pin is electrically connected with the fifth protocol transmission pin, and the third protocol transmission pin is electrically connected with the sixth protocol transmission pin.
Description
Technical Field
The utility model relates to the technical field of electronic equipment, in particular to a connecting circuit and electronic equipment.
Background
With the development of science and technology, electronic devices are more and more widely applied. Generally, electronic equipment comprises a main board and a camera module, wherein the main board and the camera module are electrically connected through a conductive piece, but the number of the required conductive pieces is usually more.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a connecting circuit and electronic equipment, and aims to solve the problem that in the related art, a mainboard is electrically connected with a camera module through a conductive piece, but the number of the required conductive pieces is usually large.
In order to solve the technical problem, the utility model is realized as follows:
in a first aspect, an embodiment of the present invention provides a connection circuit, including: a motherboard chip and an image chip;
the mainboard chip is provided with a first protocol transmission pin, a second protocol transmission pin, a third protocol transmission pin, a first signal transmission pin, a second signal transmission pin and a first reset pin; the image chip is provided with a fourth protocol transmission pin, a fifth protocol transmission pin, a sixth protocol transmission pin, a third signal transmission pin, a fourth signal transmission pin and a second reset pin;
the first protocol transmission pin is electrically connected with the fourth protocol transmission pin, the second protocol transmission pin is electrically connected with the fifth protocol transmission pin, and the third protocol transmission pin is electrically connected with the sixth protocol transmission pin;
the first signal transmission pin and the first reset pin are electrically connected to the second protocol transmission pin, the second signal transmission pin is electrically connected to the third protocol transmission pin, the third signal pin and the second reset pin are electrically connected to the fifth protocol transmission pin, and the fourth signal pin is electrically connected to the sixth protocol transmission pin.
In a second aspect, an embodiment of the present invention provides an electronic device, which includes the connection circuit described in the first aspect.
In the embodiment of the present invention, since the first protocol transmission pin and the fourth protocol transmission pin are electrically connected through the first conductive member, the second protocol transmission pin and the fifth protocol transmission pin are electrically connected through the second conductive member, and the third protocol transmission pin and the sixth protocol transmission pin are electrically connected through the third conductive member, signals can be transmitted between the first protocol transmission pin and the fourth protocol transmission pin, between the second protocol transmission pin and the fifth protocol transmission pin, and between the third protocol transmission pin and the sixth protocol transmission pin. Because the first signal transmission pin and the first reset pin are electrically connected to the second conductive member, and the third signal pin and the second reset pin are electrically connected to the second conductive member, the signal transmission path of the first signal transmission pin, the first reset pin and the second protocol signal multiplexing second protocol transmission pin is equivalent, and the signal transmission path of the third signal pin and the second reset pin multiplexing second protocol transmission pin is also equivalent. In addition, the second signal transmission pin is electrically connected to the third conductive member, the fourth signal pin is electrically connected to the third conductive member, and the signal transmission path multiplexing the third protocol transmission pin with the third signal pin and the signal transmission path multiplexing the fourth protocol transmission pin with the fourth signal pin are equivalent. That is, in the embodiment of the present invention, the number of pins can be reduced by multiplexing the signal transmission paths.
Drawings
FIG. 1 is a schematic diagram of a connection circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a first impedance matcher provided in an embodiment of the present invention.
Reference numerals:
10: a main board; 20: a camera module; 30: a first voltage converter; 40: a second voltage converter; 50: a first impedance matcher; 60: a second impedance matcher; 70: a voltage regulator; 80: a clock generator; 11: a motherboard chip; 21: an image chip; 22: a resistor group; 51: a first capacitor; 52: a second capacitor; 53: an inductance; 91: a first ground contact; 92: a second ground contact; 101: a first conductive member; 102: a second conductive member; 103: a third conductive member; 104: a fourth conductive member; 105: a fifth conductive member; 221: a first voltage dividing resistor; 222: a second voltage dividing resistor; 223: and a third voltage dividing resistor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Referring to fig. 1, a schematic diagram of a connection circuit according to an embodiment of the present invention is shown, and referring to fig. 2, a schematic diagram of a first impedance matcher according to an embodiment of the present invention is shown, and as shown in fig. 1 and fig. 2, the connection circuit includes: a motherboard chip 11 and an image chip 21.
The main board chip 11 is provided with a first protocol transmission pin, a second protocol transmission pin, a third protocol transmission pin, a first signal transmission pin, a second signal transmission pin and a first reset pin; the image chip 21 has a fourth protocol transmission pin, a fifth protocol transmission pin, a sixth protocol transmission pin, a third signal transmission pin, a fourth signal transmission pin, and a second reset pin.
The first protocol transmission pin is electrically connected with the fourth protocol transmission pin, the second protocol transmission pin is electrically connected with the fifth protocol transmission pin, and the third protocol transmission pin is electrically connected with the sixth protocol transmission pin. The first signal transmission pin and the first reset pin are electrically connected to the second protocol transmission pin, the second signal transmission pin is electrically connected to the third protocol transmission pin, the third signal pin and the second reset pin are electrically connected to the fifth protocol transmission pin, and the fourth signal pin is electrically connected to the sixth protocol transmission pin.
In the embodiment of the present invention, since the first protocol transmission pin is electrically connected to the fourth protocol transmission pin, the second protocol transmission pin is electrically connected to the fifth protocol transmission pin, and the third protocol transmission pin is electrically connected to the sixth protocol transmission pin, signals can be transmitted between the first protocol transmission pin and the fourth protocol transmission pin, between the second protocol transmission pin and the fifth protocol transmission pin, and between the third protocol transmission pin and the sixth protocol transmission pin. The first signal transmission pin and the first reset pin are electrically connected to the second protocol transmission pin, and the third signal pin and the second reset pin are electrically connected to the fifth protocol transmission pin, so that the first signal transmission pin, the first reset pin and the second protocol signal multiplex a signal transmission path of the second protocol transmission pin, and the third signal pin and the second reset pin also multiplex a signal transmission path of the second protocol transmission pin. In addition, the second signal transmission pin is electrically connected to the third protocol transmission pin, the fourth signal pin is electrically connected to the sixth protocol transmission pin, which is equivalent to the third signal pin multiplexing the signal transmission path of the third protocol transmission pin, and the fourth signal pin multiplexing the signal transmission path of the fourth protocol transmission pin. That is, in the embodiment of the present invention, the number of conductive members can be reduced by multiplexing signal transmission paths.
For example, as shown in fig. 1, the main board chip 11 may be a module where the SOC is located, the first protocol transmission pin may be a pin CPHY _ a, the second protocol transmission pin may be a CPHY _ B, the third protocol transmission pin may be a CPHY _ C, the first signal pin may be a pin SDA, the second signal pin may be an SCL, and the first reset pin may be a pin RST. The image chip 21 may be a module where the Sensor IC is located, the fourth protocol transmission pin may be a pin CPHY _ a, the fifth protocol transmission pin may be a pin CPHY _ B, the sixth protocol transmission pin may be a pin CPHY _ C, the third signal pin may be a pin SDA, the fourth signal pin may be a pin SCL, and the second reset pin may be a pin RST.
In addition, in the embodiment of the present invention, the first protocol transmission pin, the second protocol transmission pin, the third protocol transmission pin, the fourth protocol transmission pin, the fifth protocol transmission pin, and the sixth protocol transmission pin transmit a target communication protocol, and the target protocol is a CPHY protocol.
In addition, in the embodiment of the present invention, the first protocol transmission pin and the fourth protocol transmission pin may be electrically connected through the first conductive member 101, the second protocol transmission pin and the fifth protocol transmission pin are electrically connected through the second conductive member 102, and the third protocol transmission pin and the sixth protocol transmission pin are electrically connected through the third conductive member 103. Of course, the first protocol transmission pin and the fourth protocol transmission pin can be directly welded to realize electric connection, the second protocol transmission pin and the fifth protocol transmission pin are directly welded to realize electric connection, and the third protocol transmission pin and the sixth protocol transmission pin are directly welded to realize electric connection. The embodiments of the present invention are not limited thereto.
In addition, the first signal transmission pin and the first reset pin are electrically connected to the second conductive member 102, the third signal pin and the second reset pin are electrically connected to the second conductive member 102, which is equivalent to the first signal transmission pin, the first reset pin and the second protocol signal multiplexing the signal transmission path of the second protocol transmission pin, and the third signal pin and the second reset pin also multiplexing the signal transmission path of the second protocol transmission pin. The second signal transmission pin is electrically connected to the third conductive member 103, and the fourth signal pin is electrically connected to the third conductive member 103, which is equivalent to the third signal pin multiplexing the signal transmission path of the third protocol transmission pin, and the fourth signal pin multiplexing the signal transmission path of the fourth protocol transmission pin.
In addition, in the embodiment of the present invention, the camera module 20 needs to be reset by the RST signal before operating. Before the RST signal is reset, the pin CPHY _ a, the pin CPHY _ B, the pin CPHY _ C, the pin SDA, and the pin SCL on the motherboard chip 11 do not transmit signals with the pin CPHY _ a, the pin CPHY _ B, the pin CPHY _ C, the pin SDA, and the pin SCL on the image chip 21, and therefore the pin RST on the motherboard chip 11 can transmit the RST signal to the pin RST on the image chip 21 through the second conductive member 102, so that the camera module 20 can be reset through the RST signal. In addition, after the camera module 20 is reset, communication between the motherboard 10 and the camera module 20 is required, and specifically, signals are transmitted to pins SDA and SCL on the image chip 21 through pins SDA and SCL on the motherboard chip 11, wherein, the pin SDA on the motherboard chip 11 transmits signals with the pin SDA on the image chip 21 through the second conductive member 102, the pin SCL on the motherboard chip 11 transmits signals with the pin SCL on the image chip 21 through the third conductive member 103, and when the pin SDA on the motherboard chip 11 and the pin SDA on the image chip 21 transmit signals, the pin SCL on the motherboard chip 11 and the pin SCL on the image chip 21 transmit signals, the pins CPHY _ A, CPHY _ B and CPHY _ C on the motherboard chip 11 transmit signals with the pins CPHY _ A, CPHY _ B and CPHY _ C on the image chip 21.
In addition, after the pin SDA and the pin SCL on the motherboard chip 11 transmit signals, the pin CPHY _ a, the pin CPHY _ B, and the pin CPHY _ C on the motherboard chip 11 transmit signals with the pin CPHY _ a, the pin CPHY _ B, and the pin CPHY _ C on the image chip 21 through the first conductive member 101, the second conductive member 102, and the third conductive member 103, respectively, and when the pin CPHY _ a, the pin CPHY _ B, and the pin CPHY _ C on the motherboard chip 11 transmit signals, the pin SDA, the pin SCL, and the pin RST on the motherboard chip 11 do not transmit signals. Therefore, multiplexing of signal paths can be realized, and interference can not be caused in the signal transmission process.
It should be noted that the signal transmission described above is based on the signal transmission having a timing relationship, so that the number of conductive members can be reduced by multiplexing signal paths. In addition, in the embodiment of the present invention, the CPHY protocol is adopted, and since the protocol itself needs fewer pins, after the CPHY protocol is adopted, the number of pins on the motherboard chip 11 and the number of pins on the image chip 21 can be reduced, so that the number of conductive components can be reduced. The number of conductive elements can then be further reduced by multiplexing the signals.
Additionally, in some embodiments, the connection circuit may further include a first voltage converter 30 and a second voltage converter 40. The first signal pin, the second signal pin and the first reset pin are electrically connected to a first end of the first voltage converter 30, and a second end of the first voltage converter 30 is electrically connected to the second protocol transmission pin and the third protocol transmission pin. The third signal pin, the fourth signal pin and the second reset pin are electrically connected to a first end of the second voltage converter 40, and a second end of the second voltage converter 40 is electrically connected to the fifth protocol transmission pin and the sixth protocol transmission pin. The first voltage converter 30 is used for converting the first voltage into the second voltage, and the second voltage converter 40 is used for converting the second voltage into the first voltage. Wherein the first voltage is greater than the second voltage.
When the first protocol transmission pin and the fourth protocol transmission pin are electrically connected through the first conductive member 101, the second protocol transmission pin and the fifth protocol transmission pin are electrically connected through the second conductive member 102, the third protocol transmission pin and the sixth protocol transmission pin are electrically connected through the third conductive member 103, the first signal transmission pin and the first reset pin are electrically connected to the second conductive member 102, the second signal transmission pin is electrically connected to the third conductive member 103, the third signal pin and the second reset pin are electrically connected to the second conductive member 102, and the fourth signal pin is electrically connected to the third conductive member 103, at this time, when the CPHY protocol is transmitted, the level required is generally small, and the withstand voltage of the pins on the image chip 21 is relatively low, but the levels of the first signal pin, the second signal pin and the first reset pin on the main board chip 11 are generally high, i.e., the levels on pins SDA, SCL, and RST on motherboard chip 11 are generally higher. The levels of the third signal pin, the fourth signal pin, and the second reset pin on the image chip 21 are generally high, that is, the levels of the pins SDA, SCL, and RST on the image chip 21 are generally high.
Since the second conductive member 102 and the third conductive member 103 may be damaged by a higher level, the first signal pin, the second signal pin and the first reset pin may be electrically connected to the first end of the first voltage converter 30, and the second end of the first voltage converter 30 is electrically connected to the second conductive member 102 and the third conductive member 103. The third signal pin, the fourth signal pin and the second reset pin are electrically connected to the first end of the second voltage converter 40, and the second end of the second voltage converter 40 is electrically connected to the second conductive member 102 and the third conductive member 103, so that the first voltage converter 30 converts the first voltage into the second voltage, and then the second conductive member 102 and the third conductive member 103 transmit the voltage according to the second voltage. When the second voltage is transmitted to the second voltage converter 40, the second voltage converter 40 converts the second voltage into the first voltage, and then transmits the first voltage to the third signal pin, the fourth signal pin and the second reset pin on the image chip 21, so that the pins on the image chip 21 can operate according to the normal voltage.
For example, the voltage on the pin SDA, the pin SCL, and the pin RST on the motherboard chip 11 is 1.8V, and the voltage of 1.8V can be converted into 1.2V by the first voltage converter 30, and at this time, the voltage of 1.2V is transmitted on the second conductive member 102 and the third conductive member 103. When passing to the second voltage converter 40, the second voltage converter 40 converts the voltage of 1.2V into 1.8V, and then passes to the pins SDA, SCL, and RST on the image chip 21.
In addition, due to multiplexing of signal paths, impedance changes in the whole connection circuit may be caused, so that the transmission signal may be affected, and in order to avoid such a problem, in the embodiment of the present invention, as shown in fig. 1, the connection circuit may further include a first impedance matcher 50 and a second impedance matcher 60. A first end of the first impedance matcher 50 is electrically connected to a second end of the first voltage converter 30, and a second end of the first impedance matcher 50 is electrically connected to the second protocol transmission pin and the third protocol transmission pin, respectively. A first end of the second impedance matcher 60 is electrically connected to a second end of the second voltage converter 40, and a second end of the second impedance matcher 60 is electrically connected to the fifth protocol transmission pin and the sixth protocol transmission pin, respectively. The first impedance matching unit and the second impedance matching unit 60 are used to adjust the impedance in the connection circuit.
Since the first impedance matcher 50 is electrically connected to the first voltage converter 30, the second protocol transmission pin and the third protocol transmission pin, the second impedance matcher 60 is electrically connected to the second voltage converter 40, the fifth protocol transmission pin and the sixth protocol transmission pin, and the second protocol transmission pin, the third protocol transmission pin, the fifth protocol transmission pin and the sixth protocol transmission pin are signal paths and multiplexed signal paths, after the first impedance matcher 50 and the second impedance matcher 60 are connected, signals transmitted on the second protocol transmission pin, the third protocol transmission pin, the fifth protocol transmission pin and the sixth protocol transmission pin are not influenced by impedance, which is beneficial to signal transmission.
When the first signal transmission pin and the first reset pin are electrically connected to the second conductive member, the second signal transmission pin is electrically connected to the third conductive member, the third signal pin and the second reset pin are electrically connected to the second conductive member, and the fourth signal pin is electrically connected to the third conductive member, at this time, the first impedance matcher 50 is respectively electrically connected to the first voltage converter 30, the second conductive member 102, and the third conductive member 103, the second impedance matcher 60 is respectively electrically connected to the second voltage converter 40, the second conductive member 102, and the third conductive member 103, and the second conductive member 102 and the third conductive member 103 are both signal paths and are multiplexed signal paths, so that signals transmitted through the second conductive member 102 and the third conductive member 103 are not hindered after the first impedance matcher 50 and the second impedance matcher 60 are connected, is beneficial to signal transmission.
The first impedance matching unit 50 and the second impedance matching unit 60 may have a resistance of 50 ohms in the connection circuit.
In addition, in some embodiments, as shown in fig. 2, the first impedance matcher 50 may include a first capacitor 51, a second capacitor 52, and an inductor 53. A first end of the inductor 53 is electrically connected to a first end of the first capacitor 51 and a second end of the first voltage converter 30, respectively, and a second end of the first capacitor 51 is grounded. A second terminal of the inductor 53 is electrically connected to the first terminal of the second capacitor 52, the second protocol transmission pin, and the third protocol transmission pin, respectively.
That is, the first capacitor 51, the second capacitor 52 and the inductor 53 are connected to form a passive circuit, and form an impedance matching circuit, that is, an impedance matcher is formed, and impedance in the connection circuit can be matched, so that signals transmitted by the second protocol transmission pin and the third protocol transmission pin are not affected by impedance. When the first signal transmission pin and the first reset pin are electrically connected to the second conductive member 102, the second signal transmission pin is electrically connected to the third conductive member 103, the third signal pin and the second reset pin are electrically connected to the second conductive member 102, and the fourth signal pin is electrically connected to the third conductive member 103, at this time, the transmission signals on the second conductive member 102 and the third conductive member 103 are not hindered and are beneficial to signal transmission.
The second impedance matching unit 60 has the same configuration as the first impedance matching unit 50.
In addition, in the embodiment of the present invention, the number of the first capacitors 51 and the second capacitors 52 may be set according to actual requirements, for example, the number of the first capacitors 51 is 3, in this case, 3 first capacitors 51 may be connected in parallel, the number of the second capacitors 52 may be 4, and 4 first capacitors 51 may be connected in parallel. In addition, the number of the inductors 53 may be set according to actual needs, for example, the number of the inductors 53 is 2, 2 inductors 53 may be connected in series, and in this case, the inductors 53 connected in series may be electrically connected to the first capacitor 51 and the second capacitor 52, respectively.
In addition, in some embodiments, as shown in fig. 1, the connection circuit may further include a voltage regulator 70 and a resistor group 22, and the image chip 21 includes a voltage pin group. The voltage stabilizer 70 is electrically connected to one end of the resistor group 22 through the fourth conductive member 104, and the other end of the resistor group 22 is electrically connected to the voltage pin group.
When voltage stabilizer 70 is electrically connected with one end of resistor group 22, and the other end of resistor group 22 is electrically connected with voltage pin group, at this moment, when voltage stabilizer 70 transmits voltage to image chip 21, voltage can be divided through resistor group 22, thereby it is comparatively suitable to make voltage stabilizer 70 transmit the voltage to image chip 21, make the voltage on the image chip 21 comparatively suitable, be favorable to image chip 21 work.
In addition, in the embodiment of the present invention, as shown in fig. 1, the voltage regulator 70 may be electrically connected to one end of the resistor group 22 through a fourth conductive member 104.
In addition, in some embodiments, the voltage pin set includes a first voltage pin, a second voltage pin and a third voltage pin, and the resistor set 22 includes a first voltage dividing resistor 221, a second voltage dividing resistor 222 and a third voltage dividing resistor 223. A first end of the first voltage dividing resistor 221 is electrically connected to the regulator and the first voltage pin, a second end of the first voltage dividing resistor 221 is electrically connected to a first end of the second voltage dividing resistor 222 and the second voltage pin, a second end of the second voltage dividing resistor 222 is electrically connected to a first end of the third voltage dividing resistor 223 and the third voltage pin, and a second end of the third voltage dividing resistor 223 is grounded.
Since the first end of the first voltage dividing resistor 221 is electrically connected to the regulator and the first voltage pin, respectively, the voltage transmitted by the regulator 70 may be transmitted to the first end of the first voltage dividing resistor 221 and transmitted to the first voltage pin, and then the voltage passes through the first voltage dividing resistor 221, and the first voltage dividing resistor 221 may divide the voltage, so that the voltage at the second end of the first voltage dividing resistor is less than the voltage at the first end of the first voltage dividing resistor 221, and the voltage at the second end of the first voltage dividing resistor 221 is transmitted to the second voltage pin. Then, the second voltage-dividing resistor 222 may divide the voltage of the first voltage-dividing resistor 221, such that the voltage of the first end of the second voltage-dividing resistor 222 is less than the voltage of the second end of the second voltage-dividing resistor 222, and the voltage of the second end of the second voltage-dividing resistor 222 is transmitted to the third voltage pin. Thereby causing the first voltage pin, the second voltage pin, and the third voltage pin on the image chip 21 to have voltages so that the image chip 21 can operate.
For example, as shown in fig. 1, the first voltage dividing resistor 221 may be R4, the second voltage dividing resistor 222 may be R2, the third voltage dividing resistor 223 may be R3, the first voltage pin may be a pin of 2.8V in the image chip 21, the second voltage pin may be a pin of 1.8V in the image chip 21, and the third voltage pin may be a pin of 1.1V in the image chip 21.
In addition, in some embodiments, as shown in fig. 1, the camera module 20 may further include a clock generator 80, and the image chip 21 further includes a clock pin. The clock generator 80 is electrically connected to the clock pin, and the clock generator 80 is configured to send a clock signal to the clock pin.
When the clock generator 80 is electrically connected to the clock pin, the clock generator 80 may transmit a clock signal to the clock pin, so that the image chip 21 may capture an image according to the clock signal or process the image.
For example, as shown in FIG. 1, the clock pin may be pin CLK.
In addition, in the embodiment of the present invention, the clock generator 80 may include any one of a crystal oscillator, a pierce oscillator, and a clock chip.
In addition, in some embodiments, the connection circuit may further include a motherboard 10 and a camera module 20, the motherboard chip 11 is disposed on the motherboard 10, and the image chip 21 is located in the camera module 20. At this time, the main board 10 is electrically connected to the camera module 20, so that the camera module 20 can transmit the captured image to the main board 10.
In addition, when the connection circuit includes the voltage regulator 70, the voltage regulator 70 may be provided on the main board 10 at this time.
In addition, in some embodiments, as shown in fig. 1, a first ground contact 91 may be disposed on the main board 10, a second ground contact 92 is disposed in the camera module 20, and the first ground contact 91 and the second ground contact 92 are electrically connected.
When the first ground contact 91 on the main board 10 is electrically connected with the second ground contact 92 in the camera module 20, at this time, the main board 10 and the camera module 20 can be grounded through the first ground contact 91 on the main board 10, so that the camera module 20 is facilitated to work, and the influence of static electricity on the camera module 20 is avoided.
As shown in fig. 1, the first ground contact 91 and the second ground contact 92 are electrically connected to each other by a fifth conductive member 105.
In addition, in some embodiments, the first conductive member 101 may include a first sub-member and a second sub-member, the second conductive member 102 includes a third sub-member and a fourth sub-member, and the third conductive member 103 includes a fifth sub-member and a sixth sub-member. The first sub-piece, the third sub-piece and the fifth sub-piece are all arranged on the main board 10, and the second sub-piece, the fourth sub-piece and the sixth sub-piece are all arranged on the camera module 20. The first protocol transmission pin is electrically connected to the first sub-part, the fourth protocol transmission pin is electrically connected to the second sub-part, and the first sub-part is electrically connected to the second sub-part. The second protocol transmission pin, the first signal transmission pin and the first reset pin are electrically connected with the third sub-part, the fifth protocol signal transmission pin, the third signal pin and the second reset pin are electrically connected with the fourth sub-part, and the third sub-part is electrically connected with the fourth sub-part. The third protocol transmission pin and the second signal transmission pin are electrically connected to the fifth sub-component, the sixth protocol transmission pin and the fourth signal transmission pin are electrically connected to the sixth sub-component, and the fifth sub-component is electrically connected to the sixth sub-component.
It should be noted that, when the motherboard 10 is connected to the camera module 20, a first connector is usually disposed on the motherboard 10, and a second connector is disposed on the camera module 20, and the motherboard 10 is electrically connected to the camera module 20 through the first connector and the second connector. The first connector usually has a plurality of first pins, the second connector usually has a plurality of second pins, and the number of the first pins is the same as that of the second pins, so that when the first pins contact with the second pins, the camera module 20 can communicate with the motherboard 10. In the embodiment of the present invention, the first sub-component, the third sub-component, and the fifth sub-component may correspond to three first pins in a first connector on the motherboard 10, and the second sub-component, the fourth sub-component, and the sixth sub-component may correspond to three second pins of a second connector on the camera module 20.
In addition, in the embodiment of the present invention, the fourth conductive member 104 may include a seventh sub-member and an eighth sub-member, the fifth conductive member 105 may include a ninth sub-member and a tenth sub-member, the seventh sub-member and the ninth sub-member may be disposed on the main board 10, and the eighth sub-member and the tenth sub-member may be disposed on the camera module 20, in which case, the seventh sub-member and the ninth sub-member may correspond to two pins in the first connector on the main board 10, and the eighth sub-member and the tenth sub-member may correspond to two pins in the second connector on the camera module 20.
In addition, in the embodiment of the present invention, the main board 10 and the camera module 20 communicate via the CPHY protocol, and the number of the conductive members is reduced by multiplexing the signal paths, which is equivalent to reducing the number of the first pins in the first connector on the main board 10 and reducing the number of the second pins in the second connector on the camera module 20. In addition, in the embodiment of the present invention, actually, the first connector on the motherboard 10 has 5 first pins, and the second connector on the camera module 20 has 5 pins, so that the motherboard chip 11 can communicate with the image chip 21.
In the embodiment of the present invention, since the first protocol transmission pin and the fourth protocol transmission pin are electrically connected through the first conductive member 101, the second protocol transmission pin and the fifth protocol transmission pin are electrically connected through the second conductive member 102, and the third protocol transmission pin and the sixth protocol transmission pin are electrically connected through the third conductive member 103, signals can be transmitted between the first protocol transmission pin and the fourth protocol transmission pin, between the second protocol transmission pin and the fifth protocol transmission pin, and between the third protocol transmission pin and the sixth protocol transmission pin. Because the first signal transmission pin and the first reset pin are electrically connected to the second conductive member 102, and the third signal pin and the second reset pin are electrically connected to the second conductive member 102, the signal transmission path of the first signal transmission pin, the first reset pin and the second protocol signal multiplexing second protocol transmission pin is equivalent, and the signal transmission path of the second protocol transmission pin is also multiplexed by the third signal pin and the second reset pin. In addition, the second signal transmission pin is electrically connected to the third conductive member 103, and the fourth signal pin is electrically connected to the third conductive member 103, which is equivalent to the third signal pin multiplexing the signal transmission path of the third protocol transmission pin, and the fourth signal pin multiplexing the signal transmission path of the fourth protocol transmission pin. That is, in the embodiment of the present invention, the number of pins can be reduced by multiplexing the signal transmission paths.
An embodiment of the present invention provides an electronic device, which includes the connection circuit in any of the above embodiments.
It should be noted that, in the embodiment of the present invention, the electronic device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted terminal, a wearable device, a pedometer, and the like.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
While alternative embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including alternative embodiments and all such alterations and modifications as fall within the true scope of the embodiments of the utility model.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like may be used solely to distinguish one entity from another entity without necessarily requiring or implying any actual such relationship or order between such entities. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or terminal apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or terminal apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or terminal device comprising the element.
While the technical solutions provided by the present invention have been described in detail, the principles and embodiments of the present invention are described herein by using specific examples, and meanwhile, for a person of ordinary skill in the art, according to the principles and implementation manners of the present invention, changes may be made in the specific embodiments and application ranges.
Claims (10)
1. A connection circuit, comprising: a motherboard chip and an image chip;
the mainboard chip is provided with a first protocol transmission pin, a second protocol transmission pin, a third protocol transmission pin, a first signal transmission pin, a second signal transmission pin and a first reset pin; the image chip is provided with a fourth protocol transmission pin, a fifth protocol transmission pin, a sixth protocol transmission pin, a third signal transmission pin, a fourth signal transmission pin and a second reset pin;
the first protocol transmission pin is electrically connected with the fourth protocol transmission pin, the second protocol transmission pin is electrically connected with the fifth protocol transmission pin, and the third protocol transmission pin is electrically connected with the sixth protocol transmission pin;
the first signal transmission pin and the first reset pin are electrically connected to the second protocol transmission pin, the second signal transmission pin is electrically connected to the third protocol transmission pin, the third signal pin and the second reset pin are electrically connected to the fifth protocol transmission pin, and the fourth signal pin is electrically connected to the sixth protocol transmission pin.
2. The connection circuit according to claim 1, further comprising a first voltage converter and a second voltage converter;
the first signal pin, the second signal pin and the first reset pin are electrically connected to a first end of the first voltage converter, and a second end of the first voltage converter is electrically connected to the second protocol transmission pin and the third protocol transmission pin;
the third signal pin, the fourth signal pin and the second reset pin are electrically connected to a first end of the second voltage converter, and a second end of the second voltage converter is electrically connected to the fifth protocol transmission pin and the sixth protocol transmission pin;
the first voltage converter is used for converting a first voltage into a second voltage, and the second voltage converter is used for converting the second voltage into the first voltage;
wherein the first voltage is greater than the second voltage.
3. The connection circuit according to claim 2, wherein the connection circuit further comprises a first impedance matcher and a second impedance matcher;
a first end of the first impedance matcher is electrically connected with a second end of the first voltage converter, and the second end of the first impedance matcher is electrically connected to the second protocol transmission pin and the third protocol transmission pin respectively;
a first end of the second impedance matcher is electrically connected with a second end of the second voltage converter, and second ends of the second impedance matcher are respectively and electrically connected to the fifth protocol transmission pin and the sixth protocol transmission pin;
the first impedance matcher and the second impedance matcher are used for adjusting impedance in the connecting circuit.
4. The connection circuit of claim 3, wherein the first impedance matcher comprises a first capacitor, a second capacitor and an inductor;
a first end of the inductor is electrically connected with a first end of the first capacitor and a second end of the first voltage converter respectively, and a second end of the first capacitor is grounded;
the second end of the inductor is electrically connected with the first end of the second capacitor, the second protocol transmission pin and the third protocol transmission pin respectively.
5. The connection circuit according to claim 1, wherein the connection circuit further comprises a voltage regulator and a resistor group, the image chip comprises a voltage pin group;
the voltage stabilizer is electrically connected with one end of the resistor group, and the other end of the resistor group is electrically connected with the voltage pin group.
6. The connecting circuit of claim 5, wherein the voltage pin set comprises a first voltage pin, a second voltage pin, and a third voltage pin, and the resistor set comprises a first voltage dividing resistor, a second voltage dividing resistor, and a third voltage dividing resistor;
a first end of the first voltage dividing resistor is electrically connected to the voltage stabilizer and the first voltage pin, a second end of the first voltage dividing resistor is electrically connected to a first end of the second voltage dividing resistor and the second voltage pin, a second end of the second voltage dividing resistor is electrically connected to a first end of the third voltage dividing resistor and the third voltage pin, and a second end of the third voltage dividing resistor is grounded.
7. The connecting circuit of claim 1, wherein the camera module comprises a clock generator, and the image chip further comprises a clock pin;
the clock generator is electrically connected with the clock pin and used for sending a clock signal to the clock pin.
8. The connecting circuit according to any one of claims 1-7, wherein the connecting circuit further comprises a motherboard and a camera module;
the mainboard chip is arranged on the mainboard, and the image chip is located in the camera module.
9. The connecting circuit according to claim 8, wherein a first ground contact is disposed on the main board, a second ground contact is disposed in the camera module, and the first ground contact and the second ground contact are electrically connected.
10. An electronic device, characterized in that the electronic device comprises the connection circuit of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122984239.5U CN216623243U (en) | 2021-11-30 | 2021-11-30 | Connection circuit and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122984239.5U CN216623243U (en) | 2021-11-30 | 2021-11-30 | Connection circuit and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216623243U true CN216623243U (en) | 2022-05-27 |
Family
ID=81699491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122984239.5U Active CN216623243U (en) | 2021-11-30 | 2021-11-30 | Connection circuit and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216623243U (en) |
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2021
- 2021-11-30 CN CN202122984239.5U patent/CN216623243U/en active Active
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