CN216597559U

CN216597559U - Electronic package

Info

Publication number: CN216597559U
Application number: CN202220209202.7U
Authority: CN
Inventors: 赖昶均; 谢孟晃; 许铭钦; 贺政浩; 胡峻荣; 黄宇中
Original assignee: Qingdao New Core Technology Co ltd
Current assignee: Qingdao New Core Technology Co ltd
Priority date: 2022-01-25
Filing date: 2022-01-25
Publication date: 2022-05-24
Anticipated expiration: 2032-01-25

Abstract

The utility model relates to an electronic packaging part, including using single seed crystal layer preparation circuit portion, carry out rewiring circuit layer processing procedure again in this circuit portion to after chip package, need not to carry out extra course of working, can directly carry out the ball planting operation in this circuit portion, so can save the processing procedure cost by a wide margin.

Description

Electronic package

Technical Field

The present application relates to semiconductor packages, and more particularly, to an electronic package suitable for organic fan-out packaging.

Background

With the development of Semiconductor packaging technology, different Package types have been developed for Semiconductor devices (Semiconductor devices), and in order to improve electrical functions and save Package space, different three-dimensional packaging technologies, such as Fan-Out Package on Package (FO PoP) and the like, have been developed to integrate integrated circuits with different functions into a single Package structure, so as to achieve system integration through a stack design, and are suitable for application to light and thin electronic products.

In the conventional semiconductor package, a semiconductor chip is bonded to a package substrate through a plurality of solder bumps, and then the semiconductor chip is encapsulated by a molding compound.

In the conventional semiconductor package, in order to fabricate the electrical contact pad for ball-mounting on the circuit portion above the dielectric layer of the dielectric body with no pattern on the whole surface, the subsequent ball-mounting operation can be performed usually by drilling a hole through the barrier layer of the metal structure by laser to expose the copper material of the electrical contact pad; alternatively, instead of fabricating a dielectric without patterns, a separate electrical contact pad is fabricated, wherein the electrical contact pad produced by the process comprises at least two seed layers, and after the package is fabricated, the bottom barrier layer is removed by wet process or grinding process to perform ball-planting operation.

However, the laser drilling equipment is expensive, so that the manufacturing cost of the semiconductor package is difficult to reduce, and the laser needs to drill through various materials (such as the PI material of the dielectric layer and the titanium material of the metal structure), so that the hole shape is not good, and the solder ball is not easy to be combined in the hole and is easy to fall off; in another process, a step of removing the metal structure that cannot be subjected to the ball-mounting operation at the bottom layer is additionally required, so that the production period is prolonged and the production cost is increased.

Therefore, how to overcome the various problems of the prior art has become an issue to be solved.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks of the prior art, the present application provides an electronic package that can save the manufacturing cost.

The electronic package of the present application includes: a dielectric layer having opposing first and second sides; an electrical contact pad formed on the first side of the dielectric layer, wherein the electrical contact pad is composed of a seed layer and a conductive layer formed on the seed layer, and the surface of the seed layer is flush with the surface of the first side; a circuit portion formed on the second side of the dielectric layer opposite to the first side and electrically connected to the electrical contact pad; and an electronic element arranged on the second side of the dielectric layer and electrically connected with the circuit part.

In the electronic package, the circuit portion is electrically connected to the electrical contact pad through the conductive via.

In the electronic package, the circuit portion includes a metal structure and a circuit layer formed on the metal structure. For example, the metal structure includes a barrier layer and another seed layer.

In the electronic package, a plurality of metal bumps are formed on the circuit portion, so that the plurality of metal bumps are electrically connected to the circuit portion, and the electronic component is connected to the plurality of metal bumps through a plurality of conductive structures. For example, an under bump metal layer is formed on the circuit portion to bond the plurality of metal bumps. Alternatively, the conductive structure includes a post for bonding the electronic component and a solder material for bonding the post and the metal bump.

In the electronic package, the seed layer of the electrical contact pad has only one layer and is made of a single metal material.

In the electronic package, the electronic package further includes a plurality of conductive elements coupled to the plurality of electrical contact pads.

In the electronic package, the electronic package further includes a cladding layer formed on the dielectric layer to clad the electronic element.

In view of the above, in the electronic package of the present application, the electrical contact pad is formed on the carrier, the dielectric layer is formed, and a single seed layer is used to form the electrical contact pad, therefore, the seed crystal layer is not required to be matched with the existing barrier layer (or adhesive layer) and other films, so that after the carrier is removed, the electrical contact pad can be exposed for direct ball mounting without laser drilling, so compared with the prior art, the electronic package of the present application does not need to use laser drilling equipment to drill the electrical contact pad or extra wet/grinding process to remove the barrier layer (or adhesive layer) on the electrical contact pad, therefore, the manufacturing cost can be greatly reduced, and the surface smoothness of the electrical contact pad can be kept because holes are not required to be manufactured, so that the bonding of the solder balls (namely the conductive elements) is facilitated and the conductive elements are not easy to fall off.

Drawings

Fig. 1A to 1D are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to the present application.

FIG. 2A is a schematic partial cross-sectional view of another process of FIG. 1A.

Fig. 2B is a partially enlarged cross-sectional view of fig. 1B.

FIG. 2C is a schematic partial cross-sectional view of another process of FIG. 1B.

Fig. 2D is a schematic cross-sectional view of an electronic package of the present application in a subsequent application.

Fig. 3A, 3B and 3C are partially enlarged bottom views of fig. 2D.

Description of the reference numerals

2: circuit board

3: electronic package

3a line part

30,33b seed layer

31 conductive layer

310 electric contact pad

32 dielectric layer

32a first side

32b second side

320, opening a hole

33 metal structure

33a barrier layer

34 circuit layer

340 conductive blind hole

35 insulating protective layer

350 opening of the container

36 metal bump

360 metal layer under bump

4a conductive structure

40 electronic component

40a acting surface

40b non-active surface

400 electrode pad

41 coating layer

42 conductive element

43 solder material

44 column body

8: glass plate

80,90 releasing layer

9 bearing plate

And S, cutting a path.

Detailed Description

The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein.

It should be understood that the structures, ratios, sizes, and the like shown in the drawings are only used for matching with the disclosure of the specification to provide understanding and reading for those skilled in the art, and are not used to limit the practical limit conditions of the present application, so they have no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the present disclosure without affecting the efficacy and achievable purpose of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present application, and changes or modifications of the relative relationship may be made without substantial technical changes.

Fig. 1A to 1D are schematic cross-sectional views illustrating a manufacturing method of an electronic package 3 according to the present application.

As shown in fig. 1A, an electrical contact pad 310 is formed on a carrier 9, a dielectric layer 32 is formed on the carrier 9, and the dielectric layer 32 is formed with at least one opening 320 exposing a portion of the electrical contact pad 310.

In the present embodiment, the carrier 9 is a metal plate, a semiconductor wafer or a glass plate, such as a temporary full-surface silicon wafer (Si wafer), on which a release layer 90 or other temporary bonding material is disposed, such that the electrical contact pads 310 and the dielectric layer 32 are formed on the release layer 90.

The electrical contact pad 310 includes a seed layer 30 and a conductive layer 31 formed on the seed layer 30. For example, a seed layer 30 made of a single metal material (e.g., copper) is formed on the entire surface of the releasing layer 90, a conductive layer 31 is formed on a portion of the surface of the seed layer 30 by a patterning process, and finally, an unnecessary portion is removed to form a patterned electrical contact pad 310. Since the seed layer 30 is formed on the releasing layer 90, the existing barrier layer (or adhesion layer) film is not needed under the seed layer 30.

In addition, the dielectric layer 32 is made of an organic material (which may be photosensitive or non-photosensitive), such as poly-benzoxazole (PBO), Polyimide (PI), Prepreg (PP), or other organic insulating dielectric material, and the opening 320 may be a hole with a uniform aperture width (as shown in fig. 1A) or a tapered hole with a tapered aperture width (as shown in fig. 2A).

As shown in fig. 1B, a Redistribution Layer (RDL) process is performed on the dielectric Layer 32 to form a circuit portion 3 a. Wherein a portion of the circuit portion 3a is electrically connected to the electrical contact pad 310.

In the present embodiment, a portion of the circuit portion 3a has a plurality of conductive vias 340 formed in the opening 320 for electrically connecting the electrical contact pad 310, and the circuit portion 3a includes a metal structure 33 and a circuit layer 34 formed on the metal structure 33. For example, a barrier layer (or adhesion layer) 33a and a copper seed layer 33B are sequentially formed on the dielectric layer 32, as shown in fig. 2B, to serve as the metal structure 33, the circuit layer 34 is formed on a portion of the surface of the metal structure 33 by a patterning process, and then the metal structure 33 on which the circuit layer 34 is not formed is removed to form a patterned circuit as the circuit portion 3a, wherein the material forming the barrier layer 33a may be titanium (Ti), titanium/Tungsten (TiW), tantalum (Ta) or other suitable materials.

Furthermore, a plurality of layers of circuit portions 3a may be formed on the electrical contact pads 310 as required. In addition, a solder mask such as green paint can be formed on the outermost dielectric layer 32 and the circuit portion 3a as the insulating protection layer 35 (the material of the solder mask can also be the same as that of the dielectric layer 32), and the insulating protection layer 35 is formed with at least one opening 350 to expose a portion of the surface of the outermost circuit portion 3 a.

Alternatively, the opening 350 may be a hole with a uniform aperture width (as shown in FIG. 1B) or a cone with a tapered aperture width (as shown in FIG. 2C).

As shown in fig. 1C, metal bumps 36 are formed on the circuit portion 3a in each opening 350, so that each metal bump 36 is electrically connected to the circuit portion 3a, and an electronic component 40 is mounted on each metal bump 36 through a plurality of conductive structures 4a to be electrically connected to the circuit portion 3 a. Next, a coating 41 is formed on the dielectric layer 32 (or the insulating protection layer 35) so that the coating 41 covers the electronic element 40.

In the present embodiment, the electronic component 40 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, and an inductor, or a combination thereof. For example, the electronic component 40 is a semiconductor chip having an active surface 40a and an inactive surface 40b opposite to each other, the active surface 40a has a plurality of electrode pads 400, so that the electronic component 40 is bonded to the metal bumps 36 through the conductive structures 4a by the electrode pads 400.

Furthermore, an Under Bump Metallurgy (UBM) 360 may be formed on the circuit portion 3a as required to facilitate bonding the metal Bump 36, and the conductive structure 4a includes a pillar 44 bonded to the electrode pad 400 and a solder material 43 bonded to the pillar 44. For example, the pillar 44 may be a metal pillar containing copper, copper/nickel (Cu/Ni)/, copper/nickel/copper (Cu/Ni/Cu), and the solder material 43 may be a tin-silver alloy (SnAg) so that the pillar 44 is bonded to the metal bump 36 via the solder material 43, wherein the under bump metal layer 360 is formed in the opening 350 of the insulating passivation layer 35 to contact the wiring portion 3a in the opening 350.

It should be noted that, in addition to the conductive structure 4a, the electronic component 40 can also be electrically connected to the circuit portion 3a directly through a post 44 or a conventional technical means in the art, without being limited to the connection structure shown in fig. 1C.

The coating layer 41 is an insulating material, such as Polyimide (PI), dry film (dry film), and molding compound (molding compound) such as epoxy resin (epoxy). For example, the process of the cladding layer 41 may be selected from liquid compound (liquid compound), spraying (injection), pressing (laminating), molding (compression molding), etc. to form on the dielectric layer 32 (or the insulating protection layer 35).

In addition, the cladding layer 41 can clad the conductive structure 4a and the metal bump 36. Alternatively, an underfill (not shown) is first formed between the active surface 40a of the electronic component 40 and the dielectric layer 32 (or the insulating protection layer 35) to encapsulate the conductive structure 4a and the metal bump 36, and then the underfill is encapsulated by the encapsulating layer 41.

As shown in fig. 1D, the carrier 9 and the releasing layer 90 thereon are removed to expose the electrical contact pad 310, and the surface of the electrical contact pad 310 is flush with the lower surface of the dielectric layer 32. Next, a singulation process is performed along a dicing path S shown in fig. 1C to obtain a plurality of electronic packages 3.

In the present embodiment, after removing the carrier 9 and the releasing layer 90 thereon, the ball-planting operation can be directly performed on the electrical contact pad 310 with the single seed layer 30 without further processing, so as to assist the metal melting condition on the electrical contact pad 310, and then perform the ball-planting process, that is, a plurality of conductive elements 42, such as copper pillars, solder balls (solder balls) or other solder structures, are formed on the metal contact (the electrical contact pad 310), so that in the subsequent process, the electronic package 3 can be disposed on a circuit board 2 through the conductive elements 42, as shown in fig. 2D. For example, the electrical contact pads 310 may be formed in various shapes (e.g., circular as shown in fig. 3A, regular hexagonal as shown in fig. 3B, regular octagonal as shown in fig. 3C, or other shapes) as desired to effectively couple with the conductive elements 42.

Furthermore, the surface of the electrical contact pad 310 where the ball is embedded and the surface of the dielectric layer 32 are located on the same horizontal plane, so as to dispose the conductive element 42 by using a planar ball embedding method.

Therefore, in the manufacturing method of the present application, the electrical contact pad 310 is formed on the releasing layer 90 of the carrier 9, the dielectric layer 32 is then manufactured, and the single seed crystal layer 30 is used to manufacture the electrical contact pad 310, so that the electrical contact pad 310 can be exposed without matching the existing barrier layer (or adhesion layer) and other films under the seed crystal layer 30 after the carrier 9 and the releasing layer 90 are removed, for performing ball-planting operation directly, without performing laser drilling or wet process, therefore, compared with the prior art, the electronic package 3 of the present application does not need to use laser drilling equipment to drill the electrical contact pad 310 or remove the barrier layer (or adhesion layer) and other films through the wet process before ball-planting operation, thereby greatly reducing the manufacturing cost, and because the hole making or the barrier layer (or adhesion layer) removing process by wet process is not needed, the surface integrity of the electrical contact pad 310 can be maintained to facilitate bonding of the conductive element 42 without easy detachment.

The present application also provides an electronic package 3, comprising: at least one dielectric layer 32, electrical contact pads 310, circuit portions 3a, metal bumps 36, and at least one electronic component 40.

The dielectric layer 32 has a first side 32a and a second side 32b opposite to each other.

The electrical contact pad 310 is formed on the first side 32a of the dielectric layer 32, wherein the electrical contact pad 310 is composed of a seed layer 30 and a conductive layer 31 formed on the seed layer 30, and the surface of the seed layer 30 is flush with the surface of the first side 32 a.

The circuit portion 3a is formed on a second side 32b of the dielectric layer 32 opposite to the first side 32a and electrically connected to the electrical contact pad 310.

The electronic component 40 is disposed on the second side 32b of the dielectric layer 32 and electrically connected to the circuit portion 3 a. A coating layer 41 is formed on the dielectric layer 32 to coat the electronic device 40.

In one embodiment, the circuit portion 3a is electrically connected to the electrical contact pad 310 through a plurality of conductive vias 340.

In one embodiment, the circuit portion 3a includes a metal structure 33 and a circuit layer 34 formed on the metal structure 33. For example, the metal structure 33 includes a barrier layer 33a and another seed layer 33 b.

In one embodiment, a plurality of metal bumps 36 are formed on the circuit portion 3a, such that the plurality of metal bumps 36 are electrically connected to the circuit portion 3a, and the electronic component 40 is mounted on the plurality of metal bumps 36 through a plurality of conductive structures 4 a. Wherein, an under bump metal layer 360 is formed on the circuit portion 3a for combining with the metal bump 36. Alternatively, the conductive structure 4a includes a post 44 for bonding the electronic component 40 and a solder material 43 for bonding the post 44 and the metal bump 36.

In one embodiment, the seed layer 30 of the electrical contact pad 310 has only one layer and is made of a single metal material.

In one embodiment, the plurality of electrical contact pads 310 are exposed from the dielectric layer 32. For example, the electronic package 3 may include a plurality of conductive elements 42 coupled to the plurality of electrical contact pads 310.

In one embodiment, a surface of the electrical contact pad 310 is flush with the outermost surface of the dielectric layer 32.

In summary, the electronic package of the present application uses a single seed layer when manufacturing the electrical contact pad, so that the electrical contact pad can be exposed without matching with the existing films such as the barrier layer (or the adhesive layer) under the seed layer after the carrier board is removed, and the ball-mounting operation can be directly performed without performing the laser drilling or the wet process.

The above-described embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be as set forth in the claims.

Claims

1. An electronic package, comprising:

a dielectric layer having opposing first and second sides;

an electrical contact pad formed on the first side of the dielectric layer, wherein the electrical contact pad is composed of a seed layer and a conductive layer formed on the seed layer, and the surface of the seed layer is flush with the surface of the first side;

a circuit portion formed on the second side of the dielectric layer opposite to the first side and electrically connected to the electrical contact pad; and

and the electronic element is arranged on the second side of the dielectric layer and is electrically connected with the circuit part.

2. The electronic package according to claim 1, wherein the circuit portion is electrically connected to the electrical contact pad through a conductive via.

3. The electronic package according to claim 1, wherein the circuit portion comprises a metal structure and a circuit layer formed on the metal structure.

4. The electronic package of claim 3, wherein the metal structure comprises a barrier layer and another seed layer.

5. The electronic package according to claim 1, wherein a plurality of metal bumps are formed on the circuit portion, such that the plurality of metal bumps are electrically connected to the circuit portion, and the electronic component is mounted on the plurality of metal bumps through a plurality of conductive structures.

6. The electronic package according to claim 5, wherein an under bump metal layer is formed on the circuit portion to bond the plurality of metal bumps.

7. The electronic package according to claim 5, wherein the conductive structure comprises a post for bonding the electronic component and solder for bonding the post and the metal bump.

8. The electronic package of claim 1, wherein the seed layer of the electrical contact pad has only one layer and is formed of a single metal material.

9. The electronic package according to claim 1, further comprising a plurality of conductive elements associated with the plurality of electrical contact pads.

10. The electronic package according to claim 1, further comprising a cladding layer formed on the dielectric layer to encapsulate the electronic device.