CN216565119U

CN216565119U - Key circuit and development board

Info

Publication number: CN216565119U
Application number: CN202122436356.8U
Authority: CN
Inventors: 李冰; 王广军; 王磊; 陈晓彤
Original assignee: Contec Medical Systems Co Ltd
Current assignee: Contec Medical Systems Co Ltd
Priority date: 2021-10-09
Filing date: 2021-10-09
Publication date: 2022-05-17
Anticipated expiration: 2031-10-09

Abstract

The utility model provides a key circuit and a development board, wherein the key circuit comprises: the basic circuit comprises n (n is more than or equal to 2), and each basic circuit comprises an IO port and a basic key which are electrically connected in sequence; the free end of the basic key is grounded; the expansion circuit comprises a plurality of expansion circuits, and each expansion circuit comprises a diode group and an expansion key; the input ends of the diode groups comprise k (k is more than or equal to 2 and less than or equal to n), the input ends are electrically connected with the IO ports with the corresponding number, the output ends of the diode groups are electrically connected with the expansion keys, and the free ends of the expansion keys are grounded; the number b of the expansion keys meets the following conditions: b is more than or equal to 1 and less than or equal to 2ⁿ-n-1. To address IO ports on embedded development boards in the prior artThe utility model realizes the purpose of scanning the most keys as far as possible by using the least IO ports and improves the utilization rate of the IO ports of the embedded development board when the keys are scanned.

Description

Key circuit and development board

Technical Field

The utility model relates to the technical field of electronic circuits, in particular to a key circuit and a development board.

Background

In actual work, when the embedded development board is used for project design, a relatively large number of keys are often used, but the number of the IO port ports of the chip of the embedded development board is limited, so that the existing designers only try to save the IO ports in other modules. Even so, it is not easy to save one or two IO ports, and the requirement of the number of keys may not be met.

The existing mode mostly adopts a matrix keyboard mode to scan keys, and the key scanning capability of a matrix key circuit is as follows: 3 IO ports can scan 2 buttons at most, 4 IO ports can scan 4 buttons at most, and 5 IO ports can scan 6 buttons at most. Therefore, the number of keys swept by the IO port on the existing embedded development board is small.

Therefore, how to scan the most keys as much as possible by using the least IO ports is a problem to be solved when an embedded development board is used for project design.

SUMMERY OF THE UTILITY MODEL

The utility model provides a key circuit and a development board, which are used for solving the defect that the number of scanned keys of an IO port on an embedded development board is small in the prior art, realizing that the most keys are scanned as much as possible by using the least IO port and improving the utilization rate of the IO port of the embedded development board when the keys are scanned.

The utility model provides a key circuit, comprising:

the basic circuit comprises n (n is more than or equal to 2), and each basic circuit comprises an IO port and a basic key which are electrically connected in sequence; the free end of the basic key is grounded; and

the expansion circuit comprises a plurality of expansion circuits, and each expansion circuit comprises a diode group and an expansion key; the input ends of the diode groups comprise k (k is more than or equal to 2 and less than or equal to n), the input ends are electrically connected with the IO ports with corresponding quantity, the output ends of the diode groups are electrically connected with the expansion keys, and the free ends of the expansion keys are grounded;

the number b of the expansion keys meets the following conditions: b is more than or equal to 1 and less than or equal to 2ⁿ-n-1。

According to the key circuit provided by the utility model, the number of the basic circuit and the number of the IO ports are respectively 4, and the expansion circuit comprises a first expansion circuit; the diode group in the first extension circuit comprises a first diode and a second diode, and cathodes of the first diode and the second diode are electrically connected with each other;

the anode of the first diode and the anode of the second diode are electrically connected with two of the four IO ports correspondingly;

the number b1 of the first extension circuits satisfies the following condition

According to the key circuit provided by the utility model, the expansion circuit further comprises a second expansion circuit; the diode group in the second expansion circuit comprises a third diode, a fourth diode and a fifth diode, wherein cathodes of the third diode, the fourth diode and the fifth diode are electrically connected with each other;

the anode of the third diode, the anode of the fourth diode and the anode of the fifth diode are electrically connected with three of the four IO ports correspondingly;

the number b2 of the second expansion circuits satisfies the following condition

According to the key circuit provided by the utility model, the expansion circuit further comprises a third expansion circuit; the diode group in the third extension circuit comprises a sixth diode, a seventh diode, an eighth diode and a ninth diode, the cathodes of which are electrically connected with each other;

and the anode of the sixth diode, the anode of the seventh diode, the anode of the eighth diode and the anode of the ninth diode are electrically connected with the four IO ports correspondingly.

According to the key circuit provided by the utility model, the first diode and the second diode form a common cathode Schottky diode.

According to the key circuit provided by the utility model, the third diode and the fourth diode form a common cathode Schottky diode; and the fifth diode is a Schottky diode single tube.

According to the key circuit provided by the utility model, the sixth diode and the seventh diode form a common cathode Schottky diode; the eighth diode and the ninth diode constitute a common cathode schottky diode.

According to the key circuit provided by the utility model, the basic key and the expansion key are respectively connected with the transient diode in parallel.

According to the key circuit provided by the utility model, the buffer resistor is electrically connected between the output end of the diode group and the extension key.

The utility model also provides a development board which comprises the key circuit.

According to the key circuit and the development board provided by the utility model, a plurality of expansion circuits are arranged, and each expansion circuit comprises a diode group and an expansion key; the input end of the diode group comprises k (k is more than or equal to 2 and less than or equal to n), the k input ends of the diode group are respectively electrically connected with the IO ports in corresponding quantity, and key scanning is carried out by utilizing a plurality of IO ports to correspond to one expansion key, so that the number of key scanning is increased by fully utilizing the plurality of IO ports, the utilization rate of the IO ports of the embedded development board during key scanning is increased, and the defect that the number of keys of the IO ports on the embedded development board in the prior art is less is overcome.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a key circuit according to the present invention;

FIG. 2 is a second schematic diagram of the key circuit according to the present invention;

FIG. 3 is a third schematic diagram of the key circuit according to the present invention;

FIG. 4 is a fourth schematic diagram of the key circuit according to the present invention.

Reference numerals:

10: basic circuit	20: expansion circuit	11: IO port
			12: basic key	13: pull-up resistor	21: diode group
22: extension key	211: first diode	212: second diode
			213: third diode	214: fourth diode	215: fifth diode
216: sixth diode	217: seventh diode	218: eighth diode
			219: ninth diode	30: transient diode	40: buffer resistor
201: first expander circuit	202: second expander circuit	203: third expansion circuit
			100: key circuit

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The existing mode mostly adopts a matrix keyboard mode to scan keys, and the key scanning capability of a matrix key circuit is as follows: 3 IO ports can scan 2 buttons at most, 4 IO ports can scan 4 buttons at most, and 5 IO ports can scan 6 buttons at most. It can be seen that the number of scan keys of the IO port on the existing embedded development board is small.

In view of this, the utility model provides a key circuit and a development board, which solve the defect of the prior art that the number of scanned keys of an IO port on an embedded development board is small, realize that the most keys are scanned as much as possible by using the fewest IO ports, and improve the utilization rate of the IO port of the embedded development board when the keys are scanned.

The utility model is characterized in that a plurality of expansion circuits are arranged, and each expansion circuit comprises a diode group and an expansion key; the input ends of the diode groups comprise k (k is more than or equal to 2 and less than or equal to n), the k input ends of the diode groups are respectively electrically connected with the IO ports with corresponding quantity, so that a plurality of IO ports are fully utilized for key scanning, the number of key scanning is increased, the utilization rate of the IO ports of the embedded development board during key scanning is increased, and the defect that the number of keys scanning of the IO ports on the embedded development board in the prior art is small is overcome.

The key circuit of the present invention is described below with reference to fig. 1 to 4.

The key circuit 100 of the embodiment of the utility model comprises: a base circuit 10 and an expansion circuit 20.

The circuit comprises basic circuits 10, wherein the basic circuits 10 comprise n (n is more than or equal to 2), and each basic circuit 10 comprises an IO port 11 and a basic key 12 which are electrically connected in sequence; the free end of the base key 12 is grounded. That is, the number of the IO ports 11 and the number of the basic keys 12 in each basic circuit 10 are in a one-to-one correspondence relationship, and each basic circuit 10 includes one basic key 12 and one IO port 11.

In each of the basic circuits 10, when the basic key 12 is not pressed, the IO port 11 is normally at a high level corresponding to the level state. Each of the basic circuits 10 is also electrically connected with a pull-up resistor 13. The pull-up resistor 13 ensures that the IO port 11 is high without a key press. The pull-up resistor 13 has a resistance value in the range of 50K-300K ohms. Preferably, the pull-up resistor 13 has a resistance of 100K ohms.

A plurality of expansion circuits 20, wherein each expansion circuit 20 comprises a diode group 21 and an expansion key 22; the input ends of the diode group 21 include k (k is greater than or equal to 2 and less than or equal to n), the input ends are electrically connected with the corresponding number of IO ports 11, the output ends of the diode group 21 are electrically connected with the expansion keys 22, and the free ends of the expansion keys 22 are grounded.

The number b of the expansion keys 22 satisfies the following condition: b is more than or equal to 1 and less than or equal to 2ⁿ-n-1。

In each expansion circuit 20 of the present embodiment, each expansion key 22 corresponds to k (2 ≦ k ≦ n) IO ports 11. And k is at least greater than two. That is, each expansion key 22 corresponds to at least two IO ports 11, and one expansion key 22 may correspond to at most all of the n IO ports 11.

It is understood that the number of IO ports 11 connected to the input terminal of the diode group 21 in each expansion circuit 20 may be the same or different, and thus the number of IO ports 11 corresponding to the expansion key 22 in each expansion circuit 20 may be the same or different.

When the number of IO ports 11 connected to the input terminals of the diode group 21 in each expansion circuit 20 is the same, the IO ports 11 corresponding to each expansion circuit 20 may be combined in various ways. For example, when the number of the IO ports 11 is 4, the IO ports 11 include GPIO-1, GPIO-2, GPIO-3, GPIO-4. When the input end of the diode group 21 comprises two input ends, the input ends of the diode group 21 can be correspondingly electrically connected with the GPIO-1 and the GPIO-2; (GPIO-1, GPIO-3); (GPIO-2, GPIO-3); (GPIO-1, GPIO-4); (GPIO-2, GPIO-4); (GPIO-3, GPIO-4)6 combinations of IO ports 11. Therefore, when the input terminals of the diode group 21 include two input terminals, the number of the extension circuits 20 and the extension keys 22 is 6 at most.

And the number of IO ports 11 to which the input terminals of the diode group 21 in each of the expansion circuits 20 are connected may also be different. For example, on the basis that the input terminal of the diode group 21 includes two input terminals, the input terminal of the diode group 21 in the expansion circuit 20 may further include three and more input terminals. The expansion keys 22 in the expansion circuit 20 correspond to three and more inputs. When the diode group 21 in each expansion circuit 20 includes all the input terminals of 2 to 4, the number of the expansion circuits 20 and the expansion keys 22 is 2 at this time⁴-4-1 ═ 11.

In other embodiments, when there are 3 IO ports, the number b of the expansion keys 22 satisfies the following condition: b is more than or equal to 1 and less than or equal to 2³-3-1; i.e. the number of expansion keys 22 is at most 4. When there are 5 IO ports, the number b of the expansion keys 22 satisfies the following condition: b is more than or equal to 1 and less than or equal to 2⁵-5-1; i.e. the maximum number of expansion keys 2226. When there are 6 IO ports, the number b of the expansion keys 22 satisfies the following condition: b is more than or equal to 1 and less than or equal to 2⁶-6-1; i.e. the number of expansion keys 22 is at most 57.

According to the key circuit provided by the utility model, a plurality of expansion circuits 20 are arranged, and each expansion circuit 20 comprises a diode group 21 and an expansion key 22; the input end of the diode group 21 comprises k (k is more than or equal to 2 and less than or equal to n), the k input ends of the diode group 21 are respectively electrically connected with the IO ports 11 with corresponding quantity, and key scanning is carried out by utilizing the expansion keys 22 corresponding to the IO ports 11, so that the IO ports 11 are fully utilized, the key scanning number is increased, the utilization rate of the IO ports 11 of the embedded development board during key scanning is increased, and the defect that the number of the keys for scanning the IO ports 11 on the embedded development board is small in the prior art is overcome.

Referring to fig. 1, on the basis of the above embodiments, as an alternative embodiment, the present invention is described below by using a case that the basic circuit 10 and the IO port 11 both include 4.

The IO ports 11 comprise GPIO-1, GPIO-2, GPIO-3 and GPIO-4.

The expansion circuit 20 includes a first expansion circuit 201; the diode group 21 in the first expander circuit 201 includes a first diode 211 and a second diode 212 whose cathodes are electrically connected to each other; the anode of the first diode 211 and the anode of the second diode 212 are electrically connected to two of the four IO ports 11 corresponding to the IO ports 11.

Specifically, the anode of the first diode 211 and the anode of the second diode 212 are electrically connected to two of the four IO ports 11 corresponding to the IO ports 11. There are at most 6 circuit connection forms: the anode of the first diode 211 and the anode of the second diode 212 are electrically connected with the GPIO-1 port and the GPIO-2 port correspondingly; or is electrically connected with the GPIO-1 port and the GPIO-3 port correspondingly; or is electrically connected with the GPIO-2 port and the GPIO-3 port correspondingly; or is electrically connected with the GPIO-1 port and the GPIO-4 port correspondingly; or is electrically connected with the GPIO-2 port and the GPIO-4 port correspondingly; or is electrically connected with the GPIO-3 port and the GPIO-4 port correspondingly.

Referring to fig. 1, when the first expansion circuit 201 includes the 6 circuit connection types, the basic key 12 includes 4 keys, which are sequentially SW1, SW2, SW3, and SW 4; there are 6 expansion keys 22, which are SW5, SW6, SW7, SW8, SW9 and SW10 in sequence.

When the SW1 key is pressed, GPIO-1 is at low level, and the others are at high level.

GPIO-2 is low when the SW2 key is pressed, and the others are high.

GPIO-3 is low when the SW3 key is pressed, and the others are high.

The key SW4 is pressed to make GPIO-4 low, and the others high.

When the SW5 key is pressed, GPIO-2 and GPIO-3 are at low level, and the others are at high level.

When the SW6 key is pressed, the GPIO-1 and the GPIO-2 are at low level, and the other is at high level.

When the SW7 key is pressed, GPIO-3 and GPIO-4 are at low level, and the other is at high level.

When the SW8 key is pressed, the GPIO-1 and the GPIO-3 are at low level, and the other is at high level.

When the SW9 key is pressed, the GPIO-2 and GPIO-4 are at low level, and the others are at high level.

When the SW10 key is pressed, GPIO-1 and GPIO-4 are at low level, and the other is at high level.

At this time, the first expansion circuit 201 and the number b1 of the expansion keys 22 satisfy the following condition

Namely, the maximum value of the number b1 of the first expansion circuit 201 and the expansion keys 22 is 6. In this case, the total number of keys of the key circuit is 4+ 6-10 for the base key and the extended key. Compare 4 IO ports in the current matrix key circuit and can scan 4 buttons at most, this embodiment utilizes two IO ports 11 to correspond an extension button and carries out the button scanning to a plurality of IO ports 11 of make full use of improve the button scanning number, the IO port 11's of embedded development board utilization ratio when improving the scanning button, and then solve the less defect of the IO port 11 of sweeping the button number on the embedded development board among the prior art.

Referring to fig. 2, on the basis of the first expansion circuit 201, as an alternative embodiment, the expansion circuit 20 further includes a second expansion circuit 202; the diode group 21 in the second expander circuit 202 includes a third diode 213, a fourth diode 214, and a fifth diode 215 whose cathodes are electrically connected to each other;

an anode of the third diode 213, an anode of the fourth diode 214, and an anode of the fifth diode 215 are electrically connected to three of the four IO ports 11 correspondingly;

specifically, the anode of the third diode 213, the anode of the fourth diode 214, and the anode of the fifth diode 215 are electrically connected to three IO ports 11 of the four IO ports 11, and there are at most 4 circuit connection forms as follows: the anode of the third diode 213, the anode of the fourth diode 214 and the anode of the fifth diode 215 are electrically connected with the GPIO-1 port, the GPIO-2 port and the GPIO-3 port correspondingly; or is electrically connected with the GPIO-1 port, the GPIO-2 port and the GPIO-4 port correspondingly; or is electrically connected with the GPIO-1 port, the GPIO-3 port and the GPIO-4 port correspondingly; or the GPIO-2 port, the GPIO-3 port and the GPIO-4 port are electrically connected correspondingly.

Referring to fig. 2, when the second expansion circuit 202 includes the 6 circuit connection types, the basic key 12 includes 4 keys, which are sequentially SW1, SW2, SW3 and SW 4; there are 4 expansion keys 22, which are in turn SW11, SW12, SW13 and SW 14.

When the SW11 key is pressed, GPIO-1, GPIO-2 and GPIO-3 are at low level, and the others are at high level.

When the SW12 key is pressed, the GPIO-1, GPIO-2 and GPIO-4 are at low level, and the others are at high level.

When the SW13 key is pressed, GPIO-1, GPIO-3 and GPIO-4 are at low level, and the others are at high level.

When the SW14 key is pressed, GPIO-2, GPIO-3 and GPIO-4 are at low level, and the others are at high level.

It should be noted that, for simplicity of the drawing, the expansion circuits corresponding to the expansion keys SW6-SW10 are omitted in fig. 2.

At this time, the second expansion circuit 202 and the number b2 of the expansion keys 22 satisfy the following condition

I.e. the maximum value of the number b2 of the second expansion circuit 202 and the expansion keys 22 is 4. In this case, the total number of keys of the key circuit is 4+6+4+ 14. Compare 4 IO ports in current matrix key circuit and can scan 4 buttons at most, this embodiment utilizes two and three IO port 11 to correspond an extension button 22 and carries out the button scanning to a plurality of IO ports 11 of make full use of improve the button scanning number, the IO port 11's of embedded development board utilization ratio when improving the scanning button, and then solve the less defect of the IO port 11's of sweeping the key number on the embedded development board among the prior art.

On the basis of the first expansion circuit 201 and the second expansion circuit 202, as an alternative embodiment, the expansion circuit 20 further includes a third expansion circuit 203; the diode group 21 in the third expansion circuit 203 includes a sixth diode 216, a seventh diode 217, an eighth diode 218, and a ninth diode 219 whose cathodes are electrically connected to each other;

an anode of the sixth diode 216, an anode of the seventh diode 217, an anode of the eighth diode 218, and an anode of the ninth diode 219 are electrically connected to the four IO ports 11 correspondingly.

Specifically, the anode of the sixth diode 216, the anode of the seventh diode 217, the anode of the eighth diode 218, and the anode of the ninth diode 219 are electrically connected to the four IO ports 11 correspondingly, and only the following circuit connection forms exist: the anode of the sixth diode 216, the anode of the seventh diode 217, the anode of the eighth diode 218 and the anode of the ninth diode 219 are electrically connected to the GPIO-1 port, the GPIO-2 port, the GPIO-3 port and the GPIO-4 port.

Referring to fig. 3, when the second expansion circuit 202 includes the 6 circuit connection types, the basic key 12 includes 4 keys, which are sequentially SW1, SW2, SW3 and SW 4; the expand key 22 is SW 15.

It should be noted that, for simplicity of the drawing, the expansion keys SW6-SW10 and the corresponding expansion circuits of the expansion keys SW12-SW14 are omitted in fig. 3.

When the SW15 key is pressed, GPIO-1, GPIO-2, GPIO-3 and GPIO-4 are in low level. The number b3 of the third expansion circuit 203 and the expansion keys 22 is 1. In this case, the total number of keys of the key circuit is 4+6+4+ 1-15 of the base key + the extended key. Compared with the prior matrix key circuit, 4 IO ports can scan 2 at most⁴-1 ═ 15 keys. This embodiment utilizes two, three and four IO ports 11 to correspond an extension button 22 respectively and carries out the key scanning to a plurality of IO ports 11 of make full use of improve the key scanning number, the IO port 11's of embedded development board utilization ratio when improving the scanning key, and then solve the defect that the IO port 11 on the embedded development board sweeps the key number less among the prior art.

In other embodiments, the key scan may be performed by using a part of the two IO ports 11, a part of the three IO ports 11, and a corresponding one of the expansion keys 22 in the four IO ports 11. Referring to fig. 4, the expansion keys 22 include 5 in sequence, SW5a, SW6a, SW7a, SW8a and SW9 a.

When the SW5a key is pressed, GPIO-2 and GPIO-3 are at low level, and the others are at high level.

When the SW6a key is pressed, GPIO-1 and GPIO-2 are at low level, and the other is at high level.

When the SW7a key is pressed, GPIO-3 and GPIO-4 are at low level, and the other is at high level.

When the SW8a key is pressed, GPIO-1, GPIO-2 and GPIO-3 are at low level, and the others are at high level.

When the SW9a key is pressed, GPIO-1, GPIO-2, GPIO-3 and GPIO-4 are in low level.

In this case, the total number of keys of the key circuit is 4+ 5-9 of the basic key and the extended key. Compare 4 IO ports in current matrix key circuit and can scan 4 buttons at most, this embodiment utilizes partial IO port 11 in two IO ports 11 respectively, partial IO port 11 in the three IO port 11 and four IO port 11 correspond an extension button 22 and carry out the key scanning, thereby make full use of a plurality of IO ports 11, improve the button scanning number, the IO port 11's of embedded development board utilization ratio when improving the scanning button, and then solve the less defect of the button number of sweeping of IO port 11 on the embedded development board among the prior art.

On the basis of the above embodiments, as an alternative embodiment, the first diode 211 and the second diode 212 constitute a common cathode schottky diode. Because the schottky diode has the advantages of reduced forward voltage and high switching frequency, the first diode 211 and the second diode 212 are used to form the common cathode schottky diode, which is beneficial to optimizing the performance of the key circuit and reducing the power consumption of the key circuit.

Preferably, the common cathode schottky diode formed by the first diode 211 and the second diode 212 may be a common cathode schottky diode with model BAT 54C.

On the basis of the above embodiments, as an alternative embodiment, the third diode 213 and the fourth diode 214 constitute a common cathode schottky diode; the fifth diode 215 is a schottky diode single tube. Because the schottky diode has the advantages of reduced forward voltage and high switching frequency, the first diode 211 and the second diode 212 are used to form the common cathode schottky diode, which is beneficial to optimizing the performance of the key circuit and reducing the power consumption of the key circuit.

Preferably, the common cathode schottky diode formed by the third diode 213 and the fourth diode 214 may be a common cathode schottky diode with model BAT 54C. The fifth diode 215 can be a schottky diode single tube with BAT43 model.

On the basis of the above embodiments, as an alternative embodiment, the sixth diode 216 and the seventh diode 217 constitute a common cathode schottky diode; the eighth diode 218 and the ninth diode 219 constitute a common cathode schottky diode. Since the schottky diode has the advantages of reduced forward voltage and high switching frequency, the sixth diode 216 and the seventh diode 217 are used to form a common cathode schottky diode; the eighth diode 218 and the ninth diode 219 form a common cathode schottky diode, which is beneficial to optimizing the performance of the key circuit and reducing the power consumption of the key circuit.

Preferably, the common cathode schottky diode formed by the sixth diode 216 and the seventh diode 217 may be a common cathode schottky diode with a model BAT 54C. The common cathode schottky diode formed by the eighth diode 218 and the ninth diode 219 can be a common cathode schottky diode with model BAT 54C.

On the basis of the above embodiments, as an alternative embodiment, the base key 12 and the extension key 22 are respectively connected in parallel with the transient diode 30. The transient diode 30 is connected in parallel to the basic key 12, so that the basic circuit 10 is not influenced by external factors (such as electrostatic interference), and the stability of the basic circuit 10 is improved; by connecting the transient diode 30 in parallel to the extended key 22, the extended circuit 20 is not affected by external factors (such as electrostatic interference), and the stability of the extended circuit 20 is improved.

On the basis of the above embodiments, as an optional embodiment, a buffer resistor 40 is electrically connected between the output end of the diode group 21 and the extended key 22. By providing the buffer resistor 40 between the output terminal of the diode group 21 of the expansion circuit 20 and the expansion button 22, the buffer resistor 40 can prevent the expansion circuit 20 from being subjected to current surge, and the safety of the expansion circuit 20 can be improved.

In each basic circuit 10, a buffer resistor 40 is also electrically connected between the IO port 11 and the basic key 12. By providing the snubber resistor 40, the base circuit 10 can be prevented from being subjected to current surge, and the safety of the base circuit 10 can be improved.

Preferably, the buffer resistor 40 has a resistance value of 10-50 ohms. Further, in one embodiment, the buffer resistor 40 is selected to have a resistance of 22 ohms.

On the other hand, the present application proposes a development board (not shown) including the above-described key circuit. The key circuit described in the development board and the key circuit described above may be referred to with respect to each other.

The development board provided by the utility model is provided with a plurality of expansion circuits 20, wherein each expansion circuit 20 comprises a diode group 21 and an expansion key 22; the input end of the diode group 21 comprises k (k is more than or equal to 2 and less than or equal to n), the k input ends of the diode group 21 are respectively electrically connected with the IO ports 11 with corresponding quantity, and key scanning is carried out by utilizing the expansion keys 22 corresponding to the IO ports 11, so that the IO ports 11 are fully utilized, the key scanning number is increased, the utilization rate of the IO ports 11 of the embedded development board during key scanning is increased, and the defect that the number of the keys for scanning the IO ports 11 on the embedded development board is small in the prior art is overcome.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A key circuit, comprising:

the basic circuit comprises n basic circuits, and each basic circuit comprises an IO port and a basic key which are electrically connected in sequence; the free end of the basic key is grounded; and

the expansion circuit comprises a plurality of expansion circuits, and each expansion circuit comprises a diode group and an expansion key; the input ends of the diode groups comprise k, the input ends are electrically connected with the IO ports with corresponding quantity, the output ends of the diode groups are electrically connected with the expansion keys, and the free ends of the expansion keys are grounded; wherein n is more than or equal to 2; k is more than or equal to 2 and less than or equal to n;

2. The key circuit of claim 1, wherein the base circuit and the IO port each comprise 4, and the expansion circuit comprises a first expansion circuit; the diode group in the first extension circuit comprises a first diode and a second diode, wherein cathodes of the first diode and the second diode are electrically connected;

the number b1 of the first extension circuits satisfies the following condition

。

3. The key circuit of claim 2, wherein the expansion circuit further comprises a second expansion circuit; the diode group in the second expansion circuit comprises a third diode, a fourth diode and a fifth diode, wherein cathodes of the third diode, the fourth diode and the fifth diode are electrically connected with each other;

。

4. The key circuit of claim 3, wherein the expansion circuit further comprises a third expansion circuit; the diode group in the third extension circuit comprises a sixth diode, a seventh diode, an eighth diode and a ninth diode, the cathodes of which are electrically connected with each other;

5. The key circuit of claim 2, wherein the first diode and the second diode constitute a common cathode schottky diode.

6. The key circuit of claim 3, wherein the third diode and the fourth diode constitute a common cathode Schottky diode; and the fifth diode is a Schottky diode single tube.

7. The key circuit of claim 4, wherein the sixth diode and the seventh diode constitute a common cathode Schottky diode; the eighth diode and the ninth diode constitute a common cathode schottky diode.

8. The key circuit of claim 1, wherein the base key and the extended key are each connected in parallel with a transient diode.

9. The key circuit according to any one of claims 1-8, wherein a buffer resistor is electrically connected between the output terminal of the diode set and the extended key.

10. A development board comprising the key circuit of any one of claims 1 to 9.