CN210297670U

CN210297670U - GPIO (general purpose input/output) combined key circuit

Info

Publication number: CN210297670U
Application number: CN201921167680.0U
Authority: CN
Inventors: 李冰; 王广军; 王磊; 葛建伟
Original assignee: Contec Medical Systems Co Ltd
Current assignee: Contec Medical Systems Co Ltd
Priority date: 2019-07-24
Filing date: 2019-07-24
Publication date: 2020-04-10
Anticipated expiration: 2029-07-24

Abstract

The utility model provides a GPIO combined key circuit, which comprises a plurality of IO interfaces, one or a plurality of Schottky diodes, extended keys with the same number as the Schottky diodes, pull-up resistors and basic keys with the same number as the IO interfaces; two anodes of any Schottky diode can be respectively connected with any two IO interfaces, and the two IO interfaces connected with the two anodes of any Schottky diode are different from the two IO interfaces connected with the two anodes of any other Schottky diode; any IO interface is connected with a power supply through a corresponding pull-up resistor; one end of any basic key is electrically connected with the corresponding IO interface; one end of any extended key is electrically connected with the cathode of the corresponding Schottky diode. Compared with the prior art, the beneficial effects of the utility model reside in that: the utility model discloses can solve the IO interface and sweep the problem that the key number is not enough, can increase through this circuit and sweep the key number, the design principle is reliable, has wide application prospect.

Description

GPIO (general purpose input/output) combined key circuit

Technical Field

The utility model relates to an electronic circuit technical field, in particular to GPIO combination key circuit.

Background

Generally, the number of IO interfaces of a chip in the electronic circuit is limited, so that IO interface resources need to be seized from other application modules to the greatest extent in order to access a sufficient number of keys, but even though the number of IO interfaces saved cannot be matched with the number of keys.

Specifically, in the prior art, the keys are mostly scanned by using a matrix keyboard, and the key scanning capability of the matrix key circuit is as follows: 4 IO ports can scan 4 keys at most, 5 IO ports can scan 6 keys at most, and 6 IO ports can scan 9 keys at most. This obviously does not meet the practical requirements.

In addition, those skilled in the art also try to solve the above-mentioned contradiction by increasing the number of IO interfaces, for example, by adding one or more ICs to increase the IO interfaces for key scanning, but this will certainly increase a cost and expense, and this is not the optimal solution.

In summary, how to scan the most keys with the least IO interfaces is a problem that must be solved. Solving the problem has far-reaching significance in technical challenge and economic value.

Therefore, it is very urgent and necessary to design and develop a combined key circuit capable of increasing the number of key scans and obtaining key code values of a plurality of keys under the condition of limited IO interfaces.

In view of the above-mentioned drawbacks, the authors of the present invention have finally obtained the present invention through long-term research and practice.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical defects, the utility model adopts the technical scheme that the utility model provides a GPIO combined key circuit which is characterized by comprising a plurality of IO interfaces, one or a plurality of Schottky diodes, extension keys with the same number as the Schottky diodes, pull-up resistors and basic keys with the same number as the IO interfaces; two anodes of any Schottky diode can be respectively connected with any two IO interfaces, and the two IO interfaces connected with the two anodes of any Schottky diode are different from the two IO interfaces connected with the two anodes of any other Schottky diode; any IO interface is connected with a power supply through a corresponding pull-up resistor; one end of any basic key is electrically connected with the corresponding IO interface; one end of any extended key is electrically connected with the cathode of the corresponding Schottky diode.

Preferably, the GPIO combination key circuit includes N IO interfaces, the number of keys that the GPIO combination key circuit can scan at most is N + C (N,2), and C (N,2) is a combination number.

Preferably, the number of the expansion keys is less than or equal to C (N, 2).

Preferably, a buffer resistor is connected in series between the IO interface and the corresponding basic key, and a buffer resistor is connected in series between a cathode of the schottky diode and the corresponding extended key.

Preferably, the resistance value of the buffer resistor is 22 ohms.

Preferably, the GPIO combination key circuit further includes a plurality of voltage dependent resistors, one end of each voltage dependent resistor is connected to the circuit between the buffer resistor and the basic key, and the other end of each voltage dependent resistor is grounded.

Preferably, the GPIO combination key circuit further includes a plurality of voltage dependent resistors, one end of each voltage dependent resistor is connected to the circuit between the buffer resistor and the extension key, and the other end of each voltage dependent resistor is grounded.

Preferably, the resistance value of the pull-up resistor is 100K ohms.

Preferably, the model of the Schottky diode is BAT 54C.

Preferably, the other end of any one of the basic keys is grounded, and the other end of any one of the extended keys is grounded.

Compared with the prior art, the beneficial effects of the utility model reside in that:

the utility model discloses can solve the IO interface and sweep the problem that the key number is not enough, can increase through this circuit and sweep the key number. The circuit has reliable design principle and very wide application prospect.

Drawings

Fig. 1 is a schematic structural diagram of a GPIO combined key circuit in embodiment 1 of the present invention.

Reference numerals:

the power supply 10, the first IO interface 11, the second IO interface 12, the third IO interface 13, the fourth IO interface 14, the first schottky diode 21, the second schottky diode 22, the third schottky diode 23, the first pull-up resistor 31, the second pull-up resistor 32, the third pull-up resistor 33, the fourth pull-up resistor 34, the first basic key 41, the second basic key 42, the third basic key 43, the fourth basic key 44, the first extended key 51, the second extended key 52, the third extended key 53, the first buffer resistor 71, the second buffer resistor 72, the third buffer resistor 73, the fourth buffer resistor 74, the fifth buffer resistor 75, the sixth buffer resistor 76, and the seventh buffer resistor 77.

Detailed Description

The above and further features and advantages of the present invention will be described in more detail below with reference to the accompanying drawings.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of describing the present invention, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present application, unless expressly stated or limited otherwise, the first feature may be directly on or directly under the second feature or indirectly via intermediate members. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

The GPIO combination key circuit provided in this embodiment includes a plurality of IO interfaces, one or more schottky diodes, extended keys having the same number as the schottky diodes, pull-up resistors, and basic keys having the same number as the IO interfaces. Two positive poles of any schottky diode can be connected with two arbitrary IO interfaces respectively, and two IO interfaces that two positive poles of any schottky diode are connected are inequality with two IO interfaces that two positive poles of any other schottky diode are connected. Any IO interface is electrically connected with a power supply through a pull-up resistor corresponding to the IO interface. One end of any basic key is electrically connected with the IO interface corresponding to the basic key, and the other end of the basic key is grounded. One end of any extended key is electrically connected with the cathode of the corresponding Schottky diode, and the other end of the extended key is grounded.

The utility model provides a GPIO combination keying circuit, the key ability of sweeping of this circuit will be strong a lot than matrix keying circuit, GPIO combination keying circuit makes the external key number of the several mouthful scanning of IO obtain promoting through increasing schottky diode, and then improved the utilization ratio of chip IO interface, 4 a IO mouth can scan 10 buttons at most, 5 IO mouths can scan 15 buttons at most, 6 a IO mouths can scan 21 buttons at most, the problem that IO mouth sweeps the key number not enough on the embedded development board has been solved, increase the number of sweeping the key.

The calculation mode of the maximum number of the scannable keys is as follows:

suppose a GPIO combinational key circuit includes N IO interfaces, the maximum number of basic keys that can be connected to the N IO interfaces is N, the number of extended keys that can be connected to the GPIO combinational key circuit is C (N,2), the C (N,2) is a combination number, and C (N,2) ═ N! /[ 2! (N-2)! ].

Therefore, the calculation formula of the maximum number M of scannable keys is M + N (N, 2).

Take 5 IO interfaces as an example, M ═ 5+ { 5! /[ 2! (5-2)! 5+ (120/12) ═ 15.

Take 6 IO interfaces as an example, M ═ 6+ { 6! /[ 2! (6-2)! 6+ (720/48) ═ 21.

In addition, a buffer resistor can be connected between the IO interface and the corresponding basic key in series, and the buffer resistor is used for preventing the circuit from being impacted by current. And a buffer resistor can be connected between the cathode of the Schottky diode and the corresponding expansion key in series, and the buffer resistor has the function of preventing the circuit from being impacted by current.

Further, the utility model discloses still be provided with piezo-resistor on key circuit, piezo-resistor's effect is guaranteed that key circuit does not receive external factor, like electrostatic interference. One end of the partial piezoresistor is connected in a circuit between the buffer resistor and the basic key, and the other end of the partial piezoresistor is grounded. One end of the partial piezoresistor is connected in a circuit between the buffer resistor and the expansion key, and the other end of the partial piezoresistor is grounded.

Example 1

Fig. 1 is a schematic structural diagram of a GPIO combined key circuit in embodiment 1 of the present invention. As shown in fig. 1, the GPIO combined key circuit provided in this embodiment includes a plurality of IO interfaces, one or more schottky diodes, extended keys having the same number as the schottky diodes, pull-up resistors, and basic keys having the same number as the IO interfaces. Two positive poles of any schottky diode can be connected with two arbitrary IO interfaces respectively, and two IO interfaces that two positive poles of any schottky diode are connected are inequality with two IO interfaces that two positive poles of any other schottky diode are connected. Any one IO interface is electrically connected with a power supply through a pull-up resistor corresponding to the IO interface. One end of any basic key is electrically connected with the IO interface corresponding to the basic key, and the other end of the basic key is grounded. One end of any extended key is electrically connected with the cathode of the corresponding Schottky diode, and the other end of the extended key is grounded.

Preferably, in this embodiment, the number of the IO interfaces is 4, the number of the basic keys is 4, and the maximum number of the extended keys and the schottky diodes is 6, but in practice, the working principle of the GPIO combination key circuit is specifically explained by using the numbers of the extended keys and the schottky diodes as 3.

The IO interfaces include a first IO interface 11, a second IO interface 12, a third IO interface 13, and a fourth IO interface 14. The basic keys include a first basic key 41, a second basic key 42, a third basic key 43, and a fourth basic key 44. The expansion keys include a first expansion key 51, a second expansion key 52, and a third expansion key 53. The pull-up resistors include a first pull-up resistor 31, a second pull-up resistor 32, a third pull-up resistor 33, and a fourth pull-up resistor 34. The schottky diodes include a first schottky diode 21, a second schottky diode 22, and a third schottky diode 23.

One end of the first pull-up resistor 31 is electrically connected to the first IO interface 11, and the other end is connected to the power supply 10. One end of the second pull-up resistor 32 is electrically connected to the second IO interface 12, and the other end is connected to the power supply 10. One end of the third pull-up resistor 33 is electrically connected to the third IO interface 13, and the other end is connected to the power supply 10. One end of the fourth pull-up resistor 34 is electrically connected to the fourth IO interface 14, and the other end is connected to the power supply 10. And a resistor is pulled up to ensure that the IO interface is at a high level under the condition that no key is pressed. The pull-up resistor preferably has a resistance of 100K ohms.

The first pin and the second pin (two anodes) of the first schottky diode 21 are electrically connected to the second IO interface 12 and the third IO interface 13, respectively. The first pin and the second pin (two anodes) of the second schottky diode 22 are electrically connected to the first IO interface 11 and the second IO interface 12, respectively. The first pin and the second pin (two anodes) of the third schottky diode 23 are electrically connected to the third IO interface 13 and the fourth IO interface 14, respectively.

Preferably, the model of the Schottky diode is BAT 54C.

The buffer resistor further includes 7 buffer resistors, and the buffer resistors include a first buffer resistor 71, a second buffer resistor 72, a third buffer resistor 73, a fourth buffer resistor 74, a fifth buffer resistor 75, a sixth buffer resistor 76, and a seventh buffer resistor 77.

One end of the first buffer resistor 71 is electrically connected to the first IO interface 11, and the other end is electrically connected to one end of the first basic key 41. One end of the second buffer resistor 72 is electrically connected to the second IO interface 12, and the other end is electrically connected to one end of the second basic key 42. One end of the third buffer resistor 73 is electrically connected to the third IO interface 13, and the other end is electrically connected to one end of the third basic key 43. One end of the fourth buffer resistor 74 is electrically connected to the fourth IO interface 14, and the other end is electrically connected to one end of the fourth basic key 44.

One end of the fifth buffer resistor 75 is electrically connected to the third pin (cathode) of the first schottky diode 21, and the other end is electrically connected to one end of the first extended key 51. One end of the sixth buffer resistor 76 is electrically connected to the third pin (cathode) of the second schottky diode 22, and the other end is electrically connected to one end of the second extended key 52. One end of the seventh buffer resistor 77 is electrically connected to the third pin (cathode) of the third schottky diode 23, and the other end is electrically connected to one end of the third extended key 53.

Preferably, the buffer resistor has a resistance of 22 ohms. The buffer resistor can prevent the circuit from current impact.

The other end of the first basic key 41, the other end of the second basic key 42, the other end of the third basic key 43, the other end of the fourth basic key 44, the other end of the first extended key 51, the other end of the second extended key 52, and the other end of the third extended key 53 are commonly grounded.

The utility model provides a GPIO combination key circuit in 1 still includes piezo-resistor, and piezo-resistor includes first piezo-resistor, second piezo-resistor, third piezo-resistor, fourth piezo-resistor, fifth piezo-resistor, sixth piezo-resistor and seventh piezo-resistor.

The first varistor has one end connected to the circuit between the first buffer resistor 71 and the first basic key 41, and the other end grounded. One end of the second voltage dependent resistor is connected to the circuit between the second buffer resistor 72 and the second basic key 42, and the other end is grounded. One end of the third voltage dependent resistor is connected to the circuit between the third buffer resistor 73 and the third basic key 43, and the other end is grounded. One end of the fourth voltage dependent resistor is connected in the circuit between the fourth buffer resistor 74 and the fourth basic key 44, and the other end is grounded. One end of the fifth voltage dependent resistor is connected to the circuit between the fifth buffer resistor 75 and the first extended key 51, and the other end is grounded. One end of the sixth piezoresistor is connected to the circuit between the sixth buffer resistor 76 and the second extended key 52, and the other end is grounded. One end of the seventh voltage dependent resistor is connected to the circuit between the seventh buffer resistor 77 and the third extended key 53, and the other end is grounded. The first to seventh voltage dependent resistors are used for ensuring that the key circuit is not interfered by external factors such as static electricity.

The utility model provides a GPIO combination key circuit's among 1 theory of operation is:

when the first basic key 41 is pressed, the first IO interface 11 is at a low level, and the others are at a high level.

When the second basic key 42 is pressed, the second IO interface 12 is at a low level, and the others are at a high level.

When the third basic key 43 is pressed, the third IO interface 13 is at a low level, and the others are at a high level.

When the fourth basic key 44 is pressed, the fourth IO interface 14 is at a low level, and the others are at a high level.

When the first expansion key 51 is pressed, the second IO interface 12 and the third IO interface 13 are at a low level, and the others are at a high level.

When the second expansion key 52 is pressed, the first IO interface 11 and the second IO interface 12 are at a low level, and the others are at a high level.

When the third expansion key 53 is pressed, the third IO interface 13 and the fourth IO interface 14 are at a low level, and the others are at a high level.

To sum up, the utility model discloses GPIO combination key circuit in embodiment 1 has scanned seven buttons through four IO interfaces to can scan 10 buttons at most.

The utility model provides a GPIO combination key circuit in 1 makes IO scanning external button number obtain the promotion through increasing BAT54C, and then has improved the utilization ratio of chip IO interface. The utility model discloses can solve the IO interface on the embedded development board and sweep the problem that the key number is not enough, it can increase the number of sweeping the key. The utility model relates to a principle is reliable, has very extensive application prospect.

Example 2

The present embodiment is different from embodiment 1 in that:

in this embodiment, all the first to seventh buffer resistors are replaced by wires, and even so, the GPIO combined key circuit provided in this embodiment can still achieve the effect of improving the utilization rate of the chip IO interface, and can increase the number of scan keys.

Example 3

The present embodiment is different from embodiment 1 in that:

all piezoresistors in the circuit of the embodiment 1 are not arranged, and even then, the GPIO combined key circuit provided by the embodiment can still realize the effect of improving the utilization rate of the IO interface of the chip, and the number of the scanned keys can be increased.

Example 4

The present embodiment is different from embodiment 2 in that:

all piezoresistors in the circuit of the embodiment 2 are not arranged, and even then, the GPIO combined key circuit provided by the embodiment can still realize the effect of improving the utilization rate of the IO interface of the chip, and the number of the scanned keys can be increased.

The foregoing is merely a preferred embodiment of the invention, which is intended to be illustrative, not limiting. The utility model discloses in all can change to some extent structure and connected mode etc. of each part all be in the utility model discloses equal transform and the improvement of going on technical scheme's the basis all should not get rid of the utility model discloses an outside the protection scope.

Claims

1. A GPIO combined key circuit is characterized by comprising a plurality of IO interfaces, one or more Schottky diodes, expansion keys with the same number as the Schottky diodes, pull-up resistors and basic keys with the same number as the IO interfaces; two anodes of any Schottky diode can be respectively connected with any two IO interfaces, and the two IO interfaces connected with the two anodes of any Schottky diode are different from the two IO interfaces connected with the two anodes of any other Schottky diode; any IO interface is connected with a power supply through a corresponding pull-up resistor; one end of any basic key is electrically connected with the corresponding IO interface; one end of any extended key is electrically connected with the cathode of the corresponding Schottky diode.

2. The GPIO combination key circuit of claim 1, wherein the GPIO combination key circuit includes N IO interfaces, the number of keys that the GPIO combination key circuit can scan is at most N + C (N,2), and C (N,2) is a combined number.

3. The GPIO combination key circuit of claim 2, wherein the number of extended keys is equal to or less than C (N, 2).

4. The GPIO combination key circuit of claim 1, wherein a buffer resistor is connected in series between the IO interface and the corresponding basic key, and a buffer resistor is connected in series between a cathode of the schottky diode and the corresponding extended key.

5. The GPIO combination key circuit of claim 4, wherein the buffer resistor has a resistance of 22 ohms.

6. The GPIO combination key circuit of claim 4, further comprising a plurality of voltage dependent resistors, one end of each voltage dependent resistor being connected in the circuit between the buffer resistor and the base key and the other end being connected to ground.

7. The GPIO combination key circuit of claim 4, further comprising a plurality of voltage dependent resistors, one end of each voltage dependent resistor being connected in the circuit between the buffer resistor and the extended key, and the other end of each voltage dependent resistor being connected to ground.

8. The GPIO combination key circuit of claim 1, wherein the pull-up resistor has a resistance of 100 kohms.

9. The GPIO combination key circuit of any one of claims 1-8, wherein the Schottky diode is of type BAT 54C.

10. The GPIO combination key circuit of claim 1, wherein the other end of any one of the base keys is grounded and the other end of any one of the extended keys is grounded.