CN216563190U

CN216563190U - Micro LED chip and display device comprising same

Info

Publication number: CN216563190U
Application number: CN202123328556.8U
Authority: CN
Inventors: 刘召军; 黄青青; 张珂
Original assignee: Shenzhen Stan Technology Co Ltd
Current assignee: Xiamen Sitan Semiconductor Co ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-05-17
Anticipated expiration: 2031-12-28

Abstract

The present disclosure provides a micro LED chip and a display device including the same. The micro LED chip includes: a mesa structure formed by etching the micro LED epitaxial wafer; the electrode layer is arranged on the mesa structure and comprises an island structure, the island structure comprises an island main body and a connecting part, and the island main body is separated from the electrode layer and is connected with the electrode layer through the connecting part; a passivation layer disposed on the electrode layer, and including a plurality of contact holes, at least a portion of which is exposed to include at least a portion of the island body and not including the electrode layer connected to the island body; and a metal bump disposed on a portion where the plurality of contact holes are exposed. According to the technical scheme of this disclosure, the metal bump sets up can be making the yields of metal bump improve greatly on island structure to the reliability when reinforcing with the flip-chip bonding of drive base plate.

Description

Micro LED chip and display device comprising same

Technical Field

The disclosure relates to the technical field of semiconductor LEDs, in particular to a micro LED chip and a display device comprising the same.

Background

Micro LED display technology is considered to be the most promising new generation of display technology following LCD, OLED. Because the Micro LED chip is small in size, the traditional lead bonding mode cannot meet the requirement for integrating the Micro-LED chip and the driving substrate, and the traditional feasible scheme is to integrate the Micro-LED chip and the driving substrate in a flip-chip bonding mode.

Several key technologies in the flip chip technology are under bump metallization layer fabrication technology, metal bump fabrication technology, flip chip and underfill technology, respectively. For Micro-LED chips, a lower melting point material is typically used for bumping to accommodate lower temperature flip chip bonding. However, an obvious problem is that under the condition that the passivation layer has an unsatisfactory coating effect, the bump material permeates into the conductive metal layer in the reflow process, so that the passivation layer bulges or even is separated from the conductive metal layer, the bump material is not spherical, and an ideal bump cannot be formed.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problems mentioned in the background art, the present disclosure provides a micro LED chip and a display device including the same.

According to an aspect of the embodiments of the present disclosure, there is provided a micro LED chip, wherein the micro LED chip includes: a mesa structure formed by etching the micro LED epitaxial wafer; an electrode layer disposed on the mesa structure and including an island structure including an island body and a connection portion, the island body being spaced apart from the electrode layer and connected by the connection portion; a passivation layer disposed on the electrode layer and including a plurality of contact holes, at least some of which expose portions including at least a portion of the island body and not including the electrode layer connected to the island body; and a metal bump disposed on a portion where the plurality of contact holes are exposed.

Further, the mesa structure is a common cathode structure and includes a cathode corresponding portion and a plurality of anode corresponding portions.

Further, the electrode layer includes a cathode layer and an anode layer, and the micro LED chip further includes: a current diffusion layer disposed on the anode counterpart, and the anode layer is disposed on the current diffusion layer, and the cathode layer is disposed on the cathode counterpart.

Further, the anode layer and the cathode layer each include the island structure, and the exposed portion of the contact hole includes at least a portion of the island body and does not include an electrode layer connected to the island body.

Further, only the cathode layer includes the island structure, a portion of the passivation layer corresponding to the cathode layer exposed by the contact hole includes at least a portion of the island body and does not include the cathode layer connected to the island body, and a portion of the passivation layer corresponding to the anode layer exposed by the contact hole includes a portion of the anode layer.

Further, the micro LED chip further includes: an under bump metallization layer disposed on the portion of the contact hole exposed, and the metal bump is disposed on the under bump metallization layer.

Further, the material of the metal bump comprises indium.

Further, the island structure further comprises a hollow-out part for separating the island main body from the electrode layer, the hollow-out part penetrates through the electrode layer, a filling part is arranged in the hollow-out part, and the filling part is attached to and connected with the hollow-out part and connected with the passivation layer.

Further, the island structure includes a square shape in a cross section parallel to the electrode layer surface, the island body includes a square shape in the cross section, the connection portion connects four corners of the island body having a square cross section with the electrode layer, and the hollow portion includes a trapezoidal shape in the cross section.

Further, the shape of the contact hole on the cross section parallel to the surface of the electrode layer is circular or square, and the size of the contact hole is larger than that of the island main body and smaller than that of the island structure.

Further, the passivation layer comprises a blocking portion which is located in the hollow portion and connected with the electrode layer and the exposed portion of the hollow portion.

Further, the anode corresponding part sequentially comprises a substrate, a buffer layer, a first semiconductor layer, a multi-layer quantum well structure and a second semiconductor layer from bottom to top, and the cathode corresponding part sequentially comprises the substrate, the buffer layer and the first semiconductor layer from bottom to top.

Further, the first semiconductor layer is an N-GaN layer, the second semiconductor layer is a P-GaN layer, and the N-GaN layer of the cathode corresponding portion and the N-GaN layers of the anode corresponding portions are the same semiconductor layer.

According to still another aspect of the disclosed embodiments, there is also provided a display device. The display device comprises the micro LED chip.

By applying the technical scheme, the metal salient points are arranged on the island structure, so that the yield of the metal salient points is greatly improved, and the reliability of flip-chip bonding with the driving substrate is enhanced. This is because the island structure can greatly reduce the penetration of bump material into the electrode layer during the formation of the metal bump. In addition, the metal bump is arranged on the island structure, so that the passivation layer is prevented from bulging and even separating from the electrode layer due to the permeation of the bump material to the electrode layer in the forming process of the metal bump, and the performance of the Micro-LED chip can be ensured.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

fig. 1 is a flow chart illustrating a method of fabricating a micro LED chip according to one embodiment of the present disclosure;

fig. 2 a-2 h are schematic diagrams illustrating a fabrication process flow of a method of fabricating a micro LED chip according to one embodiment of the present disclosure;

fig. 3 is a top view illustrating an island structure formed in a predetermined area on a cathode layer according to one embodiment of the present disclosure;

fig. 4 is a top view illustrating a contact hole formed in a passivation layer corresponding to an island structure according to an embodiment of the present disclosure.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

Spatially relative terms, such as "above … …," "above … …," "above … … surface," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may also be oriented 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.

Exemplary embodiments according to the present disclosure will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same devices are denoted by the same reference numerals, and thus the description thereof will be omitted.

The disclosure provides a method for manufacturing a micro LED chip. Referring to fig. 1, fig. 1 is a flowchart illustrating a micro LED chip fabrication method according to one embodiment of the present disclosure. As shown in fig. 1, the method for manufacturing a micro LED chip includes the following steps S101 to S104.

And S101, providing a micro LED epitaxial wafer, and etching a mesa structure on the micro LED epitaxial wafer.

And S102, arranging a conductive metal layer on the mesa structure to serve as an electrode layer, so that an island structure is formed in a first preset region of the electrode layer, wherein the island structure comprises an island main body and a connecting part, and the island main body is separated from the electrode layer and is connected with the electrode layer through the connecting part.

And S103, arranging a passivation layer on the island structure and the electrode layer, and forming a plurality of contact holes in a second preset area of the passivation layer, so that at least part of the contact holes in the plurality of contact holes are exposed to include at least part of the island main body and not include the electrode layer connected with the island main body.

And step S104, arranging metal bumps on the exposed parts of the contact holes.

According to the technical scheme, an island structure can be formed in the conductive metal layer, namely the electrode layer, and the metal salient points formed on the island structure can greatly reduce the permeation of salient point materials to the electrode layer in the process of forming the metal salient points, so that the passivation layer is prevented from bulging and even separating from the electrode layer, the salient point materials are not spherical and can not form ideal salient points, and the performance of the Micro-LED chip and the reliability of the Micro-LED chip in flip-chip bonding with the driving substrate are further ensured.

In step S101, a micro LED epitaxial wafer may be provided, and a mesa structure may be etched on the micro LED epitaxial wafer.

According to the embodiment of the present disclosure, in order to prepare a micro LED chip, a micro LED epitaxial wafer may be obtained first, and the epitaxial wafer may be prepared in advance or may be prepared in the micro LED chip preparation method of the present disclosure. Referring to fig. 2a to 2h, fig. 2a to 2h are schematic views illustrating a process flow of a method for fabricating a micro LED chip according to an embodiment of the present disclosure, wherein fig. 2a illustrates a micro LED epitaxial wafer 1 according to an embodiment of the present disclosure. As shown in fig. 2a, the micro LED epitaxial wafer 1 may include, in order from bottom to top, a substrate 101, a buffer layer 102, a first semiconductor layer 103, a multi-layer quantum well structure 104, and a second semiconductor layer 105. It should be understood that the epitaxial wafer shown in fig. 2a is only an exemplary epitaxial wafer for explaining the technical solution of the present disclosure, and the epitaxial wafer may further include other layers or structures, which is not limited herein.

After the micro LED epitaxial wafer is obtained, it may be etched to obtain a mesa structure for disposing an electrode. Referring to fig. 2a to 2h, fig. 2a to 2h are schematic views illustrating a process flow of a method for fabricating a micro LED chip according to an embodiment of the present disclosure, wherein fig. 2b illustrates a mesa structure 2 formed after etching a micro LED epitaxial wafer 1. As shown in fig. 2b, the mesa structure 2 is a common cathode structure and may include a cathode counterpart 10 and a plurality of anode counterparts 20. A plurality of anode counterparts 20 can be arranged in an array, and since fig. 2b is a cross-sectional side view, only two anode counterparts 20 can be seen, the number of anode counterparts in fig. 2 a-2 h being merely illustrative and not limiting. The cathode corresponding portions 10 are located between and around the plurality of anode corresponding portions 20. The anode counterpart 20 may include a substrate 101, a buffer layer 102, a first semiconductor layer 103, a multi-layer quantum well structure 104, and a second semiconductor layer 105 in sequence from bottom to top, and the cathode counterpart 10 may include the substrate 101, the buffer layer 102, and the first semiconductor layer 103 in sequence from bottom to top. Preferably, the first semiconductor layer 103 may be an N-GaN layer, the second semiconductor layer 105 may be a P-GaN layer, and the N-GaN layer of the cathode corresponding part 10 and the N-GaN layers of the plurality of anode corresponding parts 20 are the same semiconductor layer, thereby forming a cathode-common structure.

According to an embodiment of the present disclosure, in order to obtain the mesa structure, the etching a mesa structure on the micro LED epitaxial wafer may include: and etching the mesa structure on the micro LED epitaxial wafer by adopting an inductively coupled plasma etching method. Specifically, positive photoresist can be spin-coated on the micro LED epitaxial wafer, mesa patterns can be photoetched, and an inductively coupled plasma etching (ICP) method is adopted, so that BCl is used₃And Cl₂Mixed gas or Cl₂And Ar₂The mixed gas is etched and finally the photoresist is removed to form the mesa structure 2 shown in fig. 2 b. Of course, any other suitable process may be used to etch a mesa structure on the micro LED epitaxial wafer.

In addition, the mesa structure may not be a common cathode structure as described above, but may be any other structure suitable for disposing an electrode, which is not limited herein.

In step S102, a conductive metal layer may be disposed on the mesa structure as an electrode layer, so that an island structure is formed in a first predetermined region of the electrode layer, where the island structure includes an island body and a connection portion, and the island body is separated from the electrode layer and connected to the connection portion through the connection portion.

According to an embodiment of the present disclosure, for the mesa structure described in step S101, a conductive metal layer may be disposed on the mesa structure as an electrode layer, and an island structure is formed in a first preset region of the electrode layer.

In particular, the electrode layers may include a cathode layer and an anode layer. In one embodiment, the disposing a conductive metal layer as an electrode layer on the mesa structure, so that forming an island structure in a first predetermined region of the electrode layer may include: and arranging a conductive metal layer as an electrode layer on the anode corresponding part and the cathode corresponding part, so that an island structure is formed in a first preset area of the electrode layer, the conductive metal layer on the anode corresponding part is used as the anode layer, and the conductive metal layer on the cathode corresponding part is used as the cathode layer. In another embodiment, the disposing a conductive metal layer as an electrode layer on the mesa structure, such that forming an island structure in a first predetermined region of the electrode layer may include: providing a current diffusion layer on the anode-corresponding portion; and arranging a conductive metal layer on the current diffusion layer and the corresponding part of the cathode to serve as an electrode layer, so that an island structure is formed in a first preset area of the electrode layer, the conductive metal layer on the current diffusion layer serves as the anode layer, and the conductive metal layer on the corresponding part of the cathode serves as the cathode layer.

Referring to fig. 2a to 2h, fig. 2a to 2h are schematic views illustrating a manufacturing process flow of a micro LED chip manufacturing method according to an embodiment of the present disclosure. Wherein fig. 2c shows that a current diffusion layer 106 is provided on the anode corresponding portion 20, and in particular, the current diffusion layer 106 is provided on the second semiconductor layer 105 of the anode corresponding portion 20. Fig. 2d shows that a conductive metal layer is provided on the current spreading layer 106 as the anode layer 1071 and on the cathode counterpart 10 as a cathode layer 1072, in particular the cathode layer 1072 is provided on the first semiconductor layer 103 of the cathode counterpart 10. It is to be understood that the anode layer 1071 and the cathode layer 1072 are made by providing a conductive metal layer on both the current diffusion layer 106 and the cathode counterpart 10. As shown in fig. 2d, the electrode layers, i.e., the cathode layer 1072 and the anode layer 1071, may include four metal layers, i.e., a titanium metal layer, an aluminum metal layer, a titanium metal layer, and a gold metal layer, from bottom to top. Of course, the electrode layer may also comprise a plurality of metal layers made of any other suitable metal.

In addition, an island structure is formed in the first predetermined region of the electrode layer, the island structure including an island body and a connection portion, the island body being spaced apart from the electrode layer and connected through the connection portion.

According to an embodiment of the present disclosure, the first predetermined region refers to a predetermined region on the electrode layer, i.e., a position corresponding to the metal bump connecting the electrode, and the first predetermined region may be on the anode layer and/or the cathode layer. Further, the position of the first predetermined region, that is, the position of the island structure, may be set according to the area of the electrode layer (anode layer or cathode layer). The electrode layer area is the area of the electrode layer having a connection relationship, and is not the sum of the areas of the divided electrode layers, and when the electrode layer area is large, an island structure should be provided on the electrode layer, and when the electrode layer area is small, an island structure may be selectively provided on the electrode layer. The island structure refers to a portion of the electrode layer that is spaced apart from and electrically connected to the electrode layer.

In one embodiment, the first predetermined area belongs to the cathode layer. Thus, it is only possible to form the island structures in the predetermined regions on the cathode layer, and not on the anode layer.

As shown in fig. 2d, an island structure 30 is formed in a predetermined region on the cathode layer 1072, the island structure 30 including an island body 301 and a connection portion 302. Since the micro LED chips in this embodiment are of a common cathode structure, the cathode layer has a large area, and therefore only the cathode layer forms an island structure in this embodiment.

Although the area of the anode layer of the micro LED chip in the cathode-common structure is small, an island structure may be formed on the anode layer. In another embodiment, not shown, the first predetermined area may belong to the cathode layer and the anode layer. Thus, island structures may be formed in predetermined areas on the cathode layer and in predetermined areas on the anode layer.

To more clearly understand the island structures, referring to fig. 3, fig. 3 shows a top view of an island structure 30 formed in a predetermined area on the cathode layer 1072 according to one embodiment of the present disclosure. An island structure in a predetermined area on the anode layer can also be represented by this fig. 3. The island structure may include an island body and a connection portion, the island body being separated from the electrode layer (cathode layer or anode layer) and connected through the connection portion, and the island structure may further include a hollowed-out portion separating the island body from the electrode layer, the hollowed-out portion penetrating through the electrode layer (cathode layer or anode layer). As shown in fig. 3, the island structure 30 includes an island body 301 and a connection portion 302, the island body 301 is separated from the cathode layer 1072 and connected to the connection portion 302, and the island structure 30 may further include a hollow 303 separating the island body 301 from the cathode layer 1072, the hollow 303 penetrating the cathode layer 1072 to expose the first semiconductor layer. The island structure thus formed can be connected to the electrode layer without affecting electrical performance, and can be maximally spaced from the electrode layer.

According to an embodiment of the present disclosure, a shape of the island structure in a cross section parallel to the electrode layer surface includes a square, a shape of the island body in the cross section includes a square, the connection portion may connect four corners of the island body having a square cross section with the electrode layer, and the shape of the hollowed portion in the cross section includes a trapezoidal shape. As shown in fig. 3, the island structure 30 may have a square shape in cross section parallel to the surface of the cathode layer 1072, the island body 301 may have a square shape in cross section, the connection portion 302 may connect four corners of the island body 301 having a square cross section to the cathode layer 1072, and the hollow portion 303 may have a trapezoidal shape in cross section. It is noted that the shape of the island structure 30 shown in fig. 3 is merely exemplary and not limiting. The shape of the island structure 30 may also be any shape suitable for manufacturing, such as a circle, a triangle, etc., and likewise the shape of the island body 301 may be any shape suitable for manufacturing, such as a circle, a triangle, etc., and the shape of the island body 301 may be different from the shape of the island structure 30, and furthermore, the connection portions 302 may be three, five, etc. in number and may be connected to the electrode layer from any part of the island body. It is noted that fig. 2d is a side cross-sectional view taken along a cross-section through the center of the island body and perpendicular to the electrode layer surface in the lateral direction (horizontal direction) in fig. 3, and fig. 2 a-2 c and 2 e-2 h may be side cross-sectional views taken at the same location as fig. 2 d.

According to an embodiment of the present disclosure, the disposing of the current diffusion layer on the anode corresponding portion may include: and depositing the current diffusion layer on the corresponding part of the anode by adopting a magnetron sputtering method. Specifically, a negative photoresist may be spin-coated on the mesa structure shown in fig. 2b, a current diffusion layer pattern is photo-etched, then an ITO current diffusion layer (which may also be a current diffusion layer such as Ni/Au) is deposited by magnetron sputtering, and the current diffusion layer 106 shown in fig. 2c is obtained after photoresist stripping. Of course, any other suitable process may be used to provide a current spreading layer on the anode counterpart.

The disposing a conductive metal layer as an electrode layer on the current diffusion layer and the corresponding portion of the cathode such that forming an island structure in a first predetermined region of the electrode layer includes: and arranging a conductive metal layer on the current diffusion layer and the corresponding part of the cathode by adopting an electron beam deposition method and a stripping process method to serve as an electrode layer, so that an island structure is formed in a first preset area of the electrode layer.

Specifically, a negative photoresist may be spin-coated on the structure shown in fig. 2c, a pattern of a conductive metal layer may be photo-etched, where the pattern of the conductive metal layer includes a pattern of a conductive portion (i.e., an island main body and a connection portion) in the island structure at a position corresponding to the first predetermined region, then the conductive metal layer is deposited by an electron beam deposition method, i.e., a titanium metal layer, an aluminum metal layer, a titanium metal layer, and a gold metal layer are sequentially deposited (with the gold metal layer on the top), and finally the photoresist and the deposited metal on the photoresist are removed by a lift-off process, so as to obtain the structure shown in fig. 2d and fig. 3. Of course, any other suitable process method may be used to dispose the electrode layer and form the island structure in the first predetermined region of the electrode layer. In addition, oxygen plasma (O) may be used prior to depositing the conductive metal layer₂plasma) the structure for depositing the conductive metal layer is subjected to glue sweeping to remove residual organic matters such as photoresist and the like so as to ensure the adhesion between the conductive metal layer and the structure contacted with the conductive metal layer.

In step S104, a passivation layer may be disposed on the island structure and the electrode layer, and a plurality of contact holes may be formed in a second predetermined region of the passivation layer such that at least some of the contact holes expose portions including at least a portion of the island body and not including the electrode layer connected to the island body.

According to an embodiment of the present disclosure, a passivation layer may be disposed on the structure including the island structure and the electrode layer formed in step S103, and a contact hole penetrating the passivation layer may be formed in the passivation layer. The number of the contact holes is related to the number of the anode corresponding portions and the cathode corresponding portions, so that the contact holes are plural, at least one contact hole corresponds to the cathode corresponding portion, and at least one contact hole corresponds to the anode corresponding portion. Therefore, depending on the installation position of the island structure, all the contact holes may expose a part of the island body in the island structure, expose the island body, or expose the island body and a part of the connection portion; or some (or one) contact holes may also expose a portion of the island body in the island structure, expose the island body, or expose the island body and a portion of the connection portion and other (or another) contact holes expose a portion of the electrode layer.

In one embodiment, the first predetermined region belongs to the cathode layer, the second predetermined region belongs to passivation layers corresponding to the cathode layer and the anode layer, a portion of the passivation layer corresponding to the cathode layer exposed through the contact hole includes at least a portion of the island body and does not include an electrode layer connected to the island body, and a portion of the passivation layer corresponding to the anode layer exposed through the contact hole includes a portion of the anode layer.

Referring to fig. 2a to 2h, fig. 2a to 2h are schematic views illustrating a process flow of manufacturing a micro LED chip manufacturing method according to an embodiment of the present disclosure, and fig. 2e illustrates a passivation layer 108 having a contact hole 40 on an island structure 30 and electrode layers (a cathode layer 1072 and an anode layer 1071).

As shown in fig. 2e, since the second predetermined region belongs to the passivation layer 108 corresponding to the cathode layer 1072 and the anode layer 1071, when the first predetermined region belongs to the cathode layer 1072, that is, when the island structure 30 is formed in the predetermined region on the cathode layer 1072 and the island structure is not formed on the anode layer 1071, the contact hole 40 in the passivation layer 108 corresponding to the cathode layer 1072 exposes a portion of the island body 301 and the connection portion 302 and does not expose the cathode layer 1072, and the contact hole 40 in the passivation layer 108 corresponding to the anode layer 1071 exposes a portion of the anode layer 1071.

In another embodiment, not shown, the first predetermined area belongs to the cathode layer and the anode layer, the second predetermined area belongs to a passivation layer corresponding to the cathode layer and the anode layer, and the exposed portion of the contact hole in the passivation layer corresponding to the cathode layer and the anode layer includes at least a portion of the island body and does not include an electrode layer connected to the island body.

Since the second predetermined area belongs to the passivation layer corresponding to the cathode layer and the anode layer, when the first predetermined area belongs to the cathode layer and the anode layer, that is, when the island structures are formed in the predetermined area on the cathode layer and the predetermined area on the anode layer, all the contact holes expose at least a portion of the island body and do not expose the electrode layer.

To more clearly understand the contact holes, referring to fig. 4, fig. 4 illustrates a top view of the contact holes 40 formed in the passivation layer 108 corresponding to the island structures, according to one embodiment of the present disclosure. The contact hole has a circular or square shape in a cross section parallel to the surface of the electrode layer, and the size of the contact hole is larger than the size of the island body and smaller than the size of the island structure, so that the contact hole exposes the island body and a part of the connection portion 302 and does not expose the electrode layer connected to the island body. As shown in fig. 4, the contact hole 40 has a circular shape in a cross section parallel to the surface of the electrode layer, and the size of the contact hole 40 is larger than the size of the island body 301 and smaller than the size of the island structure 30, so that the contact hole 40 exposes the island body 301 and a part of the connection portion 302 and does not expose the electrode layer connected to the island body.

It should be appreciated that when the passivation layer 108 is disposed, the passivation layer material may fill the hollow 303 of the island structure 30. As shown in fig. 2e, in the case that the size of the contact hole 40 is larger than the size of the island body 301 and smaller than the size of the island structure 30, when the contact hole 40 is prepared, the passivation layer material in the portion of the hollow portion corresponding to the contact hole 40 is also removed and exposes the semiconductor layer (the first semiconductor layer or the second semiconductor layer), and the passivation layer material in the portion of the hollow portion not corresponding to the contact hole 40 is remained to form a barrier portion 1081, and the barrier portion 1081 separates the portion of the hollow portion exposing the semiconductor layer from the electrode layer.

In other embodiments not shown, the size of the contact hole may be smaller than or equal to the size of the island body, such that the contact hole exposes only a portion of the island body or only the island body. The contact hole thus provided does not expose the hollowed-out portion.

According to an embodiment of the present disclosure, the disposing a passivation layer on the island structure and the electrode layer, and forming a plurality of contact holes in a second predetermined region of the passivation layer includes: depositing a passivation layer on the island structure and the electrode layer by adopting a plasma enhanced chemical vapor deposition method; and etching the contact hole on the passivation layer by adopting an inductively coupled plasma etching method. In particular, a vapor deposition method (PECVD) using plasma enhanced chemistry may be employed to deposit SiO on the structure of FIG. 2d₂Or Si₃N₄Passivation layer, SiO₂The reaction gas used is SiH₄And N₂O，Si₃N₄With the reaction gas being SiH₄And NH₃After depositing the passivation layer, coating glue on the passivation layer to etch the contact hole pattern, and etching with Inductively Coupled Plasma (ICP) via SF₆、CHF₃And O₂The mixed gas etches a contact hole, and after photoresist is removed, a structure as shown in fig. 2e is formed.

In step S105, a metal bump may be disposed on the exposed portion of the plurality of contact holes.

According to the embodiment of the present disclosure, in order to complete the preparation of the micro LED chip, a metal bump, i.e., a metal bump that implements a connection electrode, may be disposed on a portion exposed by the contact hole so as to be bonded with other components to implement a corresponding function. The metal bump material may include indium, which has a low melting point and is particularly suitable for flip chip bonding at a relatively low temperature, but may also include any suitable metal.

In an embodiment, not shown, the disposing the metal bump on the portion exposed by the plurality of contact holes may include: arranging a metal column on the exposed part of the contact hole; and reflowing the metal pillar to form the metal bump.

Specifically, the disposing of the metal pillar on the portion exposed by the contact hole may include: and depositing a metal column covering the contact hole on the exposed part of the contact hole by adopting a vacuum thermal evaporation method. Specifically, the deposited metal fills the contact hole and the metal pillar formed over the contact hole has a diameter directly larger than the diameter of the contact hole. In the case that the exposed portion of the contact hole corresponds to the island structure, especially in the case that the size of the contact hole is larger than the size of the island body and smaller than the size of the island structure in step S104, in the process of preparing the metal pillar, the metal may fill up the hollow portion corresponding to the contact hole, and the barrier portion may isolate the metal in the hollow portion from the electrode layer. The reflowing the metal pillar to form the metal bump may include: placing the metal pillar in a vacuum reflow furnace and in N₂And refluxing in formic acid environment to form the metal bump. Specifically, the whole structure with the metal column is placed into a vacuum reflux furnace for refluxing the metal column, the vacuum reflux furnace is firstly vacuumized to ensure the vacuum state, and then N is introduced into the vacuum reflux furnace₂And formic acid and heating for reflux, and the vacuum environment is initially ensured to avoid the generation of metal oxide with high melting point due to metal oxidation in the reflux process. Formic acid can reduce metal oxides, and N₂Metal oxidation can be reduced. It is noted that in the presence of an island structure, the bump material orientation can be greatly reduced during the metal bump formation processAnd the electrode layer permeates, so that the passivation layer on the electrode layer is prevented from swelling and even separating from the electrode layer due to permeation, and the bump material is prevented from being unsphered and incapable of forming an ideal bump due to material reduction caused by permeation.

According to an embodiment of the present disclosure, before disposing metal on the exposed portions of the contact holes, disposing metal bumps on the exposed portions of the plurality of contact holes may further include: and adopting oxygen plasma to sweep glue from the contact hole. Organic matters such as residual photoresist in the contact hole are removed through the photoresist, and the adhesion between the exposed metal part in the contact hole and the subsequent evaporated metal is enhanced.

In another embodiment, disposing a metal bump on the portion exposed by the plurality of contact holes includes: disposing an Under Bump Metallization (UBM) on the exposed portion of the contact hole; arranging a metal column on the under bump metallization layer; and reflowing the metal pillar to form the metal bump.

Specifically, the disposing of the under bump metallization layer on the exposed portion of the contact hole may include: and depositing a titanium metal layer and a gold metal layer on the exposed part of the contact hole by adopting an electron beam deposition method to serve as the under-bump metallization layer. The under bump metallization layer comprises an adhesion layer, a barrier layer and a wetting layer, the titanium metal layer is used as the adhesion layer and the barrier layer, and the gold metal layer is used as the wetting layer. Referring to fig. 2a to 2h, fig. 2a to 2h are schematic diagrams illustrating a process flow of a method for fabricating a micro LED chip according to an embodiment of the present disclosure, and fig. 2f illustrates an under bump metallization layer 109 deposited on an exposed portion of the contact hole, the under bump metallization layer 109 covering the passivation layer 108 around the contact hole 40. Specifically, a negative photoresist may be spin-coated on the structure shown in fig. 2e, and the pattern of the under bump metallization layer is photo-etched, however, a titanium metal layer and a gold metal layer are sequentially deposited by an electron beam deposition method, and the photoresist and the excess metal are removed to obtain the structure shown in fig. 2f, in which only the under bump metallization layer 109 is shown in fig. 2f, and the delamination of the under bump metallization layer 109 is not shown. In the case that the exposed portion of the contact hole corresponds to the island structure, especially in the case that the size of the contact hole 40 in step S104 is larger than the size of the island body 301 and smaller than the size of the island structure 30, in the process of preparing the under bump metallization layer 109, the metal may fill the exposed portion of the semiconductor layer of the hollow portion, thereby forming the metal portion 1091 as shown in fig. 2 f. The barrier portion 1081 isolates the metal portion 1091 from the electrode layer. In addition, before the under bump metallization layer is arranged, residual organic matters such as photoresist can be removed by sweeping oxygen plasma on the structure for depositing the under bump metallization layer, so that the adhesion between the under bump metallization layer and the structure in contact with the under bump metallization layer is ensured.

Disposing a metal pillar on the under bump metallization layer may include: and depositing a metal column covering the under-bump metallization layer on the under-bump metallization layer by adopting a vacuum thermal evaporation method. Referring to fig. 2a to 2h, fig. 2a to 2h are schematic views illustrating a process flow of a method for fabricating a micro LED chip according to an embodiment of the present disclosure, and fig. 2g illustrates a metal pillar 110 formed on the under bump metallization layer 109. Specifically, a negative photoresist is spin coated on the structure shown in fig. 2f, the metal pillar is patterned, and then a metal is deposited by vacuum thermal evaporation, such as indium, and the photoresist and excess metal are removed, resulting in the structure shown in fig. 2 g.

The reflowing the metal pillar to form the metal bump may include: subjecting the metal pillar to N in a vacuum reflow furnace₂And refluxing in formic acid environment to form the metal bump. Referring to fig. 2a to 2h, fig. 2a to 2h are schematic views illustrating a process flow of a method for manufacturing a micro LED chip according to an embodiment of the present disclosure, and fig. 2h illustrates a metal bump 111 formed after reflow. Specifically, the structure shown in fig. 2g is placed in a vacuum reflow furnace for reflow of the metal pillar 110, the vacuum reflow furnace is first vacuumized to ensure a vacuum state, and then N is introduced into the vacuum reflow furnace₂And formic acid and heating to reflux to give the structure shown in figure 2 h. Wherein the initial vacuum environment can avoid metal oxidation during the reflux process to generate metal oxide with high melting point, formic acid can reduce the metal oxide, and N₂Metal oxidation can be reduced. Value ofIt is noted that providing an Under Bump Metallization (UBM) on the exposed portion of the contact hole, in particular on the island structure, and then providing a metal bump on the under bump metallization may further prevent the penetration of bump material into the electrode layer during the reflow process of the metal bump formation.

According to an embodiment of the present disclosure, before disposing the under bump metallization layer on the exposed portions of the contact holes, disposing the metal bumps on the exposed portions of the plurality of contact holes further comprises: and adopting oxygen plasma to sweep glue from the contact hole. Organic matters such as residual photoresist and the like in the contact hole are removed through the photoresist, and the adhesion between the exposed metal part in the contact hole and the subsequent evaporated metal is enhanced.

Thus, the micro LED chip is completed, and fig. 2h shows the completed micro LED chip.

The technical scheme of the disclosure can determine whether an island structure for contacting the metal bump is formed in the electrode layer according to the area of the electrode layer on which the metal bump is to be formed. If the area of the electrode layer is large, the direct preparation of the metal bump on the electrode layer may cause too much bump material to penetrate into the electrode layer in the process of forming the metal bump through metal reflow, which may cause the problem that the material originally used for forming the metal bump cannot be formed into a ball due to too little residue, and thus an ideal metal bump may not be realized, and even the passivation layer on the electrode layer may bulge or separate from the electrode layer due to the penetration of the bump material into the electrode layer, thereby affecting the chip performance and the reliability when bonding with other components.

According to the preparation method of the micro LED chip disclosed by the invention, under the condition that the area of the electrode layer is larger, an island structure can be formed in the electrode layer, and the island structure comprises an island main body, a connecting part for connecting the island main body with the electrode layer and a hollow part. And the contact hole for providing the metal bump and corresponding to the island structure may expose a portion of the island body, expose the island body, or expose a portion of the island body and the connection portion, but in either case, may not expose the electrode layer connected to the island body. The island structure and the contact hole formed on the island structure enable the bump material to only contact a part of the island main body, or only contact the island main body or contact the island main body and a part of the connecting part in the backflow process when the metal bump is arranged on the island structure, and the bump material can downwards flow into the hollow part to contact the semiconductor layer exposed by the hollow part and the barrier part belonging to the passivation layer when contacting the island main body and the part of the connecting part. Under the above contact conditions, the bump material does not contact the electrode layer connected to the island body. Therefore, the metal bump is arranged on the island structure, so that the bump material is only contacted with the relevant part of the island structure in the electrode layer and is not directly contacted with the electrode layer in the reflow process, and the permeation of the bump material to the electrode layer can only pass through the connecting part of the island structure, thereby being limited. Furthermore, the connection portions of the island structures may be narrow enough to limit the penetration of the bump material into the electrode layer as much as possible while satisfying the electrical properties. Therefore, the metal bump is arranged on the island structure disclosed by the disclosure, so that the permeation of bump materials to the electrode layer can be greatly reduced in the formation process of the metal bump, the passivation layer on the electrode layer is prevented from being bulged even being separated from the electrode layer due to permeation, and the bump materials are prevented from being reduced due to permeation to cause no balling and form an ideal bump.

For example, in the process of manufacturing the micro LED chip with the cathode-common structure shown in fig. 2f in the embodiment of the present disclosure, the cathode layer has a larger area, and forming the island structure in the cathode layer allows the permeation of the bump material into the electrode layer to be greatly reduced in the process of forming the metal bump, so that the effect is more obvious.

Of course, for electrode layers with smaller areas, isolated metal islands can be selectively formed in the electrode layers. When the metal island is not formed in the electrode layer, the manufacturing cost can be reduced, and when the metal island is formed in the electrode layer, the penetration of a bump material into the electrode layer in the metal bump forming process is also allowed to be reduced, so that a more ideal metal bump can be formed, and the method is suitable for the bonding operation with high requirements on the metal bump.

In addition, an Under Bump Metallization (UBM) layer is provided on the exposed portion of the contact hole, especially on the island structure, and then a metal bump is provided on the under bump metallization layer, which can further prevent the penetration of the bump material into the electrode layer during the reflow process of the bump material during the formation of the metal bump. Therefore, the formation of the island structure in the electrode layer and the formation of the under bump metallization layer on the island structure can allow the under bump metallization layer to prevent the bump material from flowing to the island structure in the backflow process, and even if the bump material enters the contact hole and flows onto the island structure, the island structure can greatly reduce the permeation of the bump material to the electrode layer, so that the passivation layer on the electrode layer can be further prevented from swelling and even separating from the electrode layer due to the permeation, and the bump material is further prevented from being non-balled and being incapable of forming an ideal bump due to the reduction of the material caused by the permeation.

The present disclosure also provides a micro LED chip. The micro LED chip can be manufactured by the preparation method of the micro LED chip.

As shown in fig. 2a to 2h, the micro LED chip may include: a mesa structure 2 formed by etching the micro LED epitaxial wafer 1; an electrode layer disposed on the mesa structure 2, the electrode layer comprising an island structure 30, the island structure 30 comprising an island body 301 and a connection portion 302, the island body 301 being separated from the electrode layer and connected by the connection portion 302; a passivation layer 108 disposed on the electrode layer, wherein the passivation layer 108 includes a plurality of contact holes 40, and a portion of at least a portion of the plurality of contact holes 40 exposed includes at least a portion of the island body 301 and does not include the electrode layer connected to the island body 301; and metal bumps 111 disposed on the exposed portions of the plurality of contact holes 40.

According to the structure of the miniature LED chip disclosed herein, the metal bumps are arranged on the island structure, so that the yield of the metal bumps is greatly improved, and the reliability of flip-chip bonding with the driving substrate is enhanced. This is because the island structure can greatly reduce the penetration of bump material into the electrode layer during the formation of the metal bump. In addition, the metal bump is arranged on the island structure, so that the passivation layer is prevented from bulging and even separating from the electrode layer due to the permeation of the bump material to the electrode layer in the forming process of the metal bump, and the performance of the Micro-LED chip can be ensured.

Embodiments of the micro LED chip of the present disclosure are further described below with reference to fig. 2 a-2 h, fig. 3, and fig. 4.

According to an embodiment of the present disclosure, the mesa structure 2 may be etched from the micro LED epitaxial wafer 1, and the micro LED epitaxial wafer 1 may include, in order from bottom to top, a substrate 101, a buffer layer 102, a first semiconductor layer 103, a multi-layer quantum well structure 104, and a second semiconductor layer 105. The mesa structure 2 may be a common cathode structure and may include a cathode counterpart 10 and a plurality of anode counterparts 20. The plurality of anode counterparts 20 may be formed in an array, and the number of anode counterparts in the drawings is merely illustrative and not limiting. The cathode counterpart 10 is located between and around the plurality of anode counterparts 20. The anode counterpart 20 may include a substrate 101, a buffer layer 102, a first semiconductor layer 103, a multi-layer quantum well structure 104, and a second semiconductor layer 105 in sequence from bottom to top, and the cathode counterpart 10 may include the substrate 101, the buffer layer 102, and the first semiconductor layer 103 in sequence from bottom to top. Preferably, the first semiconductor layer 103 may be an N-GaN layer, the second semiconductor layer 105 may be a P-GaN layer, and the N-GaN layer of the cathode corresponding part 10 and the N-GaN layers of the plurality of anode corresponding parts 20 are the same semiconductor layer, thereby forming a cathode-common structure.

According to an embodiment of the present disclosure, the electrode layer includes a cathode layer 1072 and an anode layer 1071, the micro LED chip further includes: a current diffusion layer 106 disposed on the anode counterpart 20, and the anode layer 1071 is disposed on the current diffusion layer 106, and the cathode layer 1072 is disposed on the cathode counterpart 10. Specifically, the current diffusion layer 106 is disposed on the second semiconductor layer 105 of the anode corresponding portion 20. The cathode layer 1072 is disposed on the first semiconductor layer 103 of the cathode corresponding portion 10.

According to an embodiment of the present disclosure, the passivation layer 108 blanket encloses a cathode layer 1072 and an anode layer 1071, only the cathode layer 1072 includes the island structures 30, the portion of the passivation layer 108 corresponding to the cathode layer 1072 exposed by the contact hole 40 includes at least a portion of the island body 301 and does not include the cathode layer 1072 connected to the island body 301, and the portion of the passivation layer 108 corresponding to the anode layer 1071 exposed by the contact hole 40 includes a portion of the anode layer 1071.

According to another not shown embodiment of the present disclosure, the passivation layer covers and encloses a cathode layer and an anode layer, both of which may comprise the island structure, the exposed portion of the contact hole comprising at least a portion of the island body and not comprising an electrode layer connected to the island body.

According to an embodiment of the present disclosure, the island structure 30 further includes a hollowed-out portion 303 separating the island body 301 from the electrode layer, and the hollowed-out portion 303 penetrates through the electrode layer.

According to an embodiment of the present disclosure, a shape of the island structure 30 on a cross section parallel to the electrode layer surface includes a square, a shape of the island body 301 on the cross section includes a square, the connection portion connects four corners of the island body having a square cross section with the electrode layer, and a shape of the hollowed-out portion 303 on the cross section includes a trapezoidal shape. It is noted that the shape of the island structure 30 shown in fig. 3 is merely exemplary and not limiting. The island structure 30 may also be in any shape suitable for manufacturing, such as circular, triangular, etc., and likewise the island body 301 may be in any shape suitable for manufacturing, such as circular, triangular, etc., and the island body 301 may be in a shape different from the island structure 30, and furthermore, the connection portions 302 may be in three, five, etc. numbers and may be connected to the electrode layer from any part of the island body

According to the embodiment of the present disclosure, the shape of the contact hole 40 in a cross section parallel to the surface of the electrode layer may be circular, or may be square, and the like, and the size of the contact hole 40 is larger than the size of the island body 301 and smaller than the size of the island structure 30, so that the contact hole 40 exposes the island body 301 and a part of the connection portion 302 and does not expose the electrode layer connected to the island body 301. And the passivation layer 108 includes a barrier portion 1081, and the barrier portion 1081 is located in the hollow portion 303 and connected to the electrode layer and a portion (e.g., the first semiconductor layer) exposed by the hollow portion 303. The barrier portion 1081 may prevent the bump material flowing into the hollow portion 303 from contacting the electrode layer during the process of reflowing the bump material, so that the island body 301 and the electrode layer may be better separated, and the barrier portion 1081 may be formed together when the passivation layer is disposed, thereby facilitating the manufacturing process.

According to an embodiment of the present disclosure, the micro LED chip may further include: an under bump metallization layer 109 disposed on the exposed portion of the contact hole 40, and the metal bump 111 is disposed on the under bump metallization layer 109. Specifically, the under bump metallization layer 109 may be provided on the island body 301 at the contact hole 40 corresponding to the cathode layer 1072, and of course may be provided on the island body 301 and a part of the connection portion 302, but may not be provided on the cathode layer 1072 to which the island body 301 is connected. An under bump metallization layer 109 may be disposed on a portion of the anode layer 1071 at the contact hole 40 corresponding to the anode layer 1071. Preferably, the material of the metal bump 111 includes indium.

According to the technical scheme of the disclosure, the under bump metallization layer is arranged on the exposed part of the contact hole, particularly the island structure, and then the metal bump is arranged on the under bump metallization layer, so that the permeation of a bump material to an electrode layer in the backflow process can be further prevented in the forming process of the metal bump.

It is noted that any relevant description (including but not limited to technical features and their roles, explanations, etc.) regarding the structure of the micro LED chip in the above-mentioned micro LED chip preparation method can be applied to the micro LED chip of the present disclosure.

The present disclosure also provides a display device. The display device includes the above-described micro LED chip, which may include an array of light emitting units such as pixel units, for example, an array corresponding to the above-described array of anode corresponding portions. The display device may be, for example, a display screen applied to an electronic apparatus. The electronic device may include: any equipment with a display screen, such as a smart phone, a smart watch, a notebook computer, a tablet computer, a vehicle event data recorder, a navigator and the like.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A micro LED chip, wherein the micro LED chip comprises:

a mesa structure formed by etching the micro LED epitaxial wafer;

an electrode layer disposed on the mesa structure and including an island structure including an island body and a connection portion, the island body being spaced apart from the electrode layer and connected by the connection portion;

a passivation layer disposed on the electrode layer and including a plurality of contact holes, at least some of which expose portions including at least a portion of the island body and not including the electrode layer connected to the island body;

and a metal bump disposed on a portion where the plurality of contact holes are exposed.

2. The micro LED chip of claim 1, wherein said mesa structure is a common cathode structure and comprises a cathode counterpart and a plurality of anode counterparts.

3. The micro LED chip of claim 2, wherein said electrode layers comprise a cathode layer and an anode layer, said micro LED chip further comprising:

a current diffusion layer disposed on the anode counterpart, and the anode layer is disposed on the current diffusion layer, and the cathode layer is disposed on the cathode counterpart.

4. The micro LED chip of claim 3, wherein the anode layer and the cathode layer each comprise the island structure, the exposed portion of the contact hole comprising at least a portion of the island body and not comprising an electrode layer connected to the island body.

5. The micro LED chip of claim 3, wherein only the cathode layer comprises the island structures, the exposed portion of the contact hole in the passivation layer corresponding to the cathode layer comprises at least a portion of the island body and does not comprise the cathode layer connected to the island body, and the exposed portion of the contact hole in the passivation layer corresponding to the anode layer comprises a portion of the anode layer.

6. The micro LED chip of claim 1, wherein the micro LED chip further comprises:

an under bump metallization layer disposed on the portion of the contact hole exposed, and the metal bump is disposed on the under bump metallization layer.

7. The micro LED chip of claim 1, wherein a material of said metal bump comprises indium.

8. The micro LED chip of any one of claims 1 to 7, wherein the island structure further comprises a hollowed-out portion separating the island body from the electrode layer, the hollowed-out portion penetrating the electrode layer.

9. The micro LED chip of claim 8, wherein a shape of the island structure in a cross-section parallel to the electrode layer surface comprises a square, a shape of the island body in the cross-section comprises a square, the connection portion connects four corners of the island body having a square cross-section with the electrode layer, and a shape of the hollowed-out portion in the cross-section comprises a trapezoidal shape.

10. The micro LED chip of claim 9, wherein the contact hole is circular or square in shape in cross-section parallel to the electrode layer surface, the size of the contact hole being larger than the size of the island body and smaller than the size of the island structure.

11. The micro LED chip of claim 10, wherein said passivation layer comprises a barrier portion in said hollowed-out portion and connected to said electrode layer and to portions of said hollowed-out portion exposed.

12. The micro LED chip of claim 2, wherein the anode counterpart comprises, in order from bottom to top, a substrate, a buffer layer, a first semiconductor layer, a multi-layer quantum well structure, and a second semiconductor layer, and the cathode counterpart comprises, in order from bottom to top, a substrate, a buffer layer, and a first semiconductor layer.

13. The micro LED chip of claim 12, wherein said first semiconductor layer is an N-GaN layer, said second semiconductor layer is a P-GaN layer, and said N-GaN layer of said cathode counterpart and said N-GaN layers of said plurality of anode counterparts are the same semiconductor layer.

14. A display device, wherein the display device comprises the micro LED chip of any one of claims 1 to 13.