CN216561768U - Interface control circuit, integrated circuit and electronic equipment - Google Patents
Interface control circuit, integrated circuit and electronic equipment Download PDFInfo
- Publication number
- CN216561768U CN216561768U CN202122450741.8U CN202122450741U CN216561768U CN 216561768 U CN216561768 U CN 216561768U CN 202122450741 U CN202122450741 U CN 202122450741U CN 216561768 U CN216561768 U CN 216561768U
- Authority
- CN
- China
- Prior art keywords
- circuit
- signal
- channel
- interface
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
Abstract
The utility model discloses an interface control circuit, an integrated circuit and electronic equipment, wherein the interface control circuit comprises an interface circuit, a capacitance isolation channel, a signal transmission channel, a channel switching circuit and a receiving circuit. The capacitance isolation channel is connected to the interface circuit and comprises a signal node; one end of the signal transmission channel is connected with the interface circuit, and the other end of the signal transmission channel is connected with the signal node; the channel switching circuit is connected with the capacitance isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node. The interface control circuit provided by the utility model can inhibit the direct current component offset of the input signal and improve the accuracy of signal transmission.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to an interface control circuit, an integrated circuit, and an electronic device.
Background
Type-C is increasingly widely used in mobile terminals. When the traditional Type-C controller works, because the current is large and direct current offset can be generated, the judgment of a back-end system is easy to cause errors, and the accuracy of signal transmission of the Type-C controller is low.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, the present invention provides an interface control circuit, an integrated circuit and an electronic device to solve the above problems of the prior art.
The embodiment of the utility model provides an interface control circuit, which comprises an interface circuit, a capacitance isolation channel, a signal transmission channel, a channel switching circuit and a receiving circuit. The capacitance isolation channel is connected to the interface circuit and comprises a signal node; one end of the signal transmission channel is connected with the interface circuit, and the other end of the signal transmission channel is connected with the signal node; the channel switching circuit is connected with the capacitance isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node.
In some embodiments, a capacitive isolation channel includes a capacitance and a first comparator. One end of the capacitor is connected to the interface circuit, and the other end of the capacitor is connected to the output end of the first comparator; and the other end of the capacitor is a signal node.
In some embodiments, the interface control circuitry further comprises enable control circuitry. The enable control circuit is connected to an enable end of the first comparator.
In some embodiments, the enable control circuit includes a nand gate circuit and an inverter. The input end of the inverter is connected with the output end of the NAND gate circuit, and the output end of the inverter is connected with the enabling end of the first comparator.
In some embodiments, the channel switching circuit includes a first switch and a second switch. The first switch is arranged in the capacitance isolation channel, wherein one end of the first switch is connected to the output end of the first comparator, and the other end of the first switch is connected to the signal node; the second switch is arranged in the signal transmission channel, wherein one end of the second switch is connected to the interface circuit, and the other end of the second switch is connected to the signal node.
In some embodiments, the first switch comprises a first transmission gate connected between the output of the first comparator and the signal node; the second switch includes a second transmission gate connected between the interface circuit and the signal node.
In some embodiments, the receiving circuit comprises a second comparator. The first input end of the second comparator is connected to the signal node, and the second input end of the second comparator is used for receiving a preset reference voltage.
In some embodiments, the preset reference voltage includes at least two reference voltages, and the receiving circuit further includes a reference switching circuit. The reference switching circuit is connected to the second input terminal of the second comparator, and is configured to input any one of the at least two reference voltages to the second input terminal of the second comparator.
The embodiment of the utility model also provides an integrated circuit, which comprises the interface control circuit.
The embodiment of the utility model also provides electronic equipment which comprises an equipment main body and the integrated circuit arranged in the equipment main body.
The interface control circuit provided by the utility model is provided with an interface circuit, a capacitance isolation channel, a signal transmission channel, a channel switching circuit and a receiving circuit; the capacitance isolation channel is connected to the interface circuit and comprises a signal node; one end of the signal transmission channel is connected with the interface circuit, and the other end of the signal transmission channel is connected with the signal node; the channel switching circuit is connected with the capacitance isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node. The interface control circuit provided by the embodiment of the utility model can switch the transmission channel of the input signal between the capacitance isolation channel and the signal transmission channel through the channel switching circuit after receiving the input signal through the interface circuit, and when the transmission channel is switched to the capacitance isolation channel, the direct current voltage of the signal node can be maintained at a stable value, so that the stability of the direct current component in the input signal is maintained, the direct current component offset of the input signal is restrained, and the accuracy of signal transmission is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 shows a block diagram of an interface control circuit according to an embodiment of the present invention.
Fig. 2 shows another block diagram of the interface control circuit shown in fig. 1.
Fig. 3 is a schematic circuit diagram of an interface control circuit according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
The following disclosure provides many different embodiments or examples for implementing different features of the utility model. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Type-C is increasingly widely used in mobile terminals. When the traditional Type-C controller works, because the current is large and direct current offset can be generated, the judgment of a back-end system is easy to cause line errors, and the accuracy of signal transmission of the Type-C controller is low.
In order to solve the above technical problems, the inventors have made a long-term study and propose an interface control circuit, an integrated circuit, and an electronic device in an embodiment of the present invention, where the interface control circuit is provided with an interface circuit, a capacitive isolation channel, a signal transmission channel, a channel switching circuit, and a receiving circuit; wherein the capacitive isolation channel is connected to the interface circuit and includes a signal node; one end of the signal transmission channel is connected with the interface circuit, and the other end of the signal transmission channel is connected with the signal node; the channel switching circuit is connected with the capacitance isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node. The interface control circuit provided by the embodiment of the utility model can switch the transmission channel of the input signal between the capacitance isolation channel and the signal transmission channel through the channel switching circuit after receiving the input signal through the interface circuit, and when the transmission channel is switched to the capacitance isolation channel, the direct current voltage of the signal node can be maintained at a stable value, so that the stability of the direct current component in the input signal is maintained, the direct current component offset of the input signal is restrained, and the accuracy of signal transmission is improved.
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
As shown in fig. 1, an interface control circuit 10 provided by the present invention includes an interface circuit 11, a capacitive isolation channel 13, a signal transmission channel 15, a channel switching circuit 19, and a receiving circuit 17. The capacitive isolation path 13 is connected to the interface circuit 11, and the capacitive isolation path 13 includes a signal node 131, and the signal node 131 is connected to the receiving circuit 17. One end of the signal transmission path 15 is connected to the interface circuit 11, and the other end is connected to the signal node 131. The channel switching circuit 19 is connected to the capacitive isolation channel 13 and the signal transmission channel 15, and the input terminal of the receiving circuit 17 is connected to the signal node 131.
In this embodiment, the interface circuit 11 may be configured to connect to an external interface and receive an input signal through the external interface, and the external interface may be a power transmission port, for example, the interface circuit 11 may be configured to connect to a Micro USB interface, a Type-C USB interface, a Lightning USB interface, or other interfaces.
By way of example, interface circuit 11 may include one or more channels, and when interface circuit 11 includes multiple configuration channels, interface circuit 11 may also include a data selector (MUX). The MUX may receive multiple input data or signals and may output any one of the multiple input data or signals. For example, when the interface circuit 11 is used to connect to a Type-C USB interface, the interface circuit 11 includes a plurality of Configuration Channels (CCs) and MUXs through which signals of the plurality of Configuration channels are selectively output. Alternatively, the MUX may be, but is not limited to, a 4-to-1 data selector, a 6-to-1 data selector, an 8-to-1 data selector, and a 16-to-1 data selector.
In some embodiments, the interface circuit 11 may be used to connect an external device. For example, when the interface circuit 11 is a USB interface, the interface circuit 11 may be connected to an external device through a USB data line. Wherein, the external device may include but is not limited to a smart phone, a tablet computer, a smart watch, a smart bracelet, an electronic scale, an earphone and an electronic paper book reader.
In this embodiment, the capacitive isolation path 13 includes a signal node 131, and the input terminal of the receiving circuit 17 is connected to the signal node 131. The capacitive isolation channel 13 may be used to provide a transmission channel for an input signal of the interface control circuit 10 such that the input signal is input from the interface circuit 11 to the receiving circuit 17. When the capacitive isolation channel 13 is turned on, the signal node 131 maintains a stable dc level, and the input signal is transmitted to the receiving circuit 17 based on the principle of charge conservation through the isolation capacitor in the capacitive isolation channel 13, while the dc level of the signal node 131 remains unchanged, so as to suppress the dc component offset of the input signal and reduce the offset of the input signal received by the receiving circuit 17.
In this embodiment, the signal transmission channel 15 may be connected to the interface circuit 11 and the signal node 131, and the signal transmission channel 15 may be used to provide another transmission channel for the signal of the interface control circuit 10 and enable the input signal to be input from the interface circuit 11 to the receiving circuit 17.
The channel switching circuit 19 is connected to the capacitive isolation channel 13 and the signal transmission channel 15, and can be used to switch the transmission channel of the input signal between the capacitive isolation channel 13 and the signal transmission channel 15. For example, when it is necessary to suppress the dc component offset of the input signal, the transmission channel of the input signal may be switched to the capacitive isolation channel 13, and when it is not necessary to suppress the dc component offset of the input signal, the transmission channel of the input signal may be switched to the signal transmission channel 15. In this embodiment, the channel switching circuit 19 can switch the transmission channel of the input signal to the capacitive isolation channel 13 as needed, so as to maintain the dc voltage of the signal node 131 at a stable value, that is, maintain the dc component in the input signal received by the receiving circuit 17 stable, thereby suppressing the dc component offset of the input signal and improving the accuracy of signal transmission.
As shown in fig. 2, in some embodiments, the capacitive isolation channel 13 may include a capacitor C and a first comparator a1, one end of the capacitor C may be connected to the interface circuit 11, and the other end of the capacitor C may be connected to the output terminal of the first comparator a 1. The other end of the capacitor C may be a signal node 131. Alternatively, the other end of the capacitor C may be directly connected to the output end of the first comparator a1, or may be indirectly connected to the output end of the first comparator a1 through another component. For example, the other end of the capacitor C may be indirectly connected to the output of the first comparator a1 through one or more switches.
The capacitive isolation channel 13 can isolate a dc component in an input signal input from the interface circuit 11 to the capacitive isolation channel 13 by the characteristic of ac blocking and dc blocking of the capacitor C. Further, the first comparator a1 may compare a predetermined input signal with a reference voltage, so that the first comparator a1 outputs a predetermined level signal to the signal node 131, and the predetermined level signal may maintain the voltage at the signal node 131 at a stable value, so as to maintain the dc component in the input signal received by the receiving circuit 17 stable, thereby providing a stable dc component to the input signal, and thus achieving suppression of the drift of the dc component of the input signal. It should be noted that the predetermined reference voltage V0 may be the same as or different from the voltage value of the predetermined input signal of the first comparator a 1.
The signal transmission path 15 can also receive an input signal input from the interface circuit 11 and can output the input signal to the receiving circuit 17. It is to be noted that the signal transmission channel 15 may be a conventional transmission channel of the interface control circuit 10.
In some embodiments, the channel switching circuit 19 may include a first switch 191 and a second switch 193. The first switch 191 may be disposed in the capacitive isolation channel 13, wherein one end of the first switch 191 may be connected to the output terminal of the first comparator a1, and the other end of the first switch 191 may be connected to the signal node 131, that is, the first switch 191 is connected in series between the output terminal of the first comparator a1 and the signal node 131. Specifically, one end of the first switch 191 may be connected to the output terminal of the first comparator a1, and the other end of the first switch 191 may be connected to the capacitor C. The second switch 193 may be provided to the signal transmission path 15, wherein one end of the second switch 193 may be connected to the interface circuit 11, and the other end of the second switch 193 may be connected to the signal node 131.
In this embodiment, the first switch 191 may be used to turn on or off the capacitive isolation channel 13, and the second switch 193 may be used to turn on or off the signal transmission channel 15. By controlling the switching state of the first switch 191 and the switching state of the second switch 193, switching between the capacitive isolation channel 13 and the signal transmission channel 15 can be achieved. For example, when the first switch 191 is closed and the second switch 193 is opened, the capacitive isolation channel 13 is turned on, and the signal transmission channel 15 is turned off, and the input signal is input to the receiving circuit 17 through the capacitive isolation channel 13; when the first switch 191 is turned off and the second switch 193 is turned on, the capacitive isolation channel 13 is turned off and the signal transmission channel 15 is turned on, and the input signal is input to the receiving circuit 17 through the signal transmission channel 15.
As shown in fig. 3, in some embodiments, the first switch 191 includes a first transmission gate, which may be connected between the output of the first comparator a1 and the signal node 131. As an example, the first transmission gate may include a first fet Q1 and a second fet Q2. A first terminal of the first fet Q1 may be connected to the output terminal of the first comparator a1, and a second terminal of the first fet Q1 may be connected to the signal node 131. A first terminal of a second fet Q2 may be connected to the output terminal of the first comparator a1, and a second terminal of the second fet Q2 may be connected to the signal node 131. Wherein, a first terminal of the first fet Q1 may be interconnected with a first terminal of the second fet Q2, and a second terminal of the first fet Q1 may be interconnected with a second terminal of the second fet Q2. In this embodiment, the channel types of the first fet Q1 and the second fet Q2 are opposite, for example, the first fet Q1 may be an N-MOS transistor, and the second fet Q2 may be a P-MOS transistor. The first and second terminals of the first fet Q1 and the second fet Q2 are source/drain electrodes, respectively. The gates of the Q1 of the first fet and the Q2 of the second fet are configured to receive a pair of control signals in opposite phases. For example, the gate of the first fet Q1 is configured to receive the first control signal ena, and the gate of the second fet Q2 is configured to receive the second control signal enb, which may be obtained by inverting the first control signal ena through the inverter a 5.
In other embodiments, the first fet Q1 and the second fet Q2 may be replaced by transistors with opposite polarities.
In some embodiments, the second switch 193 includes a second transmission gate, which may be connected between the interface circuit 11 and the signal node 131. As an example, the second transmission gate may include a third fet Q3 and a fourth fet Q4. A first terminal of the third fet Q3 may be connected to the interface circuit 11 and a second terminal of the third fet Q3 may be connected to the signal node 131. A first terminal of the fourth fet Q4 may be connected to the interface circuit 11 and a second terminal of the fourth fet Q4 may be connected to the signal node 131. Wherein, a first terminal of the third fet Q3 may be interconnected with a first terminal of the fourth fet Q4, and a second terminal of the third fet Q3 may be interconnected with a second terminal of the fourth fet Q4. In this embodiment, the channel types of the third fet Q3 and the fourth fet Q4 are opposite, for example, the third fet Q3 may be an N-MOS transistor, and the fourth fet Q4 may be a P-MOS transistor. The first end and the second end of the third fet Q3 and the fourth fet Q4 are source/drain electrodes, respectively. The gates of the third fet Q3 and the fourth fet Q4 are configured to receive a pair of control signals in opposite phases. For example, the gate of the third fet Q3 is configured to receive the first control signal ena, and the gate of the fourth fet Q4 is configured to receive the second control signal enb, which may be obtained by inverting the first control signal ena through the inverter a 5.
In other embodiments, the third fet Q3 and the fourth fet Q4 may be replaced with transistors of opposite polarity.
In some embodiments, the receiving circuit 17 may include a second comparator a2, wherein a first input terminal of the second comparator a2 is connected to the signal node 131, a second input terminal of the second comparator a2 is configured to receive a preset Reference Voltage (VREF), and the second comparator a2 is configured to compare the input signal with the preset Reference Voltage VREF.
In some embodiments, the preset reference voltage VREF may include at least two reference voltages, and the receiving circuit 17 may further include a reference switching circuit 171. The reference switching circuit 171 is connected to a second input terminal of the second comparator a2, and inputs any one of at least two reference voltages. Further, the second comparator a2 is used to compare the preset reference voltage V0 with any one of at least two reference voltages. By switching different preset reference voltages VREF, the generation of idle noise can be suppressed when the receiving circuit 17 works, and the accuracy of signal transmission of the interface control circuit 10 is ensured.
In some embodiments, the interface control circuit 10 may further include an enable control circuit 12, wherein the enable control circuit 12 is connected to an enable terminal of the first comparator a1 and is configured to control the first comparator a1 to turn off when the dc voltage at the signal node 131 maintains a stable value, so as to reduce power consumption of the interface control circuit 10.
In some embodiments, the enable control circuit 12 may include a nand gate circuit A3 and an inverter a 4. The output end of the nand gate circuit A3 is connected to the input end of the inverter a4, and the output end of the inverter a4 is connected to the enable end of the first comparator a 1.
As an example, the working principle of the interface control circuit 10 will be explained in detail below with reference to fig. 3.
The interface control circuit 10 may be controlled by a pair of inverted control signals (a first control signal ena and a second control signal enb), and the second control signal enb may be generated by the first control signal ena through an inverter, and specifically, the first control signal ena may be input to the inverter a5 to obtain the second control signal enb.
Furthermore, the first field effect transistor Q1 is an N-MOS transistor, the second field effect transistor Q2 is a P-MOS transistor, the third field effect transistor Q3 is a P-MOS transistor, and the third field effect transistor Q4 is an N-MOS transistor. The first fet Q1 and the third fet Q3 are controlled by a first control signal ena, and the second fet Q2 and the fourth fet Q4 are controlled by a second control signal enb. Further, the nand gate a3 can be controlled by an enable signal EN and the first control signal ena.
In the initial stage, the first control signal ena is at a high level, the second control signal enb is at a low level, and the enable signal EN is at a low level. At this time, the first fet Q1 and the second fet Q2 are turned on, and the third fet Q3 and the fourth fet Q4 are turned off. That is, the capacitive isolation path 13 is enabled, the signal transmission path 15 is closed, the transmission path of the input signal is switched to the capacitive isolation path 13, and the input signal is input to the second comparator a2 through the capacitive isolation path 13. Meanwhile, when the enable signal EN is at a low level and the first control signal ena is at a high level, the enable control circuit 12 inputs a low level signal to the enable terminal of the first comparator a1 to enable the first comparator a 1. During the transmission of the input signal through the capacitive isolation channel 13, the capacitor C may isolate the dc component of the input signal by the ac blocking characteristic of the capacitor C, and the first comparator a1 compares a preset input signal with a reference voltage, so that the first comparator a1 outputs a preset level signal to the signal node 131, and the preset level signal maintains the voltage at the signal node 131 at a stable value, so that the dc component in the input signal received by the receiving circuit 17 is stable, which is equivalent to providing a stable dc component for the input signal, thereby achieving the suppression of the offset of the dc component of the input signal and improving the accuracy of the input signal transmission.
In some embodiments, during the transmission of the input signal through the capacitive isolation channel 13, the enable signal EN may transition from a low level to a high level, where both the enable signal EN and the first control signal ena are at a high level, and the enable control circuit 12 outputs a high level signal to the enable terminal of the first comparator a1, so that the first comparator a1 is turned off. When the first comparator a1 is turned off, the interface control circuit 10 can save power consumption.
When the first control signal ena changes from high level to low level, the second control signal enb is high level. At this time, the first fet Q1 and the second fet Q2 are turned off, and the third fet Q3 and the fourth fet Q4 are turned on. That is, the capacitive isolation channel 13 is closed, the signal transmission channel 15 is activated, the transmission channel of the input signal is switched to the signal transmission channel 15, and the input signal is input to the second comparator a2 through the signal transmission channel 15.
In some embodiments, after the input signal is input to the second comparator a2, the reference switching circuit 171 may switch the different preset reference voltage VREF of the second comparator a2, so as to suppress the generation of idle noise, and further ensure the accuracy of the signal transmission of the interface control circuit 10.
The interface control circuit provided by the embodiment of the utility model is provided with an interface circuit, a capacitance isolation channel, a signal transmission channel, a channel switching circuit and a receiving circuit; the capacitance isolation channel is connected to the interface circuit and comprises a signal node; one end of the signal transmission channel is connected with the interface circuit, and the other end of the signal transmission channel is connected with the signal node; the channel switching circuit is connected with the capacitance isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node. The interface control circuit provided by the embodiment of the utility model can switch the transmission channel of the input signal between the capacitance isolation channel and the signal transmission channel through the channel switching circuit after receiving the input signal through the interface circuit, and when the transmission channel is switched to the capacitance isolation channel, the direct current voltage of the signal node can be maintained at a stable value, so that the stability of the direct current component in the input signal is maintained, the direct current component offset of the input signal is restrained, and the accuracy of signal transmission is improved.
The present invention also provides an integrated circuit comprising the above-mentioned interface control circuit 10.
The integrated circuit provided by the embodiment of the utility model is provided with an interface circuit, a capacitance isolation channel, a signal transmission channel, a channel switching circuit and a receiving circuit; the capacitance isolation channel is connected to the interface circuit and comprises a signal node; one end of the signal transmission channel is connected with the interface circuit, and the other end of the signal transmission channel is connected with the signal node; the channel switching circuit is connected with the capacitance isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node. The interface control circuit provided by the embodiment of the utility model can switch the transmission channel of the input signal between the capacitance isolation channel and the signal transmission channel through the channel switching circuit after receiving the input signal through the interface circuit, and when the transmission channel is switched to the capacitance isolation channel, the direct current voltage of the signal node can be maintained at a stable value, so that the stability of the direct current component in the input signal is maintained, the direct current component offset of the input signal is restrained, and the accuracy of signal transmission is improved.
The utility model also provides an electronic device, which may include a device body and the integrated circuit provided in the above embodiment, wherein the integrated circuit is disposed in the device body, and the device body may be configured to provide a mounting carrier for the integrated circuit.
In this embodiment, the electronic device may be any one of a number of electronic devices including, but not limited to, a mobile power source, a charging cradle, an adapter, an in-vehicle charger, a cellular telephone, a smart phone, other wireless communication device, a personal digital assistant, an audio player, other media player, a music recorder, a video recorder, a camera, other media recorder, a radio, a wearable device (e.g., a Head Mounted Device (HMD) such as electronic eyewear, electronic clothing, an electronic bracelet, an electronic necklace, an electronic tattoo or a smartwatch, etc.), a medical device, a vehicle transportation instrument, a calculator, a programmable remote controller, a pager, a laptop computer, a desktop computer, a printer, a netbook computer, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a motion picture experts group (MPEG-1 or MPEG-2) audio layer 3(MP3) player, a mobile phone, a Personal Digital Assistant (PDA), a mobile phone, a personal digital assistant, a, Portable medical devices, and digital cameras and combinations thereof.
The electronic equipment provided by the embodiment of the utility model is provided with an interface circuit, a capacitance isolation channel, a signal transmission channel, a channel switching circuit and a receiving circuit; the capacitance isolation channel is connected to the interface circuit and comprises a signal node; one end of the signal transmission channel is connected with the interface circuit, and the other end of the signal transmission channel is connected with the signal node; the channel switching circuit is connected with the capacitance isolation channel and the signal transmission channel; the input end of the receiving circuit is connected to the signal node. The interface control circuit provided by the embodiment of the utility model can switch the transmission channel of the input signal between the capacitance isolation channel and the signal transmission channel through the channel switching circuit after receiving the input signal through the interface circuit, and when the transmission channel is switched to the capacitance isolation channel, the direct current voltage of the signal node can be maintained at a stable value, so that the stability of the direct current component in the input signal is maintained, the direct current component offset of the input signal is restrained, and the accuracy of signal transmission is improved.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it is to be understood that the terms "length," "above," "front," "top," "inner," "outer," and the like are used in the orientations and positional relationships indicated in the drawings, which are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be construed broadly, e.g., as being fixed or detachable or integrally connected; may be mechanically or electrically connected or may communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "above" the second feature may comprise the first and second features being in direct contact, or the first and second features being in contact, not directly, but via another feature therebetween. Also, the first feature "over" the second feature may include the first feature being directly over and obliquely above the second feature, or may simply mean that the first feature is at a higher level than the second feature.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the utility model, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. An interface control circuit, comprising:
an interface circuit;
a capacitive isolation channel connected to the interface circuit, the capacitive isolation channel including a signal node;
one end of the signal transmission channel is connected to the interface circuit, and the other end of the signal transmission channel is connected to the signal node;
the channel switching circuit is connected to the capacitance isolation channel and the signal transmission channel; and
and the input end of the receiving circuit is connected to the signal node.
2. The interface control circuit of claim 1 wherein said capacitive isolation path comprises a capacitor and a first comparator, one end of said capacitor being connected to said interface circuit and the other end of said capacitor being connected to an output of said first comparator; and the other end of the capacitor is the signal node.
3. The interface control circuit of claim 2, wherein the interface control circuit further comprises:
and the enabling control circuit is connected to the enabling end of the first comparator.
4. The interface control circuit of claim 3, wherein the enable control circuit comprises:
a NAND gate circuit; and
and the input end of the inverter is connected to the output end of the NAND gate circuit, and the output end of the inverter is connected to the enabling end of the first comparator.
5. The interface control circuit of claim 2, wherein the channel switching circuit comprises:
the first switch is arranged in the capacitive isolation channel, wherein one end of the first switch is connected to the output end of the first comparator, and the other end of the first switch is connected to the signal node; and
and the second switch is arranged in the signal transmission channel, wherein one end of the second switch is connected to the interface circuit, and the other end of the second switch is connected to the signal node.
6. The interface control circuit of claim 5, wherein the first switch comprises a first transmission gate connected between the output of the first comparator and the signal node;
the second switch includes a second transmission gate connected between the interface circuit and the signal node.
7. Interface control circuit according to any of claims 1 to 6, characterized in that the receiving circuit comprises:
and a first input end of the second comparator is connected to the signal node, and a second input end of the second comparator is used for receiving a preset reference voltage.
8. The interface control circuit of claim 7, wherein the preset reference voltage comprises at least two reference voltages, and wherein the receiving circuit further comprises:
and the reference switching circuit is connected to the second input end of the second comparator and is used for inputting any one of the at least two reference voltages to the second input end of the second comparator.
9. An integrated circuit comprising an interface control circuit as claimed in any one of claims 1 to 8.
10. An electronic device comprising a device body and the integrated circuit of claim 9 disposed within the device body.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122450741.8U CN216561768U (en) | 2021-10-11 | 2021-10-11 | Interface control circuit, integrated circuit and electronic equipment |
| PCT/CN2022/120278 WO2023061171A1 (en) | 2021-10-11 | 2022-09-21 | Interface control circuit, integrated circuit, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122450741.8U CN216561768U (en) | 2021-10-11 | 2021-10-11 | Interface control circuit, integrated circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216561768U true CN216561768U (en) | 2022-05-17 |
Family
ID=81566194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122450741.8U Active CN216561768U (en) | 2021-10-11 | 2021-10-11 | Interface control circuit, integrated circuit and electronic equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN216561768U (en) |
| WO (1) | WO2023061171A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023061171A1 (en) * | 2021-10-11 | 2023-04-20 | 芯海科技（深圳）股份有限公司 | Interface control circuit, integrated circuit, and electronic device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4673872B2 (en) * | 2007-06-29 | 2011-04-20 | 富士通テン株式会社 | Interface circuit |
| CN106874233B (en) * | 2017-02-16 | 2018-10-19 | 维沃移动通信有限公司 | A kind of Type-C interface control circuits, control method and mobile terminal |
| CN212112455U (en) * | 2020-05-19 | 2020-12-08 | 广州视源电子科技股份有限公司 | Type-c interface circuit, chip and electronic equipment |
| CN212649180U (en) * | 2020-06-22 | 2021-03-02 | 广东高普达集团股份有限公司 | Double-interface switching circuit and Type-C concentrator |
| CN112688542B (en) * | 2021-01-06 | 2022-04-29 | 矽力杰半导体技术(杭州)有限公司 | Control circuit and switching converter using same |
| CN216561768U (en) * | 2021-10-11 | 2022-05-17 | 芯海科技（深圳）股份有限公司 | Interface control circuit, integrated circuit and electronic equipment |
-
2021
- 2021-10-11 CN CN202122450741.8U patent/CN216561768U/en active Active
-
2022
- 2022-09-21 WO PCT/CN2022/120278 patent/WO2023061171A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023061171A1 (en) * | 2021-10-11 | 2023-04-20 | 芯海科技（深圳）股份有限公司 | Interface control circuit, integrated circuit, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023061171A1 (en) | 2023-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111130596B (en) | Multiplexing circuit, interface circuit system and mobile terminal | |
| US8829979B2 (en) | Power-efficient multi-mode charge pump | |
| US9184712B2 (en) | Low power high-speed digital receiver | |
| US9252775B2 (en) | High-voltage level-shifter | |
| US11287452B2 (en) | Low power comparator and self-regulated device | |
| US20220271558A1 (en) | Charging circuit and electronic device | |
| CN109491942B (en) | Multiplexing circuit and mobile terminal | |
| KR100480261B1 (en) | Apparatus for supplying power to mobile phone using earphone-microphone connector | |
| CN101965684A (en) | Level shifting circuit and method | |
| CN216561768U (en) | Interface control circuit, integrated circuit and electronic equipment | |
| CN107070444B (en) | Non-volatile ferroelectric logic with fine-grained power gating | |
| EP3062188B1 (en) | Multi-supply sequential logic unit | |
| EP2974015B1 (en) | Circuit and method to extend a signal comparison voltage range | |
| CN104205650A (en) | Inverter-and-switched-capacitor-based squelch detector apparatus and method | |
| JP2005295683A (en) | Portable terminal apparatus | |
| CN112740559A (en) | Transmitter with feedback control | |
| EP3968491A1 (en) | Charging circuit, charging chip, mobile terminal, and charging system | |
| CN111934035B (en) | Voltage detection chip, battery and electronic equipment | |
| CN112003458B (en) | Access pipe control circuit, power management chip and power device | |
| US20210157391A1 (en) | True power shedding | |
| US8742820B1 (en) | Power circuit and wireless network adapter | |
| JPH08228143A (en) | Level converting circuit | |
| CN108462485B (en) | Time delay circuit and electronic device | |
| TW201233054A (en) | Operational amplifier device | |
| TW541778B (en) | Power supply control device for electronic device equipped with multiple batteries |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |