CN216411817U - Liquid crystal display device with dot inversion - Google Patents

Abstract

The application discloses a liquid crystal display device with dot inversion, which comprises a plurality of data lines and a plurality of sub-pixels. Each sub-pixel comprises a first thin film transistor, a second thin film transistor and a capacitor which are sequentially arranged in different areas, the drain electrode of the first thin film transistor is connected with one end of the capacitor connected with an alternating current common voltage, and the first thin film transistor and the second thin film transistor are arranged in the same direction. The adjacent sub-pixels in the same row have the same structure, the adjacent sub-pixels in the same row have the inverted structure, and the source electrodes of the first and second thin film transistors of the sub-pixels in the same row are connected with the same data line. The second thin film transistor of the sub-pixel in the same row and odd column is connected with the first thin film transistor of the sub-pixel in the even column through a grid, and the first thin film transistor of the sub-pixel in the same row and odd column is connected with the second thin film transistor of the sub-pixel in the even column through a grid.

Description

Liquid crystal display device with dot inversion

Technical Field

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device with dot inversion.

Background

The conventional method of driving the liquid crystal display device includes: an alternating common voltage (AC-Vcom) drive mode and a direct common voltage (DC-Vcom) drive mode. In the dc common voltage driving mode, the magnitude of the common voltage (Vcom) is kept constant, and only by varying the magnitude of the data driving signal, for example: the magnitude of the common Voltage is 5 volts (V) and the magnitude of the data driving signal is 10V or 0V, so as to achieve the Voltage difference (i.e. 5V) and the positive and negative polarities of the display electrodes. In the ac common voltage driving mode, the magnitudes of the common voltage and the data driving signal are varied, for example: when the common voltage is 0V, the data driving signal is 5V, or when the common voltage is 5V, the data driving signal is 0V, and the voltage difference (i.e., 5V) and the positive and negative polarities of the display electrodes can be achieved by the voltages varied between the two voltages.

As can be seen from the above, the data driving signal required by the dc common voltage driving mode has a large magnitude, which means that the power consumption is also large, and the corresponding Integrated Circuit (IC) design is also complicated, so the ac common voltage driving mode has better application advantages.

However, in the reflective, micro-reflective, or transflective display panel based on the ac common voltage driving mode, the voltage of the data signal in the original pixel arrangement is limited, and only frame inversion (frame inversion) and row inversion (row inversion) can be implemented, so that the obvious scan line is easily perceived by human eyes when the refresh frequency is very low.

Therefore, it is an urgent need in the art to provide a liquid crystal display device based on an ac common voltage driving mode, which can achieve dot inversion (dot inversion) with optimal visual effect and eliminate the problem of visual reflection scan lines.

SUMMERY OF THE UTILITY MODEL

The present disclosure provides a liquid crystal display device with dot inversion, which solves the problem of reflective scanning lines in the prior art when the liquid crystal display device based on the ac common voltage driving mode faces an extremely low refresh frequency.

In order to achieve the above object, the present application is realized by:

the application provides a liquid crystal display device with dot inversion, which comprises: the pixel structure comprises M data lines, a plurality of sub-pixels, N first gate lines and N second gate lines, wherein the sub-pixels are arranged into M rows and N columns, and M and N are positive integers. Each sub-pixel comprises: the first thin film transistor is arranged in the first area, the second thin film transistor is arranged in the second area, and the capacitor is arranged in the third area, wherein the second area is arranged between the first area and the third area, the configuration directions of the first thin film transistor and the second thin film transistor are the same, the source electrode of the first thin film transistor is electrically connected with the source electrode of the second thin film transistor, the drain electrode of the first thin film transistor is electrically connected with one end of the capacitor, and the other end of the capacitor is electrically connected with the alternating current common voltage. The arrangement structures of the adjacent sub-pixels positioned in the same column are the same, and the arrangement structure of any sub-pixel positioned in the same row after vertically overturning along the horizontal direction is the same as the arrangement structure of the adjacent sub-pixel. The source electrode of the first thin film transistor and the source electrode of the second thin film transistor of the sub-pixels positioned in the same column are connected with the same data line. The N first gate lines are used for respectively connecting the grid electrodes of the second thin film transistors of the sub-pixels positioned in the same row and odd-numbered columns and the grid electrodes of the first thin film transistors of the sub-pixels positioned in the even-numbered columns, and the N second gate lines are used for respectively connecting the grid electrodes of the first thin film transistors of the sub-pixels positioned in the same row and odd-numbered columns and the grid electrodes of the second thin film transistors of the sub-pixels positioned in the even-numbered columns.

In the present application, the liquid crystal display device with dot inversion is designed by a layout of two-cut-three sub-pixels (i.e. each sub-pixel includes a first thin film transistor disposed in a first area, a second thin film transistor disposed in a second area, and a capacitor disposed in a third area, wherein the first thin film transistor and the second thin film transistor are disposed in the same direction), the arrangement structures of the sub-pixels adjacent to each other in the same row are the same, and the arrangement structures of the sub-pixels adjacent to each other in the same row are in an inverted configuration, such that the gate of the second thin film transistor of the sub-pixel located in the odd-numbered column of the same row is connected to the gate of the first thin film transistor of the sub-pixel located in the even-numbered column of the same row and the gate of the first thin film transistor of the sub-pixel located in the odd-numbered column of the same row is connected to the gate of the second thin film transistor of the sub-pixel located in the even-numbered column of the same row (the layout of the gate lines can shorten the length of the gate lines, and avoid the overlap between the gate lines) to realize the dot inversion with the best visual effect in the low-frequency and low-power consumption AC common voltage driving mode, thereby improving the problem of visual reflection scanning lines caused by low-frequency driving without increasing the number of processing channels and the number of photomasks.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a schematic layout view of an embodiment of a liquid crystal display device with dot inversion according to the present application;

FIG. 2 is a schematic sectional view taken along line AA' of FIG. 1;

FIG. 3 is a waveform diagram of an AC common voltage and a gate driving signal of the liquid crystal display device with dot inversion of FIG. 1 during a frame period;

FIG. 4 is a schematic diagram of pixel polarities of one embodiment of the dot inversion LCD device of FIG. 1 displaying a frame;

FIG. 5 is a schematic diagram of pixel polarities of another frame displayed by the dot inversion LCD device of FIG. 1; and

FIG. 6 is a schematic layout view of another embodiment of a liquid crystal display device with dot inversion according to the present application.

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same or similar components or process flows.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, values, method steps, operations, components, and/or components, but do not preclude the presence or addition of further features, values, method steps, operations, components, and/or groups thereof.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Please refer to fig. 1, which is a schematic layout diagram of an embodiment of a liquid crystal display device with dot inversion according to the present application. As shown in fig. 1, in the present embodiment, the liquid crystal display device 100 with dot inversion includes: the liquid crystal display device includes M data lines 110, a plurality of subpixels 120 arranged in M rows and N columns, N first gate lines 130, and N second gate lines 140, where M and N are positive integers. The dot inversion lcd device 100 shown in fig. 1 is illustrated as including 8 sub-pixels 120 (i.e., 2 × 4 array, 4 rows and 2 columns, M is 4, and N is 2), 4 data lines 110, 2 first gate lines 130, and 2 second gate lines 140, where the number of the actual data lines 110, the first gate lines 130, and the second gate lines 140, the number of the sub-pixels 120, and the arrangement thereof can be adjusted according to actual requirements. In addition, the plurality of sub-pixels 120 may be, but not limited to, reflective sub-pixels, but the embodiment is not limited to the application; for example, the plurality of sub-pixels 120 may include a micro-reflective sub-pixel, a transflective sub-pixel, or a combination thereof. It should be noted that, in order to show the arrangement structure of the plurality of sub-pixels 120, fig. 1 omits a substrate, an organic layer, a transparent conductive layer and a reflective layer that may be included in the liquid crystal display device 100 with dot inversion.

In addition, 4 data lines 110, 8 sub-pixels 120, 2 first gate lines 130, and 2 second gate lines 140 are disposed on the substrate. The substrate may include a light-transmitting material having flexibility, such as: acrylic-based resin (acryl-based resin), methacrylic-based resin (methacryl-based resin), polyisoprene (polyisoprene), vinyl-based resin (vinyl-based resin), epoxy-based resin (epoxy-based resin), urethane-based resin (urethane-based resin), silicone-based resin (siloxane-based resin), polyimide-based resin (polyimide-based resin), or polyamide-based resin (polyamide-based resin), or a light-transmitting material having rigidity, for example: a glass substrate or a quartz substrate.

Referring to fig. 1 and fig. 2, fig. 2 is a schematic cross-sectional view along line AA' of fig. 1, wherein fig. 2 is a cross-sectional view of an embodiment of the sub-pixel 120 of fig. 1 along a vertical direction of the drawing plane of fig. 1. As shown in fig. 1 and 2, each subpixel 120 includes: a first thin film transistor 50 disposed in the first region 210, a second thin film transistor 60 disposed in the second region 220, and a capacitor 70 disposed in the third region 230. In each sub-pixel 120, the second region 220 is disposed between the first region 210 and the third region 230, the first thin film transistor 50 and the second thin film transistor 60 are disposed in the same direction, the first thin film transistor 50 includes a source S1, a drain D1 and a gate G1, the second thin film transistor 60 includes a source S2, a drain D2 and a gate G2, the source S1 of the first thin film transistor 50 is electrically connected to the source S2 of the second thin film transistor 60, the drain D1 of the first thin film transistor 50 is electrically connected to one end of the capacitor 70, and the other end of the capacitor 70 is electrically connected to the ac common voltage Vcom through the voltage line 10. The first thin film transistor 50 is disposed in a direction in which a connection line between the source S1 and the drain D1 points to the capacitor 70, and the second thin film transistor 60 is disposed in a direction in which a connection line between the source S2 and the drain D2 points to the capacitor 70.

In the present embodiment, the sub-pixels 120 include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, and each sub-pixel 120 is a two-to-three sub-pixel (i.e., each sub-pixel 120 includes a first thin film transistor 50 disposed in the first region 210, a second thin film transistor 60 disposed in the second region 220, and a capacitor 70 disposed in the third region 230) for displaying a gray-scale image.

In each sub-pixel 120, the gate G1 and the gate G2 may be formed by the same patterned conductive layer, and the gate G1 and the gate G2 may be made of aluminum, platinum, silver, titanium, molybdenum, zinc, tin and/or combinations thereof, but are not limited thereto. The thin plate conductor 71 of the source S1, the drain D1, the source S2, the drain D2, and the capacitor 70 connected to the drain D1 may be formed of the same patterned conductive layer, and may include the same or different material as the gate G1 and the gate G2. In addition, the first thin film transistor 50 may further include a channel layer SE1 and a gate insulating layer GI1, and the second thin film transistor 60 may further include a channel layer SE2 and a gate insulating layer GI 2; the channel layer SE1 and the channel layer SE2 may be formed of the same layer of patterned semiconductor, and the channel layer SE1 and the channel layer SE2 may be made of silicon (e.g., amorphous silicon, polycrystalline silicon, or single crystal silicon), an oxide semiconductor (e.g., indium oxide, gallium oxide, zinc oxide, indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide), an organic semiconductor, or other semiconductor materials; the dielectric DE, the gate insulating layer GI1, and the gate insulating layer GI2 of the capacitor 70 may be formed by a same patterned conductive layer, and the dielectric DE, the gate insulating layer GI1, and the gate insulating layer GI2 of the capacitor 70 may include inorganic materials (e.g., silicon nitride, silicon oxide, silicon oxynitride), organic materials (e.g., polyimide, polyester, polymethyl methacrylate (PMMA), polyvinyl phenol (poly (4-vinylphenol), PVP), polyvinyl alcohol (PVA), Polytetrafluoroethylene (PTFE)), but are not limited thereto.

In one embodiment, the liquid crystal display device 100 with dot inversion may further include an organic layer OL disposed on the first thin film transistor 50, the second thin film transistor 60 and the capacitor 70 and having a plurality of contact holes 90, a transparent conductive layer PE disposed on the organic layer OL, and a reflective layer RE disposed on the transparent conductive layer PE and disposed at the same position as the transparent conductive layer PE. The organic layer OL may be made of polyimide-based resin, epoxy-based resin or acryl-based resin, the transparent conductive layer PE may be made of ito or izo, and the reflective layer RE may be made of metal, metal nitride or epoxy resin.

In one embodiment, the data lines 110 and the source S1 and the drain D1 of the first tft 50 and the source S2 and the drain D2 of the second tft 60 of each sub-pixel 120 may be formed by a same patterned conductive layer, and the gate lines 130, the gate lines 140 and the gate G1 of the first tft 50 and the gate G2 of the second tft 60 of each sub-pixel 120 may be formed by a same patterned conductive layer.

In one embodiment, the first thin film transistors 50 and the second thin film transistors 60 may be oxide thin film transistors or polysilicon thin film transistors, respectively.

In one embodiment, the capacitors 70 are storage capacitors, respectively.

In the present embodiment, the adjacent sub-pixels 120 in the same column have the same arrangement structure (i.e., the arrangement structure of the sub-pixels 120 adjacent to each other in the vertical direction P in the plane of the figure is the same), and the arrangement structure of any sub-pixel 120 in the same row after being vertically inverted along the horizontal direction H is the same as the arrangement structure of its adjacent sub-pixel 120 (i.e., in the sub-pixel 120 in the same row, the arrangement structure of any sub-pixel 120 is the arrangement structure after being inverted 180 degrees from the arrangement structure of its adjacent sub-pixel 120, so that in the sub-pixel 120 in the same row, the first region 210 of any sub-pixel 120 is juxtaposed with the third region 230 of its adjacent sub-pixel 120, the second region 220 of its adjacent sub-pixel 120 is juxtaposed, the arrangement direction of the first thin film transistor 50 of any sub-pixel 120 is opposite to the arrangement direction of the first thin film transistor 50 of its adjacent sub-pixel 120, and the arrangement direction of the second thin film transistor 60 of any sub-pixel 120 is opposite to the arrangement direction of the second thin film transistor 60 of its adjacent sub-pixel 120 The arrangement direction of the tubes 60 is opposite), the source S1 of the first thin film transistor 50 and the source S2 of the second thin film transistor 60 of the sub-pixel 120 located in the same column are connected to the same data line 110.

In the present embodiment, 2 first gate lines 130 are used to connect the gates G2 of the second tfts 60 of the sub-pixels 120 in the odd-numbered columns of the same row and the gates G1 of the first tfts 50 of the sub-pixels 120 in the even-numbered columns, respectively; the 2 second gate lines 140 are used to connect the gates G1 of the first tfts 50 of the sub-pixels 120 in the odd-numbered columns of the same row and the gates G2 of the second tfts 60 of the sub-pixels 120 in the even-numbered columns, respectively. The 2 first gate lines 130 may be the first control line 310 and the fourth control line 340, respectively, and the 2 second gate lines 140 may be the second control line 320 and the third control line 330, respectively.

In one embodiment, 2 first gate lines 130 and 2 second gate lines 140 are disposed in a winding manner (as shown in fig. 1).

In one embodiment, two adjacent sub-pixels 120 in the same column form a unit 80, and the liquid crystal display device 100 with dot inversion includes a plurality of units 80 arranged in an array.

In an embodiment, the liquid crystal display device 100 with dot inversion may further include: a gate driving circuit 150, a data driving circuit 160 and a common voltage generating circuit 170, wherein the gate driving circuit 150 is electrically connected to the 2 first gate lines 130 and the 2 second gate lines 140, and is configured to provide 4 gate driving signals to the 2 first gate lines 130 and the 2 second gate lines 140, respectively (specifically, the gate driving circuit 150 outputs the gate driving signals to the 2 first gate lines 130 and the 2 second gate lines 140 according to a predetermined timing sequence, and the detailed description refers to the related description of fig. 3 later); the data driving circuit 160 is electrically connected to the 4 data lines, and is configured to provide 4 data driving signals to the 4 data lines, respectively; the common voltage generating circuit 170 is electrically connected to the plurality of capacitors 70 through the voltage line 10 for providing the ac common voltage Vcom. It should be noted that the voltage line 10, the first gate line 130 and the second gate line 140 are disposed in different metal layers in the manufacturing process. In one example, the gate driving circuit 150 may include a plurality of sub-gate driving circuits (not shown) respectively disposed on one side, two sides or a periphery of the liquid crystal display device 100 with dot inversion, that is, the gate driving circuit 150 may be in a distributed configuration.

Referring to fig. 1 and 3, fig. 3 is a waveform diagram of an ac common voltage and a gate driving signal of the liquid crystal display device with dot inversion of fig. 1 during a frame period. As shown in fig. 3, the alternating common voltage Vcom is transposed every half Frame (Frame) Frame period; the first control line 310, the second control line 320, the third control line 330 and the fourth control line 340 are sequentially turned on (i.e., the first control line 310, the second control line 320, the third control line 330 and the fourth control line 340 sequentially receive the gate driving signal). It should be noted that the Data driving signal Data received by the Data line 110 is the same as the Data driving signal of the conventional liquid crystal display device driven by the ac common voltage Vcom (in the conventional liquid crystal display device, the circuit layout of all the adjacent sub-pixels is the same), and therefore, the description thereof is omitted. During the period when the ac common voltage Vcom is a low voltage, the first control line 310 and the second control line 320 receive the gate driving signal, so that the second thin film transistor 60 and the first thin film transistor 50 connected to the first control line 310 and the capacitor 70 connected thereto are turned on based on the received Data driving signal Data, and the second thin film transistor 60 and the first thin film transistor 50 connected to the second control line 320 and the capacitor 70 connected thereto are turned on based on the received Data driving signal Data; during the period when the ac common voltage Vcom is a high voltage, the third control line 330 and the fourth control line 340 receive the gate driving signal, so that the second thin film transistor 60 and the first thin film transistor 50 connected to the third control line 330 and the capacitor 70 connected thereto, and the second thin film transistor 60 and the first thin film transistor 50 connected to the fourth control line 340 and the capacitor 70 connected thereto are turned on based on the received Data driving signal Data, and therefore, the dot inversion with the best visual effect can be achieved.

Through the layout design of the two-cut-three-sub-pixels and the layout design of the gate lines in fig. 1, in combination with the low-frequency ac common voltage driving mode and the on sequence of the control lines shown in fig. 3, the polarity of the first region 210 of each sub-pixel 120 is the same as that of the third region 230, and the polarities of the first region 210 and the third region 230 of each sub-pixel 120 are opposite to that of the second region 220, as shown in fig. 4 or fig. 5 (fig. 4 is a pixel polarity diagram of an embodiment of displaying one frame of the liquid crystal display device with dot inversion in fig. 1, and fig. 5 is a pixel polarity diagram of an embodiment of displaying another frame of the liquid crystal display device with dot inversion in fig. 1). Therefore, the liquid crystal display device 100 with dot inversion of fig. 1 can realize dot inversion and improve the problem of visual scanning lines during low-frequency driving under the premise of a low-power-consumption display panel structure that two-to-three sub-pixels display gray-scale images and low-frequency alternating current common voltage.

Please refer to fig. 6, which is a schematic layout diagram of a liquid crystal display device with dot inversion according to another embodiment of the present application. As shown in fig. 6, the difference between the liquid crystal display device 200 with dot inversion of the present embodiment and the liquid crystal display device 100 with dot inversion of fig. 1 is that 2 first gate lines 430 and 2 second gate lines 440 of the present embodiment are linearly arranged. Specifically, the first thin film transistor 50 and the second thin film transistor 60 along the two sides of the 2 first gate lines 430 and the 2 second gate lines 440 are arranged in opposite directions, so that the 2 first gate lines 430 and the 2 second gate lines 440 can be arranged in a non-bypassing manner by increasing the area of the gate of the first thin film transistor 50 and the area of the gate of the second thin film transistor 60 (i.e., increasing the area of the black block corresponding to the first thin film transistor 50 and the second thin film transistor 60 in the drawing), and the lengths of the first gate lines 430 and the second gate lines 440 can be shortened.

In summary, the liquid crystal display device with dot inversion according to the embodiment of the present application is designed by a layout of two-cut three sub-pixels (i.e. each sub-pixel includes a first thin film transistor disposed in a first area, a second thin film transistor disposed in a second area, and a capacitor disposed in a third area, wherein the first thin film transistor and the second thin film transistor are disposed in the same direction), the arrangement structures of the sub-pixels adjacent to each other in the same column are the same, and the arrangement structures of the sub-pixels adjacent to each other in the same row are in an inverted configuration, such that the gate of the second thin film transistor of the sub-pixel located in the odd column in the same row is connected to the gate of the first thin film transistor of the sub-pixel located in the even column and the gate of the first thin film transistor of the sub-pixel located in the odd column in the same row is connected to the gate of the second thin film transistor of the sub-pixel located in the even column (the layout of the gate lines can shorten the length of the gate lines, and avoid the overlapping condition between the gate lines) to realize dot inversion in the low-frequency and low-power consumption alternating current common voltage driving mode, and improve the problem of visual reflection scanning lines caused by low-frequency driving (i.e. directly eliminating the visual reflection scanning lines on the circuit layout design). In addition, the layout design of the sub-pixels and the layout design of the traces are the same as the conventional array mask process, so the number of process steps and the number of masks are not increased.

Although the above-described elements are included in the drawings of the present application, it is not excluded that more additional elements may be used to achieve better technical results without departing from the spirit of the present invention.

While the utility model has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the utility model. Rather, this utility model encompasses modifications and similar arrangements that would be apparent to those skilled in the art. The scope of the claims is, therefore, to be construed in the broadest manner to include all such obvious modifications and similar arrangements.

Claims (9)

1. A liquid crystal display device with dot inversion, comprising:

m data lines, wherein M is a positive integer;

a plurality of subpixels arranged in M columns and N rows, each of the plurality of subpixels comprising: the first thin film transistor is arranged in the first area, the second thin film transistor is arranged in the second area, and the capacitor is arranged in the third area; in each of the plurality of sub-pixels, the second region is disposed between the first region and the third region, the first thin film transistor and the second thin film transistor are disposed in the same direction, the source of the first thin film transistor is electrically connected to the source of the second thin film transistor, the drain of the first thin film transistor is electrically connected to one end of the capacitor, and the other end of the capacitor is electrically connected to an ac common voltage; the arrangement structure of any sub-pixel in the same row after vertically turning along the horizontal direction is the same as that of the adjacent sub-pixels; a plurality of source electrodes of the first thin film transistors and a plurality of source electrodes of the second thin film transistors of the plurality of sub-pixels positioned in the same column are connected with the same data line, and N is a positive integer;

n first gate lines for respectively connecting the gates of the second TFTs of the sub-pixels in the odd-numbered columns of the same row and the gates of the first TFTs of the sub-pixels in the even-numbered columns; and

and the N second gate lines are used for respectively connecting a plurality of gates of the first thin film transistors of the plurality of sub-pixels positioned in odd columns of the same row and a plurality of gates of the second thin film transistors of the plurality of sub-pixels positioned in even columns.

2. The device of claim 1, wherein the N first gate lines and the N second gate lines are arranged in a detour manner.

3. The device as claimed in claim 1, wherein the N first gate lines and the N second gate lines are linearly arranged.

4. The liquid crystal display device with dot inversion according to claim 1, wherein two adjacent sub-pixels in the same row constitute a unit, and the liquid crystal display device with dot inversion comprises a plurality of the units arranged in an array.

5. The liquid crystal display device with dot inversion according to claim 1, further comprising:

the gate driving circuit is electrically connected with the N first gate lines and the N second gate lines and used for respectively providing 2N gate driving signals to the N first gate lines and the N second gate lines;

the data driving circuit is electrically connected with the M data lines and used for respectively providing M data driving signals to the M data lines; and

and the common voltage generating circuit is electrically connected with the capacitors and is used for providing the alternating current common voltage.

6. The liquid crystal display device with dot inversion of claim 1, wherein the first thin film transistors and the second thin film transistors are oxide thin film transistors or polysilicon thin film transistors, respectively.

7. The liquid crystal display device with dot inversion of claim 1, wherein the capacitors are storage capacitors.

8. The device of claim 1, wherein the plurality of sub-pixels comprise micro-reflective sub-pixels, transflective sub-pixels, or a combination thereof.

9. The liquid crystal display device according to claim 1, wherein in each of the plurality of sub-pixels, a polarity of the first region is the same as a polarity of the third region, and the polarity of the first region is opposite to the polarity of the third region and the polarity of the second region.

Images