CN216390954U - Delayed starting-up circuit - Google Patents
Delayed starting-up circuit Download PDFInfo
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- CN216390954U CN216390954U CN202122828315.3U CN202122828315U CN216390954U CN 216390954 U CN216390954 U CN 216390954U CN 202122828315 U CN202122828315 U CN 202122828315U CN 216390954 U CN216390954 U CN 216390954U
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Abstract
The application relates to thing networking communication module technical field, in particular to postpone start circuit includes: the delay capacitor is charged by the power supply after receiving the starting signal; the switch circuit is connected with the delay capacitor and is switched off or switched on according to the charging state of the delay capacitor; and one end of the starting circuit is connected with the switch circuit, the other end of the starting circuit is connected with the load circuit, and the starting circuit sends a starting signal to the load circuit after the delay capacitor finishes charging so that the switch circuit is closed, and the power supply supplies power to the load circuit. Therefore, the problems of high cost and poor stability caused by startup delay due to the addition of the delay chip in the related technology are solved, the effect of delaying the switch can be effectively achieved, various application scenes are flexibly applied, and the delay switch is high in stability, low in cost and simple and easy to realize.
Description
Technical Field
The application relates to the technical field of communication modules of the Internet of things, in particular to a startup delay circuit.
Background
With the rapid development of the internet, the internet is applied more and more, the demand of the corresponding internet of things communication module is increased day by day, and the functions are developed in various ways. At present, the modules are smaller and smaller, the internal integration function is multiple, the design is complex, the requirement on a power circuit is high, most communication modules require stable power before starting, and the circuit is required to delay starting.
In the related art, the startup delay is realized by adding a delay chip, but the chip cost is high, and the chip is not flexible and simple enough, so that a solution is needed urgently.
SUMMERY OF THE UTILITY MODEL
The application provides a delay start circuit to realize that the start delay leads to the problem that the cost is higher, poor stability through adding delay chip among the solution correlation technique, can effectually reach delay switch's effect, and the multiple application scene of nimble application, not only stability is high, and with low costs, simple easily realization.
The application provides a delay start-up circuit, includes:
the power supply and the delay capacitor are charged by the power supply after the delay capacitor receives a starting signal;
the switch circuit is connected with the delay capacitor and is switched off or switched on according to the charging state of the delay capacitor; and
and the starting circuit is connected with the switch circuit at one end and connected with the load circuit at the other end, and the starting circuit sends the starting signal to the load circuit after the delay capacitor finishes charging so that the switch circuit is closed, and the power supply supplies power to the load circuit.
Optionally, the method further comprises:
and the first end of the discharge circuit is connected with the first end of the load circuit, the second end of the discharge circuit is connected with the second end of the load circuit, and the third end of the discharge circuit is respectively connected with the power supply and the ground, so that after a shutdown signal is received, if the voltage at the two ends of a discharge capacitor in the load circuit is greater than the breakover voltage of the discharge circuit, the discharge capacitor is discharged.
Optionally, the discharge circuit comprises:
the base electrode of the first triode is connected with the power supply, the emitting electrode of the first triode is connected with one end of the discharge capacitor, and the collecting electrode of the first triode is connected with the other end of the discharge capacitor;
one end of the first resistor is connected with the base electrode of the first triode, and the other end of the first resistor is grounded.
Optionally, the discharge circuit further includes:
and one end of the second resistor is connected with the collector of the first triode, and the other end of the second resistor is connected with the other end of the discharge capacitor.
Optionally, the switching circuit comprises:
one end of the third resistor is connected with the delay capacitor;
one end of the fourth resistor is connected with the other end of the third resistor;
a base electrode of the second triode is connected with one end of the fourth resistor, a collector electrode of the second triode is connected with the power supply, and an emitting electrode of the second triode is connected with the other end of the fourth resistor;
a first MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) Transistor, a gate of the first MOS Transistor being connected to a collector of the second triode, a source of the first MOS Transistor being connected to an emitter of the second triode, and a drain of the first MOS Transistor being connected to the power-on circuit;
and one end of the fifth resistor is connected with the collector of the second triode, and the other end of the fifth resistor is connected with the emitter of the second triode.
Optionally, the method further comprises:
and one end of the sixth resistor is connected with the power supply, and the other end of the sixth resistor is connected with the collector of the second triode.
Optionally, the boot circuit includes:
a grid electrode of the second MOS tube is connected with a drain electrode of the first MOS tube, a source electrode of the second MOS tube is connected with the power supply, and a drain electrode of the second MOS tube is connected with the load circuit;
one end of the seventh resistor is connected with the source electrode of the second MOS tube, and the other end of the seventh resistor is connected with the grid electrode of the second MOS tube.
Optionally, the first MOS transistor is an NMOS transistor; the second MOS tube is a PMOS tube; the first triode is a PNP triode; the second triode is an NPN triode.
Therefore, after the delay capacitor receives the starting signal, the power supply charges the delay capacitor, the delay capacitor finishes charging, the starting circuit sends the starting signal to the load circuit after the switch circuit is closed, and the power supply supplies power to the load. Therefore, the problems of high cost and poor stability caused by startup delay due to the addition of the delay chip in the related technology are solved, the effect of delaying the switch can be effectively achieved, various application scenes are flexibly applied, and the delay switch is high in stability, low in cost and simple and easy to realize.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a circuit diagram of a delayed turn-on circuit according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
The delayed turn-on circuit of the embodiment of the present application is described below with reference to the drawings. In order to solve the problems of high cost and poor stability caused by the fact that the starting delay is achieved by adding the delay chip, the delay capacitor charges the delay capacitor after receiving the starting signal, the delay capacitor completes charging, the starting circuit sends the starting signal to the load circuit after the switch circuit is closed, and the power supply supplies power to the load circuit. Therefore, the problems of high cost and poor stability caused by startup delay due to the addition of the delay chip in the related technology are solved, the effect of delaying the switch can be effectively achieved, various application scenes are flexibly applied, and the delay switch is high in stability, low in cost and simple and easy to realize.
Specifically, fig. 1 is a circuit diagram of a delayed turn-on circuit according to an embodiment of the present disclosure.
As shown in fig. 1, the delayed turn-on circuit 10 includes: a power supply VCC _ IN, a delay capacitor C1, a switch circuit 100 and a power-on circuit 200.
After receiving the power-on signal, the delay capacitor C1 is charged by the power supply to the delay capacitor C1; the switch circuit 100 is connected with the delay capacitor C1, and the switch circuit 100 is opened or closed according to the charging state of the delay capacitor C1; one end of the startup circuit 200 is connected to the switch circuit 100, the other end of the startup circuit 200 is connected to the load circuit, and after the delay capacitor C1 completes charging, the startup circuit 200 sends a startup signal to the load circuit, and the load circuit is powered by the power supply VCC _ IN.
Optionally, in some embodiments, the switching circuit 100 includes: the circuit comprises a third resistor R3, a fourth resistor R4, a second triode Q2, a first MOS transistor Q3 and a fifth resistor R5. One end of the third resistor R3 is connected with the delay capacitor C1; one end of the fourth resistor R4 is connected with the other end of the third resistor R3; the base electrode of the second triode Q2 is connected with one end of a fourth resistor R4, the collector electrode of the second triode Q2 is connected with a power supply VCC _ IN, and the emitter electrode of the second triode Q2 is connected with the other end of the fourth resistor R4; the grid electrode of the first MOS tube Q3 is connected with the collector electrode of the second triode Q2, the source electrode of the first MOS tube Q3 is connected with the emitter electrode of the second triode Q2, and the drain electrode of the first MOS tube Q3 is connected with the startup circuit 200; one end of the fifth resistor R5 is connected to the collector of the second transistor Q2, and the other end of the fifth resistor R5 is connected to the emitter of the second transistor Q2.
Optionally, in some embodiments, the boot circuit 200 includes: a second MOS transistor Q4 and a seventh resistor R7. The grid electrode of the second MOS tube Q4 is connected with the drain electrode of the first MOS tube Q3, the source electrode of the second MOS tube Q4 is connected with a power supply VCC _ IN, and the drain electrode of the second MOS tube Q4 is connected with a load circuit; one end of the seventh resistor R7 is connected to the source of the second MOS transistor Q4, and the other end of the seventh resistor R7 is connected to the gate of the second MOS transistor Q4.
Optionally, in some embodiments, the first MOS transistor Q3 is an NMOS transistor; the second MOS transistor Q4 is a PMOS transistor; the second transistor Q2 is an NPN transistor.
The power-on signal is a signal when the power supply VCC _ IN is turned on.
Specifically, as shown IN fig. 1, when the power supply VCC _ IN is closed, the delay capacitor C1 starts to charge, and the current path of the delay capacitor C1 is as follows: one path is from the delay capacitor C1 to the third resistor R3 and then to the base of the second triode Q2, and the other path is from the delay capacitor C1 to the third resistor R3, the fourth resistor R4 and GND. The second transistor Q2 is turned on IN saturation, the voltage GS =0V between the gate and the source of the first MOS transistor Q3, the first MOS transistor Q3 is turned off, at this time, the voltage GS =0V between the gate and the source of the second MOS transistor Q4, the second MOS transistor Q4 is turned off, the power source VCC _ IN is isolated from the load circuit (Module power supply), the Module cannot be started, when the charging of the delay capacitor C1 is finished, no current flows through the delay capacitor C1, the second transistor Q2 is turned off, the voltage GS = VCC _ IN between the gate and the source of the first MOS transistor Q3, the first MOS transistor Q3 is turned on, at this time, the voltage GS = -VCC _ IN between the gate and the source of the second MOS transistor Q4 is turned on, the second MOS transistor Q4 is turned on, the power source VCC _ IN is connected to the load circuit (Module power supply), and the Module is turned on, so that the power-on delay is realized.
It should be noted that in the embodiment of the present application, the charging time of the delay capacitor C1 may be adjusted by adjusting the delay capacitor C1, or changing the resistance of the third resistor R3, or the resistance of the fourth resistor R4, or simultaneously changing the resistances of the delay capacitor C1, the third resistor R3, and the fourth resistor R4, and specific values may be set according to actual situations, which is not specifically limited herein. Preferably, the third resistor R3 is 10K and the fourth resistor R4 is 47K.
Therefore, the effect of delaying the switch can be effectively achieved, and various application scenes can be flexibly applied.
Optionally, in some embodiments, the method further comprises: a sixth resistor R6. One end of the sixth resistor R6 is connected to the power source VCC _ IN, and the other end of the sixth resistor R6 is connected to the collector of the second transistor Q2.
It should be appreciated that since the embodiment of the present application simultaneously supplies power to the base and the collector of the second transistor Q2 through the power source VCC _ IN, and the voltage levels of the base and the collector of the second transistor Q2 are different, the embodiment of the present application may be implemented by providing the sixth resistor R6 to limit the current and divide the voltage. Preferably, the sixth resistor R6 is 470K.
Optionally, in some embodiments, the delayed boot-up circuit 10 according to the embodiment of the present application further includes: a discharge circuit 300. The first end of the discharge circuit 300 is connected to the first end of the load circuit, the second end of the discharge circuit 300 is connected to the second end of the load circuit, and the third end of the discharge circuit 300 is connected to the power source VCC _ IN and the ground, respectively, and is configured to discharge the discharge capacitor C2 if the voltage across the discharge capacitor C2 IN the load circuit is greater than the on-state voltage of the discharge circuit 300 after receiving the shutdown signal.
Optionally, in some embodiments, the discharge circuit 300 includes: a first transistor Q1 and a first resistor R1. The base electrode of the first triode Q1 is connected with a power supply VCC _ IN, the emitting electrode of the first triode Q1 is connected with one end of a discharge capacitor C2, and the collecting electrode of the first triode Q1 is connected with the other end of the discharge capacitor C2; one end of the first resistor R1 is connected to the base of the first transistor Q1, and the other end of the first resistor R1 is grounded.
Optionally, in some embodiments, the first transistor Q1 is a PNP transistor.
Optionally, in some embodiments, the discharge circuit 300 further includes: and a second resistor R2. One end of the second resistor R2 is connected to the collector of the first transistor Q1, and the other end of the second resistor R2 is connected to the other end of the discharging capacitor C2.
It should be understood that, because the capacitance at the front end of the module is large in capacity, the module may not be reset and started normally due to frequent and rapid pressing of the clamp at a factory production station and re-electrifying when the capacitance is not completely powered down, and thus the module circuit works abnormally and the module crashes. Therefore, the embodiment of the application can be provided with a discharge circuit to release the circuit of the capacitance storage in the load circuit.
Specifically, when the power source VCC _ IN is turned off, if the voltage Veb between the emitter and the base of the first transistor Q1 is greater than 0.7V, the first transistor Q1 is turned on IN a saturated state, and the discharging capacitor C2 of the load circuit is rapidly discharged to the ground through the first transistor Q1 and the second resistor R2, thereby avoiding the abnormal operation of the Module circuit when the load circuit is powered on again because the stored electricity of the capacitor is not completely discharged.
It should be noted that, in the embodiment of the present application, the discharge time of the discharge capacitor C2 may be adjusted by adjusting the resistance of the second resistor R2, but the maximum power of the first transistor Q1 may not be exceeded.
Therefore, the problem that when equipment is restarted, the circuit works abnormally due to the fact that residual electricity of a large load capacitor is not discharged completely can be effectively avoided.
According to the startup delay circuit provided by the embodiment of the application, the delay capacitor is charged by the power supply after receiving the startup signal, and the delay capacitor is charged, so that after the switch circuit is closed, the startup circuit sends the startup signal to the load circuit, and the power supply supplies power to the load. Therefore, the problems of high cost and poor stability caused by startup delay due to the addition of the delay chip in the related technology are solved, the effect of delaying the switch can be effectively achieved, various application scenes are flexibly applied, and the delay switch is high in stability, low in cost and simple and easy to realize.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "N" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (8)
1. A delayed power-on circuit, comprising:
the power supply and the delay capacitor are charged by the power supply after the delay capacitor receives a starting signal;
the switch circuit is connected with the delay capacitor and is switched off or switched on according to the charging state of the delay capacitor; and
and the starting circuit is connected with the switch circuit at one end and connected with the load circuit at the other end, and the starting circuit sends the starting signal to the load circuit after the delay capacitor finishes charging so that the switch circuit is closed, and the power supply supplies power to the load circuit.
2. The delayed power-on circuit of claim 1, further comprising:
and the first end of the discharge circuit is connected with the first end of the load circuit, the second end of the discharge circuit is connected with the second end of the load circuit, and the third end of the discharge circuit is respectively connected with the power supply and the ground, so that after a shutdown signal is received, if the voltage at the two ends of a discharge capacitor in the load circuit is greater than the breakover voltage of the discharge circuit, the discharge capacitor is discharged.
3. The delayed turn-on circuit of claim 2, wherein the discharge circuit comprises:
the base electrode of the first triode is connected with the power supply, the emitting electrode of the first triode is connected with one end of the discharge capacitor, and the collecting electrode of the first triode is connected with the other end of the discharge capacitor;
one end of the first resistor is connected with the base electrode of the first triode, and the other end of the first resistor is grounded.
4. The delayed turn-on circuit of claim 3, wherein the discharge circuit further comprises:
and one end of the second resistor is connected with the collector of the first triode, and the other end of the second resistor is connected with the other end of the discharge capacitor.
5. The delayed turn-on circuit of claim 4, wherein the switching circuit comprises:
one end of the third resistor is connected with the delay capacitor;
one end of the fourth resistor is connected with the other end of the third resistor;
a base electrode of the second triode is connected with one end of the fourth resistor, a collector electrode of the second triode is connected with the power supply, and an emitting electrode of the second triode is connected with the other end of the fourth resistor;
the grid electrode of the first MOS tube is connected with the collector electrode of the second triode, the source electrode of the first MOS tube is connected with the emitter electrode of the second triode, and the drain electrode of the first MOS tube is connected with the starting-up circuit;
and one end of the fifth resistor is connected with the collector of the second triode, and the other end of the fifth resistor is connected with the emitter of the second triode.
6. The delayed power-on circuit of claim 5, further comprising:
and one end of the sixth resistor is connected with the power supply, and the other end of the sixth resistor is connected with the collector of the second triode.
7. The delayed power-on circuit of claim 6, wherein the power-on circuit comprises:
a grid electrode of the second MOS tube is connected with a drain electrode of the first MOS tube, a source electrode of the second MOS tube is connected with the power supply, and a drain electrode of the second MOS tube is connected with the load circuit;
one end of the seventh resistor is connected with the source electrode of the second MOS tube, and the other end of the seventh resistor is connected with the grid electrode of the second MOS tube.
8. The delayed power-on circuit of claim 7,
the first MOS tube is an NMOS tube;
the second MOS tube is a PMOS tube;
the first triode is a PNP triode;
the second triode is an NPN triode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122828315.3U CN216390954U (en) | 2021-11-17 | 2021-11-17 | Delayed starting-up circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122828315.3U CN216390954U (en) | 2021-11-17 | 2021-11-17 | Delayed starting-up circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216390954U true CN216390954U (en) | 2022-04-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122828315.3U Active CN216390954U (en) | 2021-11-17 | 2021-11-17 | Delayed starting-up circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216390954U (en) |
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2021
- 2021-11-17 CN CN202122828315.3U patent/CN216390954U/en active Active
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