CN216319509U - Closed-loop deep brain stimulation artifact suppression circuit - Google Patents
Closed-loop deep brain stimulation artifact suppression circuit Download PDFInfo
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- CN216319509U CN216319509U CN202122220752.7U CN202122220752U CN216319509U CN 216319509 U CN216319509 U CN 216319509U CN 202122220752 U CN202122220752 U CN 202122220752U CN 216319509 U CN216319509 U CN 216319509U
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Abstract
The utility model discloses a closed loop deep brain stimulation artifact suppression circuit, which comprises: the input end of the front-end amplifying circuit is configured to be differential input, and the output end of the front-end amplifying circuit is configured to be single-ended output; the high-pass filter circuit is connected with the front-end amplifying circuit, the input end of the high-pass filter circuit is configured to be single-ended input, and the output end of the high-pass filter circuit is configured to be single-ended output; the low-pass filter circuit is connected with the high-pass filter circuit, the input end of the low-pass filter circuit is configured as single-ended input, and the output end of the low-pass filter circuit is configured as single-ended output; and the rear-end amplifying circuit is connected with the low-pass filter circuit, the input end of the rear-end amplifying circuit is configured to be single-ended input, and the output end of the rear-end amplifying circuit is configured to be differential output. The closed-loop deep brain stimulation artifact suppression circuit disclosed by the utility model has the advantages that the cost is reduced, the power consumption is reduced and the space is saved while the weak signals are accurately acquired.
Description
Technical Field
The utility model relates to the technical field of brain-computer interfaces and medical electronic circuits, in particular to a closed-loop deep brain stimulation artifact suppression circuit.
Background
The subthalamic nucleus (STN) of Parkinson's Disease (PD) patients can continuously detect Local Field Potential (LFP) oscillations in the beta band (13-30Hz), and LFP signal intensity is correlated with the severity of the disease and the therapeutic effect.
Observing the LFP signal during stimulation may reveal new neural activity that is not present in the neural tissue in the absence of stimulation. The large difference between the amplitude of the stimulation pulses and the amplitude of the associated neural signals leads to the appearance of stimulation artifacts, which prevent accurate recording of the neural signals and processing of the valid biomarker signals.
At present, in a hardware circuit for suppressing stimulus artifacts, in order to filter remaining interference noise such as common mode noise and differential mode noise during acquisition, a neural signal is generally input in a differential manner, an analog-to-digital converter for subsequently realizing digitization also generally inputs in a differential manner, and a common filter circuit adopts a transmission manner of single-ended input and single-ended output, so if a filter circuit with interference removal is used in front of the analog-to-digital converter, 2 identical filter circuits are required to be connected to two input ends of the analog-to-digital converter.
Due to the design, on one hand, two circuits in practical application cannot be completely consistent, so that the difference of the acquisition inhibition result is caused, and the judgment result is influenced; on the other hand, a larger number of chips is required, which leads to problems such as increased cost, increased power consumption, and large occupied space.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a closed-loop deep brain stimulation artifact suppression circuit which can accurately acquire weak signals and simultaneously reduce the cost, the power consumption and the space.
In order to solve the technical problems, the technical scheme of the utility model is as follows: a closed-loop deep brain stimulation artifact suppression circuit, comprising:
the input end of the front-end amplifying circuit is configured to be differential input, and the output end of the front-end amplifying circuit is configured to be single-ended output;
the high-pass filter circuit is connected with the front-end amplifying circuit, the input end of the high-pass filter circuit is configured to be single-ended input, and the output end of the high-pass filter circuit is configured to be single-ended output;
the low-pass filter circuit is connected with the high-pass filter circuit, the input end of the low-pass filter circuit is configured as single-ended input, and the output end of the low-pass filter circuit is configured as single-ended output;
and the rear-end amplifying circuit is connected with the low-pass filter circuit, the input end of the rear-end amplifying circuit is configured to be single-ended input, and the output end of the rear-end amplifying circuit is configured to be differential output.
Preferably, the front-end amplifying circuit comprises an instrumentation amplifier INA1, an adjustable gain resistor Rg1, a +/-5V direct-current voltage-stabilizing voltage source, and the adjustable gain resistor Rg sets the gain of the front-end amplifying circuit to be 40dB or 60 dB.
Preferably, the high pass filter circuit is configured as a three-stage 6-stage type circuit, each stage of the 2-stage type circuit includes a capacitor Ch1, a resistor Rh1, a capacitor Ch2, a resistor Rh2, an operational amplifier Oph1 and a ± 5V dc power supply, the output terminal of the front-end amplification circuit is connected to the P terminal of the operational amplifier Oph1 through the capacitor Ch1 and the capacitor Ch2 in sequence, the resistor Rh1 is connected between the capacitor Ch1 and the capacitor Ch2 at one end and to the N terminal of the operational amplifier Oph1 at the other end, the resistor Rh2 is connected between the capacitor Ch2 and the P terminal of the operational amplifier Oph1 at one end, and the other end is grounded.
Preferably, the cutoff frequency of the high-pass filter circuit is set to 0.05 to 1 Hz.
Preferably, the low-pass filter circuit is configured as a five-stage 10-stage type circuit, each stage 2 includes a capacitor Cl1, a resistor Rl1, a capacitor Cl2, a resistor Rl2, an operational amplifier Opl1 and a ± 5V dc power supply, an output terminal of the high-pass filter circuit is connected to a P terminal of the operational amplifier Opl1 through a resistor Rl1 and a resistor Rl2 in sequence, one end of the capacitor Cl1 is connected between the resistor Rl1 and the resistor Rl2, the other end of the capacitor Cl2 is connected to an N terminal of the operational amplifier Opl1, one end of the capacitor Cl2 is connected between the resistor Rl2 and the P terminal of the operational amplifier Opl1, and the other end of the capacitor Cl2 is grounded.
Preferably, the cutoff frequency of the low-pass filter circuit is configured to be 40-48 Hz.
Preferably, the back-end amplification circuit comprises an adjustable gain resistor Rf1, an adjustable gain resistor Rf2, a fully differential amplifier INA2 and a ± 2.5V dc regulated voltage source, the adjustable gain resistor Rf1 is connected to a P input end and a P output end of the fully differential amplifier INA2, the adjustable gain resistor Rf2 is connected to an N input end and an N output end of the fully differential amplifier INA2, and the adjustable gain resistor Rg sets the gain of the front-end amplification circuit to 0dB to 20 dB.
Preferably, the back-end amplifying circuit further comprises a resistor Rb1, a resistor Rb2 and a matching resistor Rt, the output terminal of the low-pass filter circuit is connected to the P input terminal of the fully differential amplifier INA2 through a resistor Rb1, the N input terminal of the fully differential amplifier INA2 is connected to the ground through a resistor Rb2, and the matching resistor Rt is connected to the input terminal of the back-end amplifying circuit.
Preferably, the back-end amplifying circuit further includes an output reference capacitor Cc and an output differential capacitor Cd, the output reference capacitor Cc is connected to the Voc pin of the fully differential amplifier INA2, and the output differential capacitor Cd is connected between the P output terminal and the N output terminal of the fully differential amplifier INA 2.
Compared with the prior art, the utility model has the following advantages:
the closed-loop deep brain stimulation artifact suppression circuit adopts a fully differential low-noise structure with differential input and differential output, during acquisition, only 1 circuit needs to be arranged in one channel, the single-ended input of a filter circuit and the differential input of an analog-to-digital conversion circuit can be simultaneously met, and the problem of inconsistent two paths of filtering in differential input is not considered;
furthermore, when more channels are arranged, only the circuits with the same number need to be added, and compared with the prior art, half of the number of chips can be saved, so that the purposes of reducing power consumption, reducing cost and saving space are achieved.
Drawings
The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, the proportional sizes, and the like of the respective members in the drawings are merely schematic for facilitating the understanding of the present invention, and do not specifically limit the shapes, the proportional sizes, and the like of the respective members of the present invention. Those skilled in the art, having the benefit of the teachings of this invention, may choose from the various possible shapes and proportional sizes to implement the utility model as a matter of case. In the drawings:
FIG. 1 is a block diagram of a closed-loop deep brain stimulation artifact suppression circuit of the present invention;
FIG. 2 is a schematic diagram of a front-end amplifier circuit according to the present invention;
FIG. 3 is a schematic diagram of a high-pass filter circuit according to the present invention;
FIG. 4 is a schematic diagram of a low-pass filter circuit according to the present invention;
fig. 5 is a schematic diagram of a back-end amplifier circuit according to the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, shall fall within the scope of protection of the present invention.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a single embodiment.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the closed-loop deep brain stimulation artifact suppression circuit according to a preferred embodiment of the present invention includes a front-end amplification circuit 1, a high-pass filter circuit 2, a low-pass filter circuit 3, and a back-end amplification circuit 4, which are connected in sequence, wherein an input end of the front-end amplification circuit 1 is configured as a differential input, and an output end thereof is configured as a single-ended output; the input end of the high-pass filter circuit 2 is configured as single-ended input, and the output end is configured as single-ended output; the input end of the low-pass filter circuit 3 is configured as single-ended input, and the output end is configured as single-ended output; the input terminal of the back-end amplification circuit 4 is configured as a single-ended input, and the output terminal is configured as a differential output. The whole closed-loop deep brain stimulation artifact suppression circuit is configured to be a fully differential low-noise structure with differential input and differential output.
Specifically, as shown in fig. 2, the front-end amplification circuit 1 includes an instrumentation amplifier INA1, an adjustable gain resistor Rg1, a ± 5V dc voltage-stabilizing voltage source, and a peripheral capacitor. The instrument amplifier INA1 is powered by +/-5V, and the instrument amplifier INA1 has the advantages of low offset voltage and low output noise, and can meet the requirement of minimum noise of neural signal recording.
The instrument amplifier INA1 sets amplification times through the adjustable gain resistor Rg1, the gain of the whole front-end amplification circuit 1 is configured to be 40 dB-60 dB, and preferably, when the resistance value of the adjustable gain resistor Rg1 is set to be 60.4 omega, the gain of the front-end amplification circuit 1 is 40 dB; when the resistance of the adjustable gain resistor Rg1 is set to 6.04 Ω, the gain of the front-end amplification circuit 1 is 60 dB.
The cut-off frequency of the high-pass filter circuit 2 is configured to be 0.05-1 Hz, so that low-frequency signals which do not need to be collected can be well filtered. As shown in fig. 3, the high-pass filter circuit 2 is preferably designed with-3 dB passband ripple, a cutoff frequency of 0.5Hz, a stopband frequency of 0.1Hz, attenuation of-100 dB, and a three-stage 6-stage Butterworth-type circuit is obtained according to a 2-stage salen-key structure, but in order to reduce noise, the high-pass filter circuit 2 does not introduce resistance amplification, and the configured amplification is 1. The 2-stage high-pass filter circuit of each stage has the same structure (fig. 3 shows a specific structure of one stage), the first-stage 2-stage high-pass filter circuit includes a capacitor Ch1, a resistor Rh1, a capacitor Ch2, a resistor Rh2, an operational amplifier Oph1 and a ± 5V dc power supply, the operational amplifier Oph1 is powered by ± 5V, the output terminal of the instrumentation amplifier INA1 is connected to the P terminal of the operational amplifier Oph1 through the capacitor Ch1 and the capacitor Ch2 in sequence, one end of the resistor Rh1 is connected between the capacitor Ch1 and the capacitor Ch2, the other end is connected to the N terminal of the operational amplifier Oph1, one end of the resistor Rh2 is connected between the P terminals of the capacitor Ch2 and the operational amplifier Oph1, and the other end is grounded. Furthermore, the second-stage 2-order high-pass filter circuit comprises a capacitor Ch3, a resistor Rh3, a capacitor Ch4, a resistor Rh4, an operational amplifier Oph2 and a +/-5V direct-current power supply; the third-stage 2-order high-pass filter circuit comprises a capacitor Ch5, a resistor Rh5, a capacitor Ch6, a resistor Rh6, an operational amplifier Oph3 and a +/-5V direct-current power supply, wherein the first stage and the second stage are preferably completed by using a low-noise low-offset-voltage dual operational amplifier ADA4522-2, and the third stage is completed by using a low-noise low-offset-voltage single operational amplifier ADA 4522-1. The high-pass filter circuit 2 is thus set up, and its filter output noise is less than 1.1 uVpp.
The cut-off frequency of the low-pass filter circuit 3 is configured to be 40-48 Hz, so that local field potential signals in a beta frequency band can be well acquired, and particularly, the cut-off frequency is configured to be optimal to be 45 Hz. The low-pass filter circuit 3 preferably adopts an active low-pass filter circuit, can better reduce input and output noise, thereby reducing total noise, and has simple structure, steep reduction at cut-off frequency and good filtering effect. Specifically, as shown in fig. 4, the low-pass filter circuit 3 is preferably designed with-3 dB passband ripple, a cutoff frequency of 45Hz, and a stopband frequency of 125Hz, and a five-stage 10-stage Butterworth-type circuit is obtained according to a 2-stage salen-key structure, and similarly, in order to reduce noise, the low-pass filter circuit does not introduce resistance amplification, and the amplification is configured to be 1. The 2 nd order low-pass filter circuit of each stage has the same structure (fig. 4 shows a specific structure of one of the stages), the first stage 2 nd order low-pass filter circuit includes a capacitor Cl1, a resistor Rl1, a capacitor Cl2, a resistor Rl2, an operational amplifier Opl1 and a ± 5V dc power supply, the operational amplifier Opl1 is powered by ± 5V, an output end of the high-pass filter circuit is connected to a P end of the operational amplifier Opl1 through a resistor Rl1 and a resistor Rl2 in sequence, one end of the capacitor Cl1 is connected between the resistor Rl1 and the resistor Rl2, the other end of the capacitor Cl1 is connected to an N end of the operational amplifier Opl1, one end of the capacitor Cl2 is connected between the P end of the resistor Rl2 and the operational amplifier Opl1, and the other end of the capacitor Cl2 is grounded. Furthermore, the second-stage 2-order low-pass filter circuit comprises a capacitor Cl3, a resistor Rl3, a capacitor Cl4, a resistor Rl4, an operational amplifier Opl2 and a +/-5V direct-current power supply; the third-stage 2-order low-pass filter circuit comprises a capacitor Cl5, a resistor Rl5, a capacitor Cl6, a resistor Rl6, an operational amplifier Opl3 and a +/-5V direct-current power supply; the fourth-stage 2-order low-pass filter circuit comprises a capacitor Cl7, a resistor Rl7, a capacitor Cl8, a resistor Rl8, an operational amplifier Opl4 and a +/-5V direct-current power supply; the fifth stage 2 nd order low pass filter circuit comprises a capacitor Cl9, a resistor Rl9, a capacitor Cl10, a resistor Rl10, an operational amplifier Opl5 and a +/-2.5V power supply direct current power supply. The first stage, the second stage, the third stage and the fourth stage are preferably completed by adopting a low-noise low-offset-voltage dual operational amplifier ADA4522-2, and the fifth stage is completed by adopting a low-noise low-offset-voltage single operational amplifier ADA 4522-1. The low-pass filter circuit 3 is thus set, and the filter output noise thereof is less than 1.6 uVpp.
As shown in fig. 5, the back-end amplifier circuit 4 includes a resistor Rb1, an adjustable gain resistor Rf1, a resistor Rb2, an adjustable gain resistor Rf2, a matching resistor Rt, a fully differential amplifier INA2, an output reference capacitor Cc, an output differential capacitor Cd, ± 2.5V dc regulated voltage source, and a decoupling capacitor. The fully differential amplifier INA2 adopts the fully differential amplifier HP210 to realize a low input offset voltage of 10uV and an output noise of 9nV/√ Hzf ═ 1k, so as to meet the minimum noise requirement of neural signal recording; furthermore, an adjustable gain resistor Rf1 is connected to the P input end and the P output end of the fully differential amplifier INA2, an adjustable gain resistor Rf2 is connected to the N input end and the N output end of the fully differential amplifier INA2, amplification factors are set through the adjustable gain resistor Rf1 and the adjustable gain resistor Rf2, the gain of the whole rear-end amplification circuit 4 is configured to be 0 dB-20 dB, and the rear-end amplification circuit 4 and the front-end amplification circuit 1 achieve 40 dB-80 dB total gain through gain matching. When the resistances of the adjustable gain resistor Rf1, the adjustable gain resistor Rf2, the resistor Rb1 and the resistor Rb2 are all set to 215 Ω, the gain of the rear-end amplification circuit 4 is 0 dB; when the resistance values of the adjustable gain resistor Rf1 and the adjustable gain resistor Rf2 are set to 1000 Ω, and the resistance values of the resistor Rb1 and the resistor Rb2 are set to 100 Ω, the gain of the back-end amplification circuit 4 is 20 dB.
The output end of the low-pass filter circuit 3 is connected to the P input end of the fully differential amplifier INA2 through a resistor Rb1, and the N input end of the fully differential amplifier INA2 is grounded through a resistor Rb2, so that single-ended input of the fully differential amplifier INA2 is realized. A Voc pin of the fully differential amplifier INA2 can be provided with a default output end intermediate power supply reference, and an output reference capacitor Cc is added to the Voc pin to reduce other high output noise of internal high impedance bias; an output differential capacitor Cd is added between a P output end and an N output end of the fully differential amplifier INA2 to filter high-frequency components and enter a subsequent analog-to-digital conversion circuit; because the output end of the rear-end amplifying circuit 4 is configured as differential output, a matching resistor Rt needs to be added at the input end of the rear-end amplifying circuit 4, impedance matching related to actual gain is done by selecting a proper matching resistor Rt, and if the signal has a topping condition or excessive attenuation, mismatching is indicated, so that the gain setting is incorrect.
Unlike the previous circuits, the voltage of the fully differential amplifier INA2 needs to be matched to the voltage of the analog-to-digital conversion circuit that is subsequently digitized, and in particular to the maximum voltage input range of the analog-to-digital conversion circuit, in order to prevent the analog-to-digital conversion circuit from saturating. Specifically, when the fully differential amplifier INA2 is preferably powered by ± 2.5V, the maximum output voltage of the back-end amplification circuit 4 is determined to be-5 Vpp, so that after a signal passes through the back-end amplification circuit 4, the amplification factor is generally set to be 0 dB-20 dB, and the maximum amplification factor is 20dB, when the signal is set to be higher than 0dB, the signal peak-to-peak amplitude needs to be considered in cooperation with the gain of the analog-to-digital conversion circuit, and the signal peak-to-peak amplitude cannot exceed the maximum voltage range borne by the analog-to-digital conversion circuit.
When a nerve signal is collected, the nerve signal is input into a front-end amplifying circuit 1 in a differential mode, the nerve signal comprises a weak local field potential signal in the brain and a stimulation signal to generate a strong stimulation artifact signal, after the nerve signal is amplified by the front-end amplifying circuit 1, a 100uVpp level local field potential signal is amplified to 10 mVpp-100 mVpp after passing through the front-end amplifying circuit, the maximum amplitude of the 10mV level stimulation artifact signal is amplified to 1 Vpp-10 Vpp, and the amplified nerve signal is output to a high-pass filter circuit 2 in a single-ended mode; after the amplified neural signals are subjected to high-pass filtering, baseline drift and low-frequency direct-current components are filtered, at the moment, stimulation artifact signals and harmonic components thereof are attenuated to be approximately-10 Vpp level, local field potential signals are also attenuated to be still-100 mVpp level, and various high-frequency components of the mixed signals are output to the low-pass filter circuit 3 in a single-ended mode; after the stimulation artifact frequency components and harmonic signals thereof in the high-frequency components of the mixed signals are subjected to low-pass filtering, the stimulation artifact frequency components and the harmonic signals thereof are greatly attenuated by about-100 dB and are suppressed from a 10Vpp level to a 100uVpp level, while the local field potential signals are only slightly attenuated by about-3 dB and still are still at a 100mVpp level, the stimulation artifact signals are suppressed, and useful local field potential signals are left, and the clean local field potential signals are output to a next-stage rear-end amplifying circuit 4 in a single-ended manner; after the local field potential signal is amplified by the rear-end amplifying circuit 4, the maximum output amplitude is 1000mVpp level, the single-ended signal is converted into a differential signal, and then the differential signal is filtered by an output differential capacitor Cd and output to the next level of analog-to-digital conversion circuit.
The utility model provides a closed loop deep brain stimulation artifact suppression circuit adopts the full differential low noise structure of differential input and differential output, during the collection, a passageway only needs to set up 1 way circuit, just can satisfy filter circuit's single-ended input and analog-to-digital conversion circuit's differential input simultaneously, need not to consider the inconsistent problem of two way filtering in the differential input, and is further, when setting up more passageways, only need increase the circuit of the same quantity, compare with prior art, can save half chip quantity, reach and reduce the consumption, and therefore the cost is reduced, and the purpose of space is saved.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided would be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for all purposes. The omission in the foregoing claims of any aspect of the subject matter that is disclosed herein is not intended to forego such subject matter, nor should the applicants be construed as having contemplated such subject matter as being part of the disclosed subject matter.
Claims (9)
1. A closed-loop deep brain stimulation artifact suppression circuit, comprising:
the input end of the front-end amplifying circuit is configured to be differential input, and the output end of the front-end amplifying circuit is configured to be single-ended output;
the high-pass filter circuit is connected with the front-end amplifying circuit, the input end of the high-pass filter circuit is configured to be single-ended input, and the output end of the high-pass filter circuit is configured to be single-ended output;
the low-pass filter circuit is connected with the high-pass filter circuit, the input end of the low-pass filter circuit is configured as single-ended input, and the output end of the low-pass filter circuit is configured as single-ended output;
and the rear-end amplifying circuit is connected with the low-pass filter circuit, the input end of the rear-end amplifying circuit is configured to be single-ended input, and the output end of the rear-end amplifying circuit is configured to be differential output.
2. The closed loop deep brain stimulation artifact suppression circuit according to claim 1, wherein the front end amplification circuit comprises an instrumentation amplifier INA1, an adjustable gain resistor Rg1, a 5V DC regulated voltage source, the adjustable gain resistor Rg setting the gain of the front end amplification circuit to 40dB or 60 dB.
3. The closed-loop deep brain stimulation artifact suppression circuit according to claim 1, wherein the high-pass filter circuit is configured as a three-stage 6-stage circuit, each stage of the 2-stage circuit comprises a capacitor Ch1, a resistor Rh1, a capacitor Ch2, a resistor Rh2, an operational amplifier Oph1 and a ± 5V dc power supply, the output end of the front-end amplification circuit is connected to the P end of the operational amplifier Oph1 through the capacitor Ch1 and the capacitor Ch2 in sequence, the resistor Rh1 is connected between the capacitor Ch1 and the capacitor Ch2 at one end and is connected to the N end of the operational amplifier Oph1 at the other end, and the resistor Rh2 is connected between the P ends of the capacitor Ch2 and the operational amplifier Oph1 at one end and is grounded at the other end.
4. The closed-loop deep brain stimulation artifact suppression circuit according to claim 3, wherein a cutoff frequency of the high-pass filter circuit is configured to be 0.05-1 Hz.
5. The closed-loop deep brain stimulation artifact suppression circuit according to claim 1, wherein the low-pass filter circuit is configured as a five-stage 10-stage circuit, each stage of 2-stage circuit includes a capacitor Cl1, a resistor Rl1, a capacitor Cl2, a resistor Rl2, an operational amplifier Opl1 and a ± 5V dc power supply, an output end of the high-pass filter circuit is connected to a P end of the operational amplifier Opl1 through a resistor Rl1 and a resistor Rl2 in sequence, one end of the capacitor Cl1 is connected between the resistor Rl1 and the resistor Rl2, the other end of the capacitor Cl2 is connected to an N end of the operational amplifier Opl1, one end of the capacitor Cl2 is connected between the resistor Rl2 and the P end of the operational amplifier Opl1, and the other end of the capacitor Cl2 is grounded.
6. The closed-loop deep brain stimulation artifact suppression circuit according to claim 5, wherein a cutoff frequency of the low-pass filter circuit is configured to be 40-48 Hz.
7. The closed-loop deep brain stimulation artifact suppression circuit according to claim 1, wherein the back-end amplification circuit comprises an adjustable gain resistor Rf1, an adjustable gain resistor Rf2, a fully differential amplifier INA2 and a + -2.5V DC regulated voltage source, the adjustable gain resistor Rf1 is connected to the P input and P output of the fully differential amplifier INA2, the adjustable gain resistor Rf2 is connected to the N input and N output of the fully differential amplifier INA2, and the adjustable gain resistor Rg sets the gain of the front-end amplification circuit to 0 dB-20 dB.
8. The closed-loop deep brain stimulation artifact suppression circuit according to claim 7, wherein the back-end amplification circuit further comprises a resistor Rb1, a resistor Rb2, and a matching resistor Rt, wherein the output of the low-pass filter circuit is connected to the P-input of a fully-differential amplifier INA2 through a resistor Rb1, the N-input of the fully-differential amplifier INA2 is connected to ground through a resistor Rb2, and the matching resistor Rt is connected to the input of the back-end amplification circuit.
9. The closed-loop deep brain stimulation artifact suppression circuit according to claim 8, characterized in that said back-end amplification circuit further comprises an output reference capacitance Cc connected to a Voc pin of said fully differential amplifier INA2 and an output differential capacitance Cd connected between a P output terminal and an N output terminal of a fully differential amplifier INA 2.
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| CN202122220752.7U CN216319509U (en) | 2021-09-14 | 2021-09-14 | Closed-loop deep brain stimulation artifact suppression circuit |
| PCT/CN2022/099789 WO2023029677A1 (en) | 2021-09-03 | 2022-06-20 | Closed-loop deep brain stimulation decision-making method, apparatus and system, and electronic device |
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| CN202122220752.7U CN216319509U (en) | 2021-09-14 | 2021-09-14 | Closed-loop deep brain stimulation artifact suppression circuit |
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| WO2023029677A1 (en) * | 2021-09-03 | 2023-03-09 | 复旦大学 | Closed-loop deep brain stimulation decision-making method, apparatus and system, and electronic device |
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| WO2023029677A1 (en) * | 2021-09-03 | 2023-03-09 | 复旦大学 | Closed-loop deep brain stimulation decision-making method, apparatus and system, and electronic device |
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