CN216303654U - Ceramic circuit board with bare structure in brazed mode - Google Patents
Ceramic circuit board with bare structure in brazed mode Download PDFInfo
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- CN216303654U CN216303654U CN202120233718.0U CN202120233718U CN216303654U CN 216303654 U CN216303654 U CN 216303654U CN 202120233718 U CN202120233718 U CN 202120233718U CN 216303654 U CN216303654 U CN 216303654U
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Abstract
The utility model discloses a ceramic circuit board brazed with a bare structure, which comprises first ceramic and second ceramic, wherein a first annular circuit with more than two units is manufactured on the front surface of the first ceramic by a semiconductor process and an electroplating process, a packaging circuit conforming to a semiconductor chip is manufactured in the first annular circuit, the second ceramic is manufactured into a bare shape with a smaller diameter than the first annular circuit of the first ceramic, a second annular circuit which is the same as the surface unit of the first ceramic is manufactured, weldable metal is plated on the second annular circuit of the second ceramic by the semiconductor process and the electroplating process, and the first annular circuit of the first ceramic is contacted with the second annular circuit of the second ceramic and is put into a vacuum eutectic furnace together to be sintered into a whole. The ceramics of the utility model have the same thermal expansion coefficient, and can not generate the peeling phenomenon.
Description
Technical Field
The utility model relates to the technical field of circuit boards, in particular to a ceramic circuit board brazed with a bare structure.
Background
At present, the copper electroplating mode is used for overcoming the defects that the difference between the thermal expansion coefficient of copper and the thermal expansion coefficient of ceramic is large, the copper can be easily peeled off under the condition of cold and hot alternation, the aluminum nitride front long dam and the back long circuit have too large thickness difference and are easy to warp and change, when a window sheet is brazed on the copper dam, airtight combination cannot be carried out due to warping, and when a ceramic circuit and a semiconductor chip are welded, a cavity is enlarged and cannot be in tight contact.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problems, the utility model provides the following technical scheme:
the utility model provides a ceramic circuit board brazed with a bare structure,
comprises a first ceramic and a second ceramic,
the first ceramic is provided with more than two first annular circuits on the front surface by a semiconductor process and an electroplating process, a packaging circuit is arranged inside the first annular circuits,
the back surface of the first ceramic is provided with a bonding pad, holes are drilled on the positions of the anode and the cathode of the chip of the packaging circuit and filled with conductive materials to be conducted with the bonding pad on the back surface of the first ceramic,
the second ceramic is made into a bare shape with a smaller diameter than the first annular line of the first ceramic, and made into a second annular line identical to the first ceramic surface unit,
the second annular circuit of the second ceramic is plated with a solderable metal by a semiconductor process and an electroplating process,
and the first annular line of the first ceramic is in contact with the second annular line of the second ceramic, and the first annular line and the second annular line of the second ceramic are put into a vacuum eutectic furnace together and sintered into a whole.
Preferably, the material of the first ceramic and the second ceramic is aluminum oxide and/or aluminum nitride.
Preferably, the first annular lines on the first ceramic are uniformly spaced, and the second annular lines on the second ceramic are uniformly spaced.
Preferably, the first ceramic and the second ceramic are the same in size and material.
Preferably, the solderable metal is plated with titanium by the semiconductor process, copper is plated on the titanium, and thick copper is plated on the surface of the copper by an electroplating process, or the thick copper is plated with silver, or the thick copper is plated with nickel, palladium is plated on the nickel, or the nickel is plated with gold.
Preferably, nitrogen is filled in the vacuum eutectic furnace, and the redox gas introduced into the vacuum eutectic furnace is hydrogen.
Preferably, the first and second circular lines are circular and/or square in shape.
Preferably, the semiconductor process is configured as vacuum sputtering.
The utility model has the beneficial effects
The thermal expansion coefficients of the ceramics are the same, the peeling phenomenon can not be generated, the warping degree, the parallelism and the roughness of the ceramics can be reduced by a mechanical method before the ceramics are used for manufacturing a circuit, the ceramic enclosure dam is welded when a window sheet is manufactured, the air tightness can be kept, the holes are very low, and the holes are very low when the ceramic circuit is welded with a semiconductor chip.
Drawings
FIG. 1 is a schematic view of an assembly structure of a first ceramic and a second ceramic
Fig. 2 shows a first ceramic ring line and a package line formed inside the ring line to conform to a semiconductor chip.
FIG. 3 is a schematic view of a second ceramic ring line and a bare space.
Description of reference numerals: 1-first ceramic, 2-first annular line, 3-second ceramic, 4-second annular line.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
As shown in fig. 1 to 3, the present invention provides a ceramic wiring board soldered with a bare structure,
comprising a first ceramic 1, a second ceramic 3,
more than two first annular circuits 2 are made on the front surface of the first ceramic 1 by a semiconductor process and an electroplating process, a packaging circuit conforming to a semiconductor chip is made inside the first annular circuits 2,
the back surface of the first ceramic 1 is provided with a bonding pad, holes are drilled on the positions of the anode and the cathode of the chip of the packaging circuit and filled with conductive materials to be conducted with the bonding pad on the back surface of the first ceramic 1,
the second ceramic 3 is made into a bare shape with a smaller diameter than the first annular line 2 of the first ceramic 1, and is made into a second annular line 4 which is the same as the surface unit of the first ceramic 1,
the second ring-shaped circuit 4 of the second ceramic 3 is plated with a solderable metal by means of a semiconductor process and an electroplating process,
the first annular line 2 of the first ceramic 1 is in contact with the second annular line 4 of the second ceramic 3, the first annular line and the second annular line are placed into a vacuum eutectic furnace together and sintered into a whole, and nitrogen is filled into the vacuum eutectic furnace in the sintering process, so that the generation of oxides is prevented, and the oxidation is reduced; the redox gas introduced into the vacuum eutectic furnace is set as hydrogen, the reduction function of the hydrogen is realized, the hydrogen is reduced for the workpiece, the oxide is removed, and a good welding effect is achieved;
the thermal expansion coefficients of the ceramics are the same, the peeling phenomenon can not be generated, the warping degree, the parallelism and the roughness of the ceramics can be reduced by a mechanical method before the ceramics are used for manufacturing a circuit, the ceramic enclosure dam is welded when a window sheet is manufactured, the air tightness can be kept, the cavities are very low, and the cavities are very low when the ceramic circuit is welded with a semiconductor chip;
the first ceramic 1 and the second ceramic 3 are the same in size and material, in this embodiment, the first ceramic 1 and the second ceramic 3 are both made of alumina, and the alumina has the characteristics of high temperature resistance and high hardness;
the first annular circuits 2 on the first ceramic 1 are uniformly arranged at intervals, the second annular circuits 4 on the second ceramic 3 are uniformly arranged at intervals, and the intervals are convenient for the integral attractiveness and prevent mutual interference;
in this embodiment, the solderable metal is plated with titanium, the titanium is plated with copper, the surface of the copper is plated with thick copper in an electroplating process, the thick copper is plated with silver, a concave cup is formed in an electroplating manner, and a semiconductor chip can be packaged in the concave cup;
in the embodiment, the first and second annular lines 2 and 4 are square, which is convenient for increasing the practical area;
the semiconductor process is configured as vacuum sputtering.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the utility model.
Claims (7)
1. A ceramic circuit board with a bare structure soldered is characterized in that,
comprises a first ceramic (1) and a second ceramic (3),
the first ceramic (1) is made into more than two first annular circuits (2) on the front surface by a semiconductor process and an electroplating process, a packaging circuit is made inside the first annular circuits (2),
the back surface of the first ceramic (1) is provided with a bonding pad, holes are drilled on the positions of the anode and the cathode of the chip of the packaging circuit and filled with conductive materials to be conducted with the bonding pad on the back surface of the first ceramic (1),
the second ceramic (3) is made into a naked shape with a smaller diameter than the first annular line (2) of the first ceramic (1), and is made into a second annular line (4) which is the same as the surface unit of the first ceramic (1),
the second annular circuit (4) of the second ceramic (3) is plated with weldable metal by means of a semiconductor process and an electroplating process,
the first annular line (2) of the first ceramic (1) is in contact with the second annular line (4) of the second ceramic (3), and the first annular line and the second annular line are placed into a vacuum eutectic furnace together and sintered into a whole.
2. The ceramic wiring board with a bare soldered structure according to claim 1,
the first annular circuits (2) on the first ceramic (1) are arranged at uniform intervals, and the second annular circuits (4) on the second ceramic (3) are arranged at uniform intervals.
3. The ceramic wiring board with a bare soldered structure according to claim 2,
the first ceramic (1) and the second ceramic (3) are same in size and material.
4. The ceramic wiring board with a bare soldered structure according to claim 1,
plating titanium on the weldable metal by adopting the semiconductor process, plating copper on the titanium, and plating thick copper on the surface of the copper by using an electroplating process, plating silver on the thick copper, or plating nickel on the thick copper, plating palladium on the nickel, or plating gold on the nickel.
5. The ceramic wiring board with a bare soldered structure according to claim 1,
and nitrogen is filled in the vacuum eutectic furnace, and the redox gas introduced into the vacuum eutectic furnace is set as hydrogen.
6. The ceramic wiring board with a bare soldered structure according to claim 2,
the first annular line (2) and the second annular line (4) are round and/or square in shape.
7. The ceramic wiring board with a bare soldered structure according to claim 1,
the semiconductor process is configured as vacuum sputtering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120233718.0U CN216303654U (en) | 2021-01-27 | 2021-01-27 | Ceramic circuit board with bare structure in brazed mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120233718.0U CN216303654U (en) | 2021-01-27 | 2021-01-27 | Ceramic circuit board with bare structure in brazed mode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216303654U true CN216303654U (en) | 2022-04-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120233718.0U Active CN216303654U (en) | 2021-01-27 | 2021-01-27 | Ceramic circuit board with bare structure in brazed mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216303654U (en) |
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2021
- 2021-01-27 CN CN202120233718.0U patent/CN216303654U/en active Active
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