CN216290279U - Automatic power-off management circuit, power supply device and electronic equipment - Google Patents
Automatic power-off management circuit, power supply device and electronic equipment Download PDFInfo
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Abstract
The technical scheme of the application provides an automatic power supply cut-off management circuit, a power supply device and electronic equipment, wherein the circuit comprises a power supply output end, a power supply input end, a PMOS (P-channel metal oxide semiconductor) tube, a voltage division unit, a quasi-voltage unit, a switch control unit and a discharge unit; the source electrode of the PMOS tube is connected with the power supply input end, the drain electrode of the PMOS tube is connected with the power supply output end, and the grid electrode of the PMOS tube is connected with the third end of the switch control unit; the first end of the voltage division unit is connected with the power output end, the second end of the voltage division unit is grounded, and the third end of the voltage division unit is connected with the third end of the quasi-voltage unit; the first end of the quasi-voltage unit is connected with the power supply output end, the second end of the quasi-voltage unit is grounded, the fourth end of the quasi-voltage unit is connected with the second end of the switch control unit, the first end of the switch control unit is connected with the source electrode of the PMOS tube, the fourth end of the switch control unit is grounded, and the fifth end of the switch control unit is connected with the second end of the discharge unit; and the first end of the discharge unit is connected with the power output end, and the third end of the discharge unit is grounded. So that the circuit can be automatically switched off when the voltage is low.
Description
Technical Field
The present invention relates to the field of circuit protection, and in particular, to an automatic power-off management circuit, a power supply device, and an electronic apparatus.
Background
The battery is an indispensable accessory in the design of the existing mobile electronic product, the use of the battery electric quantity is not unlimited, the battery is protected by keeping a certain electric quantity, the protection of the battery residual quantity in the prior art is realized by one software system, and the other battery turn-off device is in the two existing protection schemes, the resources required by the system protected by the software system are huge, such as Windows, Android and the like, and obviously, the protection is not suitable for simple devices. Battery shut-off devices require manual operation and are not satisfactory for automation.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, the present invention provides an automatic power cut-off management circuit, which includes a power output terminal, a power input terminal, a PMOS transistor, a voltage dividing unit, a voltage reference unit, a switch control unit, and a discharging unit;
the source electrode of the PMOS tube is connected with the power supply input end, the drain electrode of the PMOS tube is connected with the power supply output end, and the grid electrode of the PMOS tube is connected with the third end of the switch control unit;
the first end of the voltage division unit is connected with the power output end, the second end of the voltage division unit is grounded, and the third end of the voltage division unit is connected with the third end of the quasi-voltage unit;
the first end of the quasi-voltage unit is connected with the power output end, the second end of the quasi-voltage unit is grounded, and the fourth end of the quasi-voltage unit is connected with the second end of the switch control unit;
the first end of the switch control unit is connected with the source electrode of the PMOS tube, the fourth end of the switch control unit is grounded, and the fifth end of the switch control unit is connected with the second end of the discharge unit;
and the first end of the discharge unit is connected with the power output end, and the third end of the discharge unit is grounded.
Furthermore, the voltage division unit comprises a first resistor and a second resistor, the first resistor and the second resistor are connected in series, and a series node between the first resistor and the second resistor is the third end connected to the third end of the quasi-voltage unit.
Further, the quasi-voltage unit comprises a quasi-voltage chip and a third resistor;
the quasi-voltage chip comprises a reference end, a discharge end and a grounding end, the reference end is connected with the voltage dividing unit, the grounding end is grounded, the discharge end is connected with the third resistor in series, the third resistor is connected with the power output end, and a series node between the discharge end and the third resistor serves as the fourth end of the quasi-voltage unit and is connected with the switch control unit.
Further, the switch control unit comprises a PNP triode, a fourth resistor and a fifth resistor;
the emitting electrode of the PNP triode, the fourth resistor and the fifth resistor are sequentially connected in series, the collector electrode of the PNP triode is connected with the source electrode of the PMOS tube, and the base electrode of the PNP triode is connected with the quasi-voltage unit;
a series node between the fourth resistor and the fifth resistor is used as a third end of the switch control unit and is connected with the grid electrode of the PMOS tube, and the fifth resistor is grounded;
and a lead is led out between the emitting electrode of the PNP triode and the fourth resistor and is connected with the discharge unit.
Furthermore, the switch control unit further comprises a first capacitor, one end of the first capacitor is connected with the emitter of the PNP triode, and the other end of the first capacitor is connected with one end of the fifth resistor, which is grounded.
Further, the discharge unit includes a sixth resistor, an NPN triode, a first protection resistor and a second protection resistor;
one end of the sixth resistor is connected with the output end, and the other end of the sixth resistor is connected with a collector of the NPN triode;
one end of the first protection resistor is connected with the base electrode of the NPN triode, the other end of the first protection resistor is connected with the switch control unit, one end of the second protection resistor is connected with the base electrode of the NPN triode, the other end of the second protection resistor is connected with the emitting electrode of the NPN triode, and the emitting electrode of the NPN triode is grounded.
Furthermore, the discharge unit further comprises a second capacitor, one end of the second capacitor is connected with the first protection resistor, and the other end of the second capacitor is connected with an emitter of the NPN triode.
Furthermore, the power supply further comprises a third capacitor and a fourth capacitor, wherein one end of the third capacitor is connected between the PMOS tube and the power output end, the other end of the third capacitor is grounded, one end of the fourth capacitor is connected between the PMOS tube and the power output end, the other end of the fourth capacitor is grounded, and the fourth capacitor is connected with the third capacitor in parallel.
Further, the present application also provides a power supply device using the automatic power-off management circuit according to any one of the above embodiments.
Further, the present application also provides an electronic device using the power supply apparatus according to the above embodiment.
The technical scheme of the application provides an automatic power supply cut-off management circuit, which comprises a power supply output end, a power supply input end, a PMOS (P-channel metal oxide semiconductor) tube, a voltage division unit, a voltage reference unit, a switch control unit and a discharge unit; the source electrode of the PMOS tube is connected with the power supply input end, the drain electrode of the PMOS tube is connected with the power supply output end, and the grid electrode of the PMOS tube is connected with the third end of the switch control unit; the first end of the voltage division unit is connected with the power output end, the second end of the voltage division unit is grounded, and the third end of the voltage division unit is connected with the third end of the quasi-voltage unit; the first end of the quasi-voltage unit is connected with the power output end, the second end of the quasi-voltage unit is grounded, and the fourth end of the quasi-voltage unit is connected with the second end of the switch control unit; the first end of the switch control unit is connected with the source electrode of the PMOS tube, the fourth end of the switch control unit is grounded, and the fifth end of the switch control unit is connected with the second end of the discharge unit; and the first end of the discharge unit is connected with the power output end, and the third end of the discharge unit is grounded. When the voltage of the power output end is higher than the preset voltage, the normal power supply of the power supply can be ensured, and when the voltage is small, the circuit is automatically turned off, so that the battery cannot completely use up the electric quantity, a certain electric quantity of the battery is kept, and the service life of the battery is protected.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
FIG. 1 is a schematic diagram showing an automatic shutdown management circuit in an embodiment of the present application;
FIG. 2 is a schematic diagram showing another structure of an automatic shutdown management circuit in the embodiment of the present application;
fig. 3 shows a schematic structural diagram of a switch control unit in the embodiment of the present application.
And (3) symbol labeling: r1-a first resistor, R2-a second resistor, R3-a third resistor, R4-a fourth resistor, R5-a fifth resistor, R6-a sixth resistor, R7-a first protection resistor, R8-a second protection resistor, U1-a voltage reference chip, Q1-PMOS tube, Q2-PNP triode, Q3-NPN triode, VBAT-power input end, VOUT-power output end, C1-a first capacitor, C2-a second capacitor, C3-a third capacitor and C4-a fourth capacitor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
The present invention will be described in detail with reference to specific examples.
Example 1
The present embodiment provides an automatic power cut-off management circuit for protecting the remaining power of a battery to ensure the service life of the battery, and the automatic power cut-off management circuit is described below with reference to fig. 1.
The automatic cut-off power management circuit comprises a power output end, a power input end, a PMOS (P-channel metal oxide semiconductor) tube, a voltage division unit, a quasi-voltage unit, a switch control unit and a discharge unit.
The power input end and the power output end form an output branch, the PMOS tube is arranged on the output branch as a switch tube, wherein the source electrode of the PMOS tube is connected with the power input end, the drain electrode of the PMOS tube is connected with the power output end, and the grid electrode of the PMOS tube is connected with the switch control unit.
Wherein the first end of voltage division unit is connected with power output end, and the second end ground connection, the third end is connected with the third end of quasi-voltage unit for power input end's voltage is after the voltage division of voltage division unit, with certain proportion get voltage and send into quasi-voltage unit.
And the first end of the quasi-voltage unit is connected with the power output end, the second end of the quasi-voltage unit is grounded, and the fourth end of the quasi-voltage unit is connected with the second end of the switch control unit. The quasi-voltage unit controls the level output to the switch control unit according to the voltage divided by the voltage dividing unit, so as to control the influence of the switch control unit on the PMOS tube, for example, when the divided voltage is high voltage, the quasi-voltage unit sends out high level, and when the divided voltage is low voltage, the quasi-voltage unit sends out low level.
The first end of the switch control unit is connected with the source electrode of the PMOS tube, the fourth end of the switch control unit is grounded, and the fifth end of the switch control unit is connected with the second end of the discharge unit. The switch control unit determines the level of outputting to the grid electrode of the PMOS tube according to the high-low level sent by the quasi-voltage unit, particularly, when the quasi-voltage unit sends the high level, the grid level of the PMOS tube is pulled to be 0, the conduction channel between the source electrode and the drain electrode is opened, a channel is arranged between the unit input end and the power output end, normal power supply can be realized, when the voltage sent by the quasi-voltage unit is the low level, the PMOS optical grid level is enabled to have a high level, the source electrode and the drain electrode are turned off, the circuit between the power output end and the power input end is not conducted, and the turn-off operation in the low voltage process is realized.
The first end of the discharge unit is connected with the power output end, and the third end of the discharge unit is grounded. When the output branch circuit is conducted, the discharging unit is not conducted, and when the output branch circuit is not conducted, the discharging unit is conducted to discharge the residual electric quantity in the circuit, so that the effect of protecting the electronic device is achieved.
In this embodiment, the power input terminal is used to access a stable power source, such as a battery, the voltage of the battery is divided by the voltage dividing circuit, and then the divided voltage is input to the voltage reference unit, and the voltage reference unit sends a corresponding high-low level to the switch control unit according to the divided voltage. When the high level is sent, the switch control unit changes the grid of the PMOS tube into the low level to enable the output branch circuit to be conducted, if the high level is sent, the grid of the PMOS tube is changed into the high level to enable the output branch circuit to be turned off, and in the turning-off process, the residual electric quantity in the circuit can be discharged to the ground from the discharging unit to protect the electronic device.
In this embodiment, the power supply at the power supply output end may be a battery or a battery pack formed by a plurality of batteries, and the triggering condition for turning off the circuit is whether the quasi-voltage unit is subjected to a high voltage or a low voltage, when the voltage of the battery is reduced to a certain limit, the circuit is turned off, and when the voltage of the battery is restored to the high voltage due to charging or replacement, the circuit is turned on again.
Example 2
Further, fig. 2 is a schematic circuit diagram of the auto-power-off management circuit in this embodiment. VBAT is a power input terminal, and in this embodiment, VBAT also indicates a power voltage, where the power source may be a lithium battery with a voltage of 4.2V when the battery voltage is fully charged, and it is specified that when the battery voltage drops to 3.4V, the battery power is considered to be insufficient, and a power-off function should be started to protect the battery margin.
The voltage dividing unit is formed by connecting a first resistor R1 and a second resistor R2 in series, the second resistor R2 is grounded, and the specific resistance values of R1 and R2 are adjusted correspondingly according to the standard voltage of the actually connected power supply, in the embodiment, R1 is 90K ohms, R2 is 250K ohms, a lead is led out from the series point between R1 and R2 to be connected with the reference terminal REF of the quasi-voltage chip U1 in the quasi-voltage unit, so that the quasi-voltage chip U1 can receive the voltage around R2, that is, a relational expression exists, VREF is VBAT ÷ (R1+ R2). times.R 2, if the reference voltage of the reference terminal REF is 2.5V, the condition that when VBAT is less than 3.4V, the output terminal C of the quasi-voltage chip U1 outputs a low level, and when VBAT is more than 3.4V, the output terminal C of the quasi-voltage chip U1 outputs a high level.
The third resistor R3 is a pull-up resistor of the quasi-voltage chip U1, connected to the output terminal C, and used for ensuring stability during power supply, and the ground terminal a is used for grounding.
The circuit control unit is provided with a PNP triode Q2, the base of the Q2 is connected with the output end C and used for receiving high and low levels emitted by the voltage-reference chip U1, and the collector of the Q2 is connected with an output branch at one side of the source of the Q1. According to the working principle of the PNP triode, when the base of Q2 is at a high level, Q2 is not conducting, otherwise, it is conducting at a low level, so when VBAT >3.4V, Q2 is not conducting, so that the voltage at the gate of the PMOS transistor Q1 is 0, and then the conducting channel between the source and the drain is turned on, conversely, when Q2 is conducting, and after voltage division is performed by the fourth resistor R4 and the fifth resistor R5 connected thereto, the voltage around R5 will be present at the gate of Q1, and the specific resistance values of R4 and R5 may be 1K and 10K, so as to ensure that the voltage at the gate of Q1 is sufficiently large, and at the same time, R4 also plays a role in protecting the circuit device.
The emitter of the Q2 is further connected with a discharge unit, the discharge unit is composed of a sixth resistor R6, an NPN triode Q3, a first protection resistor R7 and a second protection resistor R8, one end of R7 is connected with the base of Q3, the other end of R7 is connected with the emitter of Q2, the base of Q3 is preset at one end of R8 and is connected with the emitter of Q3, one end of R6 is connected with a power output end VOUT, the other end of R6 is connected with the collector of Q3 and serves as a protection resistor of Q3, and the emitter of Q3 is grounded.
The Q3, the R7 and the R8 may be integrally formed and integrated together or separately disposed, which is not limited in this application.
When Q2 is turned on, Q1 is turned off, so the collector of Q3 will have a high level and a voltage difference with the emitter is formed, so the collector and emitter of Q3 are turned on, VOUT discharges through R5 and Q3 to discharge the residual charge in the circuit, and when Q2 is turned off, the base of Q3 has no voltage, so the emitter and collector of Q3 are not conductive, and therefore the power output VOUT will not be affected.
In this embodiment, through the partial pressure of partial pressure R1 and R2, make the quasi-voltage chip decide whether the output is high level or low level according to the voltage size that the partial pressure comes, with this on-state of control PNP triode Q2, and then the on-state of control PMOS triode Q1 source and drain, with the on-state between control power input VBAT and the power output VOUT, as long as set up suitable quasi-voltage chip U1 and the resistance of R1 and R2, just can realize the circuit automatic turn-off operation when the battery is in the low-voltage, make when the battery is in low-battery low-voltage, keep certain electric quantity for the battery, in order to protect the life of battery.
Example 3
The present embodiment further provides an automatic power-off management circuit, as shown in fig. 3, which is different from the above embodiments in that the automatic power-off management circuit further includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.
Wherein, C1 and C2 are connected in parallel, one end of each is connected with the output branch at the drain side of Q1, the other end is grounded, and the energy storage and filtering processing as an output power VOUT exists, so that the current is stable when Q1 is conducted.
C3 is connected with R3 and R4 in parallel, one end of C4 is connected with the base of Q3, the other end is connected with the radioactive electrode of Q3, and the time delay processing of disconnection operation is carried out, when the voltage drops to the voltage which can be disconnected, the existence of C3 and C4 is needed, so that the disconnection process is more moderate and can not be immediately disconnected, and the circuit can be better protected by giving buffer time to the electric equipment at the power output end VOUT.
The embodiment of the application also provides a power supply, and the power supply uses the automatic cut-off power supply management circuit in the embodiment.
The embodiment of the application also provides electronic equipment, and the electronic equipment comprises a battery and the power supply.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.
Claims (10)
1. An automatic power supply cut-off management circuit is characterized by comprising a power supply output end, a power supply input end, a PMOS (P-channel metal oxide semiconductor) tube, a voltage division unit, a quasi-voltage unit, a switch control unit and a discharge unit;
the source electrode of the PMOS tube is connected with the power supply input end, the drain electrode of the PMOS tube is connected with the power supply output end, and the grid electrode of the PMOS tube is connected with the third end of the switch control unit;
the first end of the voltage division unit is connected with the power output end, the second end of the voltage division unit is grounded, and the third end of the voltage division unit is connected with the third end of the quasi-voltage unit;
the first end of the quasi-voltage unit is connected with the power output end, the second end of the quasi-voltage unit is grounded, and the fourth end of the quasi-voltage unit is connected with the second end of the switch control unit;
the first end of the switch control unit is connected with the source electrode of the PMOS tube, the fourth end of the switch control unit is grounded, and the fifth end of the switch control unit is connected with the second end of the discharge unit;
and the first end of the discharge unit is connected with the power output end, and the third end of the discharge unit is grounded.
2. The automatic cutout power management circuit of claim 1 wherein said voltage divider unit comprises a first resistor and a second resistor, said first resistor and said second resistor being connected in series, a series node between said first resistor and said second resistor being connected to a third terminal of said voltage divider unit.
3. The automatic power-off management circuit according to claim 1, wherein the quasi-voltage unit comprises a quasi-voltage chip and a third resistor;
the quasi-voltage chip comprises a reference end, a discharge end and a grounding end, the reference end is connected with the voltage dividing unit, the grounding end is grounded, the discharge end is connected with the third resistor in series, the third resistor is connected with the power output end, and a series node between the discharge end and the third resistor serves as the fourth end of the quasi-voltage unit and is connected with the switch control unit.
4. The automatic power-off management circuit as claimed in claim 1, wherein the switching control unit comprises a PNP transistor, a fourth resistor, and a fifth resistor;
the emitting electrode of the PNP triode, the fourth resistor and the fifth resistor are sequentially connected in series, the collector electrode of the PNP triode is connected with the source electrode of the PMOS tube, and the base electrode of the PNP triode is connected with the quasi-voltage unit;
a series node between the fourth resistor and the fifth resistor is used as a third end of the switch control unit and is connected with the grid electrode of the PMOS tube, and the fifth resistor is grounded;
and a lead is led out between the emitting electrode of the PNP triode and the fourth resistor and is connected with the discharge unit.
5. The automatic power-off management circuit as claimed in claim 4, wherein the switch control unit further comprises a first capacitor, one end of the first capacitor is connected to the emitter of the PNP transistor, and the other end of the first capacitor is connected to one end of the fifth resistor, which is grounded.
6. The automatic power-off management circuit according to claim 1, wherein the discharge unit comprises a sixth resistor, an NPN transistor, a first protection resistor, and a second protection resistor;
one end of the sixth resistor is connected with the output end, and the other end of the sixth resistor is connected with a collector of the NPN triode;
one end of the first protection resistor is connected with the base electrode of the NPN triode, the other end of the first protection resistor is connected with the switch control unit, one end of the second protection resistor is connected with the base electrode of the NPN triode, the other end of the second protection resistor is connected with the emitting electrode of the NPN triode, and the emitting electrode of the NPN triode is grounded.
7. The automatic power-off management circuit as claimed in claim 6, wherein the discharge unit further comprises a second capacitor, one end of the second capacitor is connected to the first protection resistor, and the other end of the second capacitor is connected to the emitter of the NPN transistor.
8. The automatic power-off management circuit as claimed in claim 1, further comprising a third capacitor and a fourth capacitor, wherein one end of the third capacitor is connected between the PMOS transistor and the power output terminal, the other end of the third capacitor is grounded, one end of the fourth capacitor is connected between the PMOS transistor and the power output terminal, the other end of the fourth capacitor is grounded, and the fourth capacitor is connected in parallel with the third capacitor.
9. A power supply apparatus characterized by using the automatic turn-off power management circuit according to any one of claims 1 to 8.
10. An electronic device characterized by comprising a battery and a power supply apparatus as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202122761230.8U CN216290279U (en) | 2021-11-11 | 2021-11-11 | Automatic power-off management circuit, power supply device and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202122761230.8U CN216290279U (en) | 2021-11-11 | 2021-11-11 | Automatic power-off management circuit, power supply device and electronic equipment |
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| CN216290279U true CN216290279U (en) | 2022-04-12 |
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