CN216290242U - Battery management circuit and battery management system - Google Patents

Abstract

The utility model discloses a battery management circuit and a battery management system, wherein the battery management circuit comprises: the protection circuit is used for carrying out charge-discharge protection on the main power loop; the analog front-end chip is connected with the protection circuit and is used for acquiring an electric signal of the main power loop; the main control chip is connected with the analog front-end chip and the protection circuit and is used for controlling the protection circuit to execute at least one stage of long-delay charging and discharging protection according to the electric signals collected by the analog front-end chip; the analog front-end chip is also used for controlling the protection circuit to execute at least one stage of short-delay charge and discharge protection according to the collected electric signals; the method has the advantages that the time delay time can be greatly shortened, the timeliness of protection is improved, the safety of a power device on a main power loop is protected, and the safety, reliability and robustness of a battery management system are enhanced.

Description

Battery management circuit and battery management system

Technical Field

The utility model relates to the technical field of batteries, in particular to a battery management circuit and a battery management system.

Background

Most of BMS circuit boards on the market at present are of double-discharge overcurrent protection structures. In addition, the discharge short-circuit protection is also only provided with a triple discharge overcurrent protection structure. This configuration is satisfactory for small capacity packages, but exposes deficiencies and system hazards for packages greater than 50 Ah.

For example, a 50Ah battery pack system, the first-stage discharge overcurrent protection value is 60A, and 5-second delay protection is realized; a secondary overcurrent protection value is 70A, and 500ms of protection is delayed; discharging short-circuit protection 200A, and delaying for 200us protection; the current difference between 70A and 200A exists between the secondary overcurrent protection and the discharge short-circuit protection, and the delay time is the time difference between 500ms and 200 us; this is a huge gap for lithium batteries; if 180A (3.6C) discharge current appears in the middle, the charging and discharging MOS tube with rated current of 50A is difficult to withstand the impact of the large current for 500ms, the unreasonable overcurrent protection structure can gradually greatly consume the service lives of the charging and discharging MOS tube, the main power circuit fuse and the precision resistor, and particularly the service life of the charging and discharging MOS tube is greatly influenced.

In addition, most of the discharging overcurrent protection is directly controlled by the MCU on the BMS circuit board, the delay time is calculated by the MCU through the timer, the delay protection time is only the delay of software processing and does not include the delay time delayed on a hardware circuit, namely, the delay also exists on hardware.

SUMMERY OF THE UTILITY MODEL

The utility model provides a battery management circuit and a battery management system, and aims to solve the problem that a protection circuit has failure risk due to overlong protection delay time when a large-capacity battery pack is subjected to current overcurrent.

In a first aspect, the present invention provides a battery management circuit applied to a battery management system, where the battery management circuit includes: the protection circuit is used for carrying out charge-discharge protection on the main power loop; the analog front-end chip is connected with the protection circuit and is used for acquiring an electric signal of the main power loop; the main control chip is connected with the analog front-end chip and the protection circuit and is used for controlling the protection circuit to execute at least one stage of long-delay charging and discharging protection according to the electric signals collected by the analog front-end chip; the analog front-end chip is also used for controlling the protection circuit to execute at least one stage of short-delay charge and discharge protection according to the collected electric signals.

Furthermore, the battery management circuit further comprises a control circuit, an input end of the control circuit is connected with the main control chip and the analog front-end chip, an output end of the control circuit is connected with the protection circuit, and the control circuit is used for controlling the protection circuit to execute charge and discharge protection according to control signals output by the main control chip and the analog front-end chip.

Further, the control circuit comprises a first control unit and a second control unit, the protection circuit comprises a first protection unit and a second protection unit which are connected to the main power loop, the input end of the first control unit is connected with the main control chip and the analog front end chip, the output end of the first control unit is connected with the first protection unit, the input end of the second control unit is connected with the main control chip and the analog front end chip, and the output end of the second control unit is connected with the second protection unit.

Further, the first control unit and the second control unit are both and gate function circuits.

Furthermore, the first control unit comprises a first and gate, a first input end of the first and gate is connected with the main control chip, a second input end of the first and gate is connected with the analog front-end chip, and an output end of the first and gate is connected with the first protection unit; the second control unit comprises a second AND gate, a first input end of the second AND gate is connected with the main control chip, a second input end of the second AND gate is connected with the analog front end chip, and an output end of the second AND gate is connected with the second protection unit.

Further, the first input end and the second input end of the first and gate and the first input end and the second input end of the second and gate receive level signals, and the level signals include a high level and a low level.

Furthermore, the protection circuit is a discharge short-circuit protection circuit, the first protection unit is a charging MOS transistor, a source electrode and a drain electrode of the charging MOS transistor are connected in series to the main power loop, and a gate electrode of the charging MOS transistor is connected to an output end of the first and gate; the second protection unit is a discharge MOS tube, a source electrode and a drain electrode of the discharge MOS tube are connected in series with the main power loop, and a grid electrode of the discharge MOS tube is connected with an output end of the second AND gate.

Furthermore, the power supply device also comprises a precision resistor, wherein the precision resistor is connected to the main power loop and is also connected with the analog front-end chip.

In a second aspect, the present invention also provides a battery management circuit, including: the device comprises a main control chip, a front end analog chip, a first AND gate function circuit, a second AND gate function circuit, a charging MOS tube, a discharging MOS tube, a sampling resistor, a battery pack and a main power loop; the main power loop is connected with a battery pack, a sampling resistor, a charging MOS tube and a discharging MOS tube, the simulation front end chip is coupled with the battery pack, the simulation front end chip is connected with the sampling resistor, the simulation front end chip is in communication connection with the main control chip, the simulation front end chip is connected with the first AND gate function circuit and the second AND gate function circuit, the main control chip is connected with the first AND gate function circuit and the second AND gate function circuit, the output end of the first AND gate function circuit is connected with the control end of the charging MOS tube, and the output end of the second AND gate function circuit is connected with the control end of the discharging MOS tube.

In a third aspect, the present invention further provides a battery management system, which includes a battery management circuit and a main power loop, where the battery management circuit is connected to the main power loop, and the battery management circuit is the battery management circuit according to the first aspect and the second aspect.

Compared with the prior art, the utility model has the beneficial effects that: the electric signal on the main power loop is collected through the analog front-end chip, the main control chip controls the protection circuit to execute at least one stage of long-delay charge-discharge protection according to the electric signal collected by the analog front-end chip, the analog front-end chip directly controls the protection circuit to execute at least one stage of short-delay charge-discharge protection according to the collected electric signal, therefore, multi-stage protection control can be realized by utilizing the mutual matching of the main control chip and the analog front-end chip, the protection circuit can be controlled without the main control chip by utilizing the direct control of the analog front-end chip, the delay time is greatly shortened, the timeliness of protection is improved, the safety of a power device on the main power loop is protected, and the safety, the reliability and the robustness of a battery management system are enhanced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 shows a schematic diagram of a battery management circuit according to an embodiment of the utility model;

FIG. 2 is a diagram illustrating four-stage discharge overcurrent protection of a battery management circuit according to an embodiment of the utility model;

fig. 3 shows a simplified circuit diagram of a battery pack BMS system according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to fig. 1, an embodiment of the present invention provides a battery management circuit 30 applied to a Battery Management System (BMS), where the battery management circuit 30 includes: the protection circuit 30, the analog front-end chip 20, the main control chip 10 and the protection circuit 30 are used for carrying out charge-discharge protection on the main power loop 40; the analog front-end chip 20 is connected with the protection circuit 30, and the analog front-end chip 20 is used for acquiring an electric signal of the main power loop 40; the main control chip 10 is connected with the analog front-end chip 20 and the protection circuit 30, and the main control chip 10 is used for controlling the protection circuit 30 to execute at least one stage of long-delay charge and discharge protection according to the electric signal acquired by the analog front-end chip 20; the analog front-end chip 20 is further configured to control the protection circuit 30 to perform at least one stage of short-delay charging and discharging protection according to the collected electrical signal.

It should be noted that the protection circuit 30 in this embodiment is a discharge short protection circuit 30, and is used to implement overcurrent protection on the main power loop 40. The protection circuit 30 of this embodiment may be not only the discharge short-circuit protection circuit 30, but also any other protection function for the battery management system may be implemented by using the battery management circuit 30 of this embodiment, and therefore, the protection circuit 30 of this embodiment may also be a protection circuit 30 of another function, and the protection circuit 30 is not limited herein.

In addition, the long delay and the short delay in this embodiment are a set of relative concepts, that is, the delay time of the long delay is longer than that of the short delay. For example, the long delay is 5 seconds, or 500 milliseconds, and the short delay is 50 milliseconds, or 1 millisecond. Therefore, the skilled person can unambiguously determine the difference between the long delay and the short delay, and clearly determine the delay time of the long delay and the short delay.

Specifically, the main control chip 10 in this embodiment refers to an MCU (microcontroller unit) chip, and the MCU chip is mainly used to execute various controls in the battery management system. The analog front end chip 20, afe (analog front end), refers to the battery sampling chip in the BMS specifically for collecting various electrical signals. In the present embodiment, the analog front end chip 20 is used for collecting the current of the main power loop 40.

For the embodiment, the analog front-end chip 20 is adopted to directly control the protection circuit 30, it is emphasized that the MCU is directly used for overcurrent protection of current with large level, the analog front-end chip 20AFE is not adopted to control the charge and discharge MOS transistor, the current is collected by the analog front-end chip 20AFE and then transmitted to the MCU through communication, and the MCU sends a control instruction through program processing, which greatly prolongs the protection time of discharge overcurrent, so that power devices such as the charge and discharge MOS transistor can bear long-term overload pressure, and the potential safety hazard and failure risk of the battery pack are caused. In the embodiment, the analog front-end chip 20 is adopted to directly send the control instruction to the protection circuit 30 to execute the charging and discharging protection, the control instruction does not need to pass through the MCU, the primary processing is reduced, the processing time of the MCU is saved, and meanwhile, the delay time delayed on a hardware circuit is effectively avoided, so that the protection time can be greatly shortened.

It should be further noted that the current dual discharge overcurrent protection structure does not fully utilize the discharge overcurrent protection function of the AFE of the analog front-end chip 20, which causes waste of the discharge overcurrent protection function of the analog front-end chip 20, and this is not a reasonable design of the BMS system. In the embodiment, the analog front-end chip 20 is used for controlling the protection circuit 30 to further realize the charging and discharging protection of the main power loop 40, the functions of discharging overcurrent protection and charging and discharging tube control on the analog front-end chip 20 are fully used, the best use of things can be achieved, the important function of the analog front-end chip in the BMS system is played, and the resource utilization rate of the BMS system is improved on the basis of not increasing the material cost.

In summary, by implementing the present embodiment, the analog front end chip 20 collects the electrical signal on the main power loop 40, the main control chip 10 controls the protection circuit 30 to perform at least one stage of long-delay charging/discharging protection according to the electrical signal collected by the analog front end chip 20, the analog front end chip 20 directly controls the protection circuit 30 to perform at least one stage of short-delay charging/discharging protection according to the collected electrical signal, therefore, the mutual cooperation of the main control chip 10 and the analog front-end chip 20 can realize multi-stage protection control, and the analog front-end chip 20 is used for directly controlling the protection circuit 30, so that the control on the protection circuit 30 can be finished without the main control chip 10, the delay time is greatly shortened, the timeliness of protection is improved, the safety of a power device on the main power loop 40 is protected, and the safety, reliability and robustness of the battery management system are enhanced.

In an embodiment, when the electrical signal is smaller than a preset threshold, the analog front-end chip 20 generates a long-delay control signal and outputs the long-delay control signal to the main control chip 10, and the main control chip 10 controls the protection circuit 30 to perform long-delay charge and discharge protection in response to the long-delay control signal; the analog front-end chip 20 generates a short-delay control signal when the electrical signal is greater than a preset threshold, and controls the protection circuit 30 to perform short-delay charging and discharging protection according to the short-delay control signal.

The existing BMS double-discharge overcurrent protection structure has the problems of safety and reliability for a large-capacity battery pack, and mainly has the problems that the overload time of power devices such as a charge-discharge MOS tube is too long and the service life of the power devices such as the MOS tube is seriously influenced due to too little discharge overcurrent protection current and too short delay time setting level, so that the protection delay time is too long when a large-level current is in overcurrent; safety problems of the battery pack are easily caused, and the reliability of the BMS is also deeply affected. Therefore, in the present embodiment, the main control chip 10 and the analog front-end chip 20 cooperate to perform different delay charging and discharging protection on electrical signals of different levels, so as to implement multi-level protection control. Specifically, in the present embodiment, a preset threshold is set to distinguish a large-scale current from a small-scale current, where the preset threshold is a preset current value, and when the current collected by the analog front-end chip 20 is greater than the preset threshold, it is determined that the current is the large-scale current; when the current collected by the analog front-end chip 20 is smaller than the preset threshold, it is determined that the current is a low-level current. For different levels of current, the analog front-end chip 20 and the main control chip 10 respectively perform charge and discharge protection control, the main control chip 10 controls the protection circuit 30 to perform long-delay charge and discharge protection for a small level of current, and the analog front-end chip 20 controls the protection circuit 30 to perform short-delay charge and discharge protection for a large level of current. Therefore, according to the currents of different grades, the charging and discharging protection of different delay times can be carried out through the main control chip 10 or the analog front-end chip 20, and therefore a multi-level protection structure is achieved.

In the implementation of the control process, the analog front-end chip 20 compares the acquired electrical signal with a preset threshold, and generates a long-delay control signal or a short-delay control signal based on the comparison result. If the long-delay control signal is generated, the long-delay control signal is output to the main control chip 10 and executed by the main control chip 10; if the short-delay control signal is generated, the method can be directly executed.

In an embodiment, the analog front-end chip 20 does not receive a notification instruction signal for successfully performing the long delay control output by the main control chip 10, and the analog front-end chip 20 controls the protection circuit 30 to perform the long delay charging and discharging protection according to the long delay control signal.

The main control chip 10 does not receive the notification instruction signal for successfully executing the short delay control output by the analog front-end chip 20, and the main control chip 10 generates the short delay control signal to control the protection circuit 30 to execute the short delay charging and discharging protection.

The existing design is that the MCU independently controls the circuit of the charging and discharging MOS tube, the dual redundancy design is lacked, the MCU independently controls the charging and discharging tube to have failure risk, and the BMS system design is lacked in safety, reliability and robustness. Therefore, in the present embodiment, when the main control chip 10 performs protection and fails, the analog front-end chip 20 replaces the main control chip 10 to control the protection circuit 30 to perform charge and discharge protection; similarly, when the analog front-end chip 20 fails to perform protection, the main control chip 10 controls the protection circuit 30 to perform charge and discharge protection instead of the analog front-end chip 20. Illustratively, the AFE may perform long-delay charge-discharge protection instead of the MCU if the MCU fails. When the MCU can normally execute the long-delay charging and discharging protection, the MCU sends an instruction to inform the AFE that the protection is not executed, thereby ensuring the safety of the BMS system and the battery pack.

The analog front-end chip 20 sends a notification instruction signal for successful execution to the main control chip 10 after performing the short-delay charge-discharge protection, and similarly, the main control chip 10 sends a notification instruction signal for successful execution to the analog front-end chip 20 after performing the long-delay charge-discharge protection. Therefore, the main control chip 10 and the analog front-end chip 20 can judge whether the control fails according to whether the notification instruction signal of successful execution is received, and if the control fails, the failed control is executed instead of each other, so that all the control can be enabled to take effect.

By implementing the embodiment, the MCU and the analog front-end chip 20 realize dual redundant control on the protection circuit 30, thereby avoiding the risk of single control failure, shortening the short-delay overcurrent protection time, and protecting the safety of the power device; the safety, reliability and robustness of the BMS system are enhanced.

In a specific implementation, the main control chip 10 performs a first-level long-delay charge and discharge protection and a second-level long-delay charge and discharge protection, and the analog front-end chip 20 performs a third-level short-delay charge and discharge protection and a fourth-level short-delay charge and discharge protection; each stage of time delay charge-discharge protection is configured with corresponding electric signals and the level of time delay; when the master control chip 10 executes the secondary long-delay charge-discharge protection, the analog front-end chip 20 executes the secondary long-delay charge-discharge protection; when the analog front-end chip 20 executes the three-level short-delay charge-discharge protection and the four-level short-delay charge-discharge protection, the master control chip 10 executes the three-level short-delay charge-discharge protection and the four-level short-delay charge-discharge protection.

Specifically, each stage of the delayed charging and discharging protection is configured with a corresponding electric signal and a corresponding level of the delay time. For example, the electrical signal level of the first-stage long-delay charge-discharge protection is 60A, the electrical signal level of the second-stage long-delay charge-discharge protection is 70A, the electrical signal level of the third-stage short-delay charge-discharge protection is 100A, and the electrical signal level of the fourth-stage short-delay charge-discharge protection is 150A; the delay time grade of the first-stage long-delay charge-discharge protection is 5 seconds, the delay time grade of the second-stage long-delay charge-discharge protection is 500 milliseconds, the delay time grade of the third-stage long-delay charge-discharge protection is 50 milliseconds, and the delay time grade of the fourth-stage long-delay charge-discharge protection is 1 millisecond.

When the collected current is larger than 60A, performing primary long-delay charge-discharge protection, and delaying for 5 seconds; when the collected current is larger than 70A, secondary long-delay charge-discharge protection is executed, and 500-millisecond delay protection is carried out; when the collected current is more than 100A, three-stage short-delay charge-discharge protection is executed, and 50-millisecond delay protection is carried out; and when the collected current is more than 150A, performing actual short-delay charging and discharging protection, and delaying 1 millisecond protection.

Exemplarily, as shown in fig. 2, the discharging and overcurrent four-stage protection structure of the 50Ah battery pack is schematically illustrated, the first stage and the second stage are controlled by the MCU, the protection delay time is long, the current is transmitted to the MCU by communication after being collected from the AFE, the MCU executes the program code to complete the discharging and overcurrent protection functions of the first stage and the second stage, and the time for transmitting the protection signal is long. The third stage and the fourth stage are controlled by the AFE, the protection delay time is short, the current directly enters the comparator to output an overcurrent protection signal after the current is collected from the AFE, and finally the AFE completes the execution of overcurrent protection, so that the shortest time is consumed for protection, and the timeliness of protection is greatly improved. The current difference between the four-stage overcurrent protection and the discharge short-circuit protection is small, the protection delay time difference is small, and the protection structure is in seamless butt joint with the discharge short-circuit protection; the execution efficiency of the discharge overcurrent protection of the BMS system is improved, and a good protection effect is presented; the safety of the power devices on the main power loop 40 is protected, and the safety, reliability and robustness of the BMS system are enhanced. The figure only shows a four-stage discharge overcurrent protection structure of a 50Ah battery pack, and the structure can be expanded into a battery pack system with 60Ah to 100Ah and can be of a more multi-stage structure.

In an embodiment, the battery management circuit 30 further includes a control circuit, an input end of the control circuit is connected to the main control chip 10 and the analog front-end chip 20, an output end of the control circuit is connected to the protection circuit 30, and the control circuit is configured to control the protection circuit 30 to execute charge and discharge protection according to control signals output by the main control chip 10 and the analog front-end chip 20. The main control chip 10 and the analog front end chip 20 control the protection circuit 30 through the control circuit, which can increase the reliability, robustness and timeliness of the BMS system control protection circuit 30.

Specifically, the control circuit includes a first control unit 51 and a second control unit 52, the protection circuit 30 includes a first protection unit and a second protection unit connected to the main power loop 40, an input end of the first control unit 51 is connected to the main control chip 10 and the analog front end chip 20, an output end of the first control unit 51 is connected to the first protection unit, an input end of the second control unit 52 is connected to the main control chip 10 and the analog front end chip 20, and an output end of the second control unit 52 is connected to the second protection unit.

The first control unit 51 and the second control unit 52 are both and gate functional circuits. It should be noted that the and gate function circuit in this embodiment may have various circuit designs, and no matter what kind of design, as long as the and gate function can be implemented, the and gate function circuit may be specifically designed according to actual requirements.

In one embodiment, the first control unit 51 includes a first and gate, a first input end of the first and gate is connected to the main control chip 10, a second input end of the first and gate is connected to the analog front-end chip 20, and an output end of the first and gate is connected to the first protection unit; the second control unit 52 includes a second and gate, a first input end of the second and gate is connected to the main control chip 10, a second input end of the second and gate is connected to the analog front-end chip 20, and an output end of the second and gate is connected to the second protection unit. The first input end and the second input end of the first AND gate and the first input end and the second input end of the second AND gate receive level signals, and the level signals comprise high levels and low levels.

Specifically, the first control unit 51 at least includes a first and gate, the second control unit 52 at least includes a second and gate, and two input terminals of the first and gate and the second and gate are both connected to the main control chip 10 and the analog front-end chip 20, that is, the first and gate and the second and gate are both controlled by the main control chip 10 and the analog front-end chip 20. The main control chip 10 and the analog front-end chip 20 control the first and second and gates through level signals.

In an embodiment, the protection circuit is a discharge short-circuit protection circuit, the first protection unit is a charging MOS transistor, a source and a drain of the charging MOS transistor are connected in series to the main power loop, and a gate of the charging MOS transistor is connected to an output terminal of the first and gate; the second protection unit is a discharge MOS tube, a source electrode and a drain electrode of the discharge MOS tube are connected in series with the main power loop, and a grid electrode of the discharge MOS tube is connected with an output end of the second AND gate.

Specifically, the protection circuit 30 of the present embodiment is a discharge short-circuit protection circuit, and can perform short-circuit protection on the main power loop when overcurrent occurs. The first and second and gates output a signal for controlling the charging MOS transistor and the discharging MOS transistor to be turned on or off after comparing the level signals input by the main control chip 10 and the analog front-end chip 20, thereby implementing the discharging short-circuit protection.

In one embodiment, the battery management circuit further includes a precision resistor R1, the precision resistor R1 is connected to the main power loop, and the precision resistor R1 is further connected to the analog front end chip 20. The analog front end chip 20 collects the electrical signal on the main power loop through the precision resistor R1. The resistance error of the precise resistor R1 is small, and the precise effect of delay control can be ensured.

Illustratively, referring to fig. 3, this is a simplified block circuit diagram of a battery pack BMS system. Wherein, B1-B10 are battery packs, P + and P-are the positive terminals of the load and the charger and the negative terminals of the load and the charger respectively, Q1 is a charging MOS tube, and Q2 is a discharging MOS tube.

The main display is the control circuit of the charging and discharging MOS tube by the MCU and the AFE chip. CHG1 and DSG1 are output signals of the MCU control charging and discharging MOS tube; CHG2 and DSG2 are output signals of the AFE control charge-discharge MOS tube; in order to improve the reliability, robustness and timeliness of the charging and discharging MOS tube controlled by the BMS system, two signals CHG1 and CHG2 control the switch of the charging MOS tube through an AND gate; the two signals of DSG1 and DSG2 control the switch of the discharge MOS tube through an AND gate; the AND gate can be a specific AND gate device, and can also be an AND gate functional circuit built by independent devices such as a triode or an MOS tube. This dual redundant charge and discharge pipe control circuit not only can use in discharge overcurrent protection function, and any protect function to the BMS system can all realize doubly through this redundant circuit. The dual redundancy control structures are mutually matched to realize, and when the AFE fails and cannot execute protection, the MCU can quickly respond to finish the execution of the protection. For example, the AFE may include a three-stage discharge overcurrent protection function, and a two-stage overcurrent protection setting may be added to the AFE, and if the MCU fails, the AFE may perform the two-stage overcurrent protection function. When the MCU can normally execute the secondary overcurrent protection, the MCU sends an instruction to inform the AFE that the protection is not needed to be executed, thereby ensuring the safety of the BMS system and the battery pack.

An embodiment of the present invention further provides a battery management circuit, including: the main control circuit comprises a main control chip 10, a front-end analog chip 20, a first AND gate function circuit 51, a second AND gate function circuit 52, a charging MOS tube Q1, a discharging MOS tube Q2, a sampling resistor, a battery pack and a main power loop 40; the main power loop 40 is connected with a battery pack, a sampling resistor, a charging MOS transistor Q1 and a discharging MOS transistor Q2, the analog front end chip 20 is coupled with the battery pack, the analog front end chip 20 is connected with the sampling resistor, the analog front end chip 20 is in communication connection with the main control chip 10, the analog front end chip 20 is connected with the first AND gate function circuit 51 and the second AND gate function circuit 52, the main control chip 10 is connected with the first AND gate function circuit 51 and the second AND gate function circuit 52, the output end of the first AND gate function circuit 51 is connected with the control end of the charging MOS transistor Q1, and the output end of the second AND gate function circuit 52 is connected with the control end of the discharging MOS transistor Q2.

In a specific implementation, the analog front-end chip 20 and the main control chip 10 output level signals when controlling the first and gate function circuit 51 and the second and gate function circuit 52. For example, a high level signal, i.e., "1", is output, and a low level signal, i.e., "0", is output. When the first and gate functional circuit 51 receives that the level signals sent by the analog front-end chip 20 and the main control chip 10 are both 1, controlling the charging MOS transistor to turn on the Q1; if the two received level signals are not 1 at the same time, for example, 1/0, 0/1 and 0/0, the charging MOS transistor Q1 is controlled to be turned off. It is to be understood that the charging MOS transistor Q1 may be controlled to be turned off when all of the charging MOS transistors are 1. Similarly, the second and gate functional circuit 52 controls the discharging MOS transistor Q2 to turn on or off through the two level signals output by the analog front-end chip 20 and the main control chip 10, which is not described herein again. In addition, the aforementioned embodiments are referred to when the analog front end chip 20 and the main control chip 10 execute control, and are not described herein again.

The embodiment of the present invention further provides a battery management system, which includes a battery management circuit 30 and a main power loop 40, where the battery management circuit 30 is connected to the main power loop 40, and the battery management circuit 30 is the battery management circuit 30 described in the above embodiment.

Through implementing this embodiment, the multistage discharge overcurrent protection structure of BMS system has protected the safety of the power device on main power circuit 40 such as charge and discharge MOS pipe, fuse and precision resistance effectively, has prolonged their life, has strengthened the security, reliability and the robustness of BMS system. The multi-stage discharge overcurrent protection structure of the BMS system, on one hand, uses the analog front-end chip 20 to execute short-delay protection for large-level current overcurrent protection; on the other hand, the MCU is used for performing long-delay protection on low-level current overcurrent, so that a dual-redundancy charging and discharging MOS (metal oxide semiconductor) tube control system is realized, the dual-redundancy also comprises the mutual matching of the MCU and the AFE, and if one of the MCU and the AFE has a fault, the other one can still perform discharging overcurrent protection.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the utility model, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. A battery management circuit applied to a battery management system is characterized by comprising:

the protection circuit is used for carrying out charge and discharge protection on the main power loop;

the analog front-end chip is connected with the protection circuit and is used for acquiring an electric signal of the main power loop;

the main control chip is connected with the analog front-end chip and the protection circuit and is used for controlling the protection circuit to execute at least one stage of long-delay charging and discharging protection according to the electric signals collected by the analog front-end chip;

the analog front-end chip is also used for controlling the protection circuit to execute at least one stage of short-delay charge and discharge protection according to the collected electric signals.

2. The battery management circuit according to claim 1, further comprising a control circuit, wherein an input terminal of the control circuit is connected to the main control chip and the analog front-end chip, an output terminal of the control circuit is connected to the protection circuit, and the control circuit is configured to control the protection circuit to perform charging and discharging protection according to control signals output by the main control chip and the analog front-end chip.

3. The battery management circuit according to claim 2, wherein the control circuit comprises a first control unit and a second control unit, the protection circuit comprises a first protection unit and a second protection unit connected to a main power loop, an input terminal of the first control unit is connected to the main control chip and the analog front-end chip, an output terminal of the first control unit is connected to the first protection unit, an input terminal of the second control unit is connected to the main control chip and the analog front-end chip, and an output terminal of the second control unit is connected to the second protection unit.

4. The battery management circuit of claim 3, wherein the first control unit and the second control unit are both AND gate function circuits.

5. The battery management circuit according to claim 4, wherein the first control unit comprises a first AND gate, a first input end of the first AND gate is connected with the main control chip, a second input end of the first AND gate is connected with the analog front-end chip, and an output end of the first AND gate is connected with the first protection unit; the second control unit comprises a second AND gate, a first input end of the second AND gate is connected with the main control chip, a second input end of the second AND gate is connected with the analog front end chip, and an output end of the second AND gate is connected with the second protection unit.

6. The battery management circuit of claim 5, wherein the first and second inputs of the first AND gate and the first and second inputs of the second AND gate receive a level signal, the level signal comprising a high level and a low level.

7. The battery management circuit according to claim 6, wherein the protection circuit is a discharge short-circuit protection circuit, the first protection unit is a charging MOS transistor, a source and a drain of the charging MOS transistor are connected in series to the main power loop, and a gate of the charging MOS transistor is connected to an output terminal of the first AND gate; the second protection unit is a discharge MOS tube, a source electrode and a drain electrode of the discharge MOS tube are connected in series with the main power loop, and a grid electrode of the discharge MOS tube is connected with an output end of the second AND gate.

8. The battery management circuit according to any of claims 1-7, further comprising a precision resistor coupled to the main power loop, the precision resistor further coupled to the analog front end chip.

9. A battery management circuit, comprising: the device comprises a main control chip, an analog front-end chip, a first AND gate function circuit, a second AND gate function circuit, a charging MOS tube, a discharging MOS tube, a sampling resistor, a battery pack and a main power loop;

the main power loop is connected with a battery pack, a sampling resistor, a charging MOS tube and a discharging MOS tube, the simulation front end chip is coupled with the battery pack, the simulation front end chip is connected with the sampling resistor, the simulation front end chip is in communication connection with the main control chip, the simulation front end chip is connected with the first AND gate function circuit and the second AND gate function circuit, the main control chip is connected with the first AND gate function circuit and the second AND gate function circuit, the output end of the first AND gate function circuit is connected with the control end of the charging MOS tube, and the output end of the second AND gate function circuit is connected with the control end of the discharging MOS tube.

10. A battery management system comprising battery management circuitry and a primary power loop, the battery management circuitry being connected to the primary power loop, the battery management circuitry being as claimed in any one of claims 1 to 9.

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