CN216288439U

CN216288439U - Stack device

Info

Publication number: CN216288439U
Application number: CN202122482597.6U
Authority: CN
Inventors: 侯彬; 谢永宜
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2021-10-14
Filing date: 2021-10-14
Publication date: 2022-04-12
Anticipated expiration: 2031-10-14

Abstract

The application relates to the technical field of integrated circuits and discloses a stacked device. The stacked device includes: a first wafer including a first circuit; a second wafer comprising a second circuit; the first circuit comprises at least one of a processor, a timer, a bus, an encryption/decryption circuit, a memory access controller and an analog controller; or, the first circuit comprises at least one of a configurable logic circuit, a dedicated SRAM memory, a user-configurable logic circuit, an encoder, a decoder, and Digital IP; the first wafer and the second wafer are stacked and connected to form a stacked device. By the method, the product yield of the stacked device can be improved, the requirement on the maximum exposure area of the stacked device is reduced, the cost of the wafer of the single stacked device is reduced, the development cost of the stacked device is reduced, and the development period is shortened.

Description

Stack device

Technical Field

The present application relates to the field of integrated circuit technology, and more particularly, to a stacked device.

Background

With the rapid development of semiconductor technology towards the deep submicron and even nanometer directions, IC designers integrate more and more systems with complex functions on a single chip to realize electronic systems with smaller size, higher bandwidth and more powerful functions.

If the micro control unit itself is used as a general chip, chips with different control function versions are needed due to different application scene requirements, so as to achieve the purpose of reducing the system cost; an efficient and reliable implementation method for a micro-control unit chip becomes the focus of IC designers.

SUMMERY OF THE UTILITY MODEL

The technical problem that this application mainly solved provides a heap device, can promote the product yield of preparation heap device, reduces the requirement to the maximum exposure area of heap device, and the cost-reduction of the wafer of single heap device, and then reduces the development cost of heap device, shortens development cycle.

In order to solve the above problem, one technical solution adopted by the present application is to provide a stacked device including: a first wafer including a first circuit; a second wafer comprising a second circuit; the first circuit comprises at least one of a processor, a timer, a bus, an encryption/decryption circuit, a memory access controller and an analog controller; or, the first circuit comprises at least one of a configurable logic circuit, a dedicated SRAM memory, a user-configurable logic circuit, an encoder, a decoder, and Digital IP; the first wafer and the second wafer are stacked and connected to form a stacked device.

The first wafer and the second wafer are connected in a laminated bonding mode in a three-dimensional heterogeneous integration mode.

The first wafer and the second wafer are stacked in a 2.5D mode.

Wherein, the number of the first wafer and the second wafer is at least two; the first wafer and the second wafer are stacked at intervals and are connected with each other; or at least two first wafers are stacked, at least two second wafers are stacked, and at least two first wafers and at least two second wafers are stacked.

The second wafer further comprises a self-power circuit, and the first circuit and the second circuit are connected with the self-power circuit so as to supply power to the first circuit and the second circuit through the self-power circuit.

And the side of the first wafer far away from the second wafer further comprises a bonding pad, wherein the bonding pad is used for connecting external devices, and the external devices comprise but are not limited to a storage device and a power supply device.

Wherein, the stacked device is a stacked MCU or a stacked FPGA.

When the stacked device is a stacked MCU, the second circuit comprises at least one of an analog-to-digital conversion circuit, a phase-locked loop, a generator, a sensor, a clock circuit, a driving circuit, a general input/output port, a memory, a fuse and an inductance coil.

The driving circuit comprises an LCD driving unit and/or an LED driving unit.

When the stacked device is a stacked FPGA, the second circuit comprises at least one of a configurable input/output circuit, an Analog IP circuit, a phase-locked loop, a serial circuit, a deserializing circuit, a general input/output port, a memory, a fuse and an inductance coil.

The beneficial effect of this application is: the present application provides stacked devices that are distinguished from the prior art. Through dividing into different first circuit and second circuit with the heap device, and then form first wafer and second wafer, compare all functional circuit integration in the device in the traditional art in same wafer, adopt the same nanometer level preparation technology, whole heap device is realized by first wafer and second wafer integration, single wafer area is less, can promote the product yield of preparation heap device, reduce the requirement to the maximum exposure area of the wafer of heap device, and the cost of single wafer reduces, and then reduces the development cost of device, shorten development cycle.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

fig. 1 is a schematic flowchart illustrating a manufacturing method of a stacked MCU provided in the present application;

FIG. 2 is a schematic structural diagram of an embodiment of a stacked MCU provided in the present application;

FIG. 3 is a schematic diagram of a stacked MCU structure provided in the present application;

FIG. 4 is a schematic diagram of another stacked MCU structure provided in the present application;

FIG. 5 is a schematic structural diagram of another embodiment of a stacked MCU provided in the present application;

FIG. 6 is a schematic structural diagram of another embodiment of a stacked MCU provided in the present application;

FIG. 7 is a schematic structural diagram of another embodiment of a stacked MCU provided in the present application;

FIG. 8 is a schematic structural diagram of another embodiment of a stacked MCU provided in the present application;

FIG. 9 is a schematic structural diagram of another embodiment of a stacked MCU provided in the present application;

FIG. 10 is a schematic structural diagram of another embodiment of a stacked MCU provided in the present application;

FIG. 11 is a schematic structural diagram of an embodiment of an electronic device provided in the present application;

FIG. 12 is a schematic flow chart diagram illustrating an embodiment of a method for fabricating a stacked FPGA;

FIG. 13 is a schematic diagram of an embodiment of a stacked FPGA provided herein;

FIG. 14 is a schematic diagram of a stacked FPGA provided in the present application;

FIG. 15 is a schematic diagram of another stacked FPGA structure provided in the present application;

FIG. 16 is a schematic diagram of another embodiment of a stacked FPGA provided herein;

FIG. 17 is a schematic diagram of another embodiment of a stacked FPGA provided herein;

FIG. 18 is a schematic diagram of another embodiment of a stacked FPGA as provided herein;

FIG. 19 is a schematic diagram of another embodiment of a stacked FPGA as provided herein;

FIG. 20 is a schematic diagram of another embodiment of a stacked FPGA as provided herein;

FIG. 21 is a schematic diagram of another embodiment of a stacked FPGA provided herein;

fig. 22 is a schematic structural diagram of another embodiment of an electronic device provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The stacked device includes a first wafer and a second wafer. The first wafer comprises a first circuit, and the second wafer comprises a second circuit; the first wafer and the second wafer are stacked and connected to form a stacked device.

In this application, the stacked device may be a stacked MCU or a stacked FPGA.

Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a method for manufacturing a stacked MCU provided in the present application. The method comprises the following steps:

step 101: and classifying the functional circuits of the MCU to obtain at least a first circuit and a second circuit.

Wherein the parameter information of the first circuit and the second circuit are different.

Wherein, the parameter information at least comprises any one or combination of the following items: design requirement information of the functional circuit, relation information of performance stability and manufacturing process requirements of the functional circuit, and attribute information of the functional circuit.

The attribute information of the functional circuit may be that the functional circuit is a full-custom circuit, and the design performance of the circuit designed by full-custom is optimal.

For example, functional circuits belonging to a logic function are defined as the same attribute, and functional circuits belonging to an analog function are defined as the same attribute.

In some embodiments, for example, a processor, a timer, a bus, an encryption/decryption circuit, a memory access controller, and an analog controller belonging to a logic function circuit are divided into a first circuit. An analog-to-digital conversion circuit, a phase-locked loop, a generator, a sensor, a clock circuit, a driving circuit, a general input/output port and a memory which belong to an analog function circuit are divided into a second circuit. Thus, the first circuit includes at least one of a processor, a timer, a bus, an encryption/decryption circuit, a memory access controller, and an analog controller. The second circuit includes at least one of an analog-to-digital conversion circuit, a phase-locked loop, a generator, a sensor, a clock circuit, a driving circuit, a general input/output circuit, and a memory.

Step 102: and manufacturing the first circuit by adopting a first manufacturing process to obtain at least one first MCU wafer.

For example, the first MCU wafer may be fabricated by a 12 nm, 22 nm, or 28 nm process.

Step 103: and manufacturing the second circuit by adopting a second manufacturing process to obtain at least one second MCU wafer.

For example, the second MCU wafer may be fabricated by a40 nm or 65 nm process.

In some embodiments, the first manufacturing process and the second manufacturing process may be the same, so that two MCU wafers may be manufactured simultaneously, saving manufacturing time and shortening manufacturing cycle.

Step 104: and stacking and connecting at least one first MCU wafer and at least one second MCU wafer, and packaging into a stacked MCU.

In some embodiments, at least one first MCU die and at least one second MCU die may be integrated or integrated into one package based on 3DIC packaging technology or 2.5D packaging technology, resulting in a stacked MCU.

In some embodiments, the first MCU wafer and the second MCU wafer may be electrically connected in a 2.5D or 3DIC package placed horizontally or vertically and then packaged.

The 2.5D package technique can be adopted to arrange the first MCU wafer and the second MCU wafer in parallel on a Silicon Interposer (Silicon Interposer), and the first MCU wafer and the second MCU wafer are connected through a Micro Bump (Micro Bump) to make the inner metal wire of the Silicon Interposer connect the electronic signals of the first MCU wafer and the second MCU wafer; then, the lower metal bumps (Solder bumps) are connected Through Silicon Vias (TSVs), and the external metal balls are connected through the wire carrier board, so as to realize a tighter interconnection between the first MCU wafer, the second MCU wafer and the package substrate. The first MCU wafer and the second MCU wafer are packaged through a 2.5D packaging technology, and the size of the stacked MCU can be reduced.

The 3DIC packaging technique may be to stack the first MCU wafer and the second MCU wafer on a Silicon Interposer (Silicon Interposer) and directly use a through Silicon via to connect the electrical signals of the stacked first MCU wafer and second MCU wafer. The first MCU wafer and the second MCU wafer are packaged through a 3DIC packaging technology, the size of the stacked MCU can be further reduced, and compared with 2.5D packaging, the area of the MCU can be reduced.

In some embodiments, the first MCU wafer and the second MCU wafer may be manufactured through different foundries, that is, the first MCU wafer and the second MCU wafer may be manufactured at the same time, which saves the manufacturing time.

In some embodiments, the first MCU wafer and the second MCU wafer are connected in a stacked bonding manner by three-dimensional heterogeneous integration to obtain a stacked MCU.

In an application scenario, the following process can be used to fabricate the stacked MCU. First, a first circuit corresponding to a first MCU wafer and a second circuit corresponding to a second MCU wafer of the stacked MCU are determined. And manufacturing a first circuit corresponding to the first MCU wafer and a second circuit corresponding to the second MCU wafer according to different nano-scale manufacturing processes. If so, arranging a first circuit corresponding to the first MCU wafer on the first MCU wafer according to a 12 nm, 22 nm or 28 nm process; and arranging a second circuit corresponding to the second MCU wafer on the second MCU wafer according to a 40-nanometer or 65-nanometer process. The first MCU wafer and the second MCU wafer can be designed, tested and produced respectively according to actual functional circuits. For example, the first MCU wafer and the second MCU wafer can be fabricated at the same time, which can save the fabrication time.

After the first MCU Wafer and the second MCU Wafer are manufactured, a 3DIC (three-dimensional integrated) packaging technology, such as D2D (Die to Die)/D2W (Die to Wafer)/W2W (Wafer to Wafer) system packaging of TSV (Through Silicon Vias), Hybrid Bonding and other processes, may be adopted to integrate or integrate the first MCU Wafer and the second MCU Wafer into one package, for example, at least a portion of the first MCU Wafer and the second MCU Wafer are stacked and electrically connected, thereby completing the manufacturing of the entire stacked MCU.

Through dividing the heap MCU into first MCU wafer and second MCU wafer according to different function, and the nanometer level of the manufacturing process of first MCU wafer and second MCU wafer is different, compare in that all functional circuit of MCU integrate in same wafer among the conventional art, adopt the same nanometer level manufacturing process, whole heap MCU is realized by first MCU wafer and the integration of second MCU wafer, each MCU wafer area is less, can promote the product yield of preparation MCU, reduce the requirement to MCU's maximum exposure area, and the cost reduction of single MCU wafer. And at least partial areas of the first MCU wafer and the second MCU wafer are stacked and connected, so that the global wiring in the stacked MCU is shortened, the access speed among all functional circuits of the stacked MCU can be increased, the power consumption is reduced, and the overall performance is improved.

Furthermore, after the first MCU wafer or the second MCU wafer is manufactured, verified and tested successfully, the performance and the function of the first MCU wafer or the second MCU wafer are determined, repeated research and development are not needed to follow the migration of process nodes, a large amount of research and development costs of manpower, hardware resources and the like are saved, the design efficiency is improved, and the development period is shortened; meanwhile, the repeated authorization cost of certain authorized IPs can be saved.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a stacked MCU provided in the present application. The stacked MCU100 includes a first MCU wafer 10 and a second MCU wafer 20.

The first MCU wafer 10 includes a first circuit. Second MCU wafer 20 includes a second circuit.

In some embodiments, the first MCU wafer 10 and the second MCU wafer 20 may be stacked and connected at least in part, the first MCU wafer 10 and the second MCU wafer 20 have different nano-scale manufacturing processes, and the first MCU wafer and the second MCU wafer are electrically connected to form a stacked Micro Controller Unit (MCU).

The micro control Unit properly reduces the frequency and specification of a Central Processing Unit (CPU), and integrates peripheral interfaces such as a memory (memory), a counter (Timer), a USB (universal serial bus), an A/D (analog/digital) converter, a UART (universal asynchronous receiver/transmitter), a PLC (programmable logic controller), a DMA (direct memory access), and the like, even an LCD (liquid crystal display) driving circuit on a single chip to form a chip-level computer.

In some embodiments, first MCU wafer 10 and second MCU wafer 20 may be electrically connected in a 2.5D or 3DIC package placed horizontally or vertically, and then packaged to obtain stacked MCU 100.

In some embodiments, the nanoscale of the fabrication process of first MCU wafer 10 and second MCU wafer 20 may be the same.

In some embodiments, the first MCU wafer 10 and the second MCU wafer 20 may be classified according to logic functions and analog functions. If the logic function is defined as a first circuit and the simulation function is defined as a second circuit, the first circuit in the first MCU wafer 10 corresponds to the logic function, and the second circuit in the second MCU wafer 20 corresponds to the simulation function. If the logic function is defined as the second circuit and the analog function is defined as the first circuit, the first circuit in the first MCU wafer 10 corresponds to the analog function, and the second circuit in the second MCU wafer 20 corresponds to the logic function.

In some embodiments, the first MCU wafer 10 and the second MCU wafer 20 are stacked and connected at least partially. For example, referring to fig. 3, the first MCU wafer 10 and the second MCU wafer 20 are stacked and connected in a partial region. Compared with the prior art in which circuits corresponding to all functional circuits are integrated on the same MCU wafer, the first MCU wafer 10 and the second MCU wafer 20 are partially stacked, so that the wiring between the corresponding functional circuits on the first MCU wafer 10 and the second MCU wafer 20 is shortened, the access speed between the circuits corresponding to the functional circuits can be increased, the power consumption is reduced, and the overall performance is improved.

For example, referring to fig. 4, the first MCU wafer 10 and the second MCU wafer 20 are stacked and connected. Compared with the conventional technology in which all functional circuits are integrated on the same MCU wafer, the first MCU wafer 10 and the second MCU wafer 20 are stacked, so that the wiring between the corresponding functional circuits on the first MCU wafer 10 and the second MCU wafer 20 is shortened, the access speed between the functional circuits can be increased, the power consumption is reduced, and the overall performance is improved.

It is understood that the specific stacking manner may be set according to the actual sizes of the first MCU wafer 10 and the second MCU wafer 20. When the stacked MCU100 includes a plurality of first MCU wafers 10 and a plurality of second MCU wafers 20, the first MCU wafers 10 and the second MCU wafers 20 may be stacked one on another. For example, a second MCU wafer 20 is disposed between two first MCU wafers 10. For example, a first MCU wafer 10 is disposed between two second MCU wafers 20.

In this embodiment, by dividing the stacked MCU100 into the first MCU wafer 10 and the second MCU wafer 20 according to different functions, compared to the conventional art in which all functional circuits of the MCU are integrated on the same MCU wafer, the same nano-scale manufacturing process is adopted, the whole stacked MCU100 is implemented by integrating the first MCU wafer 10 and the second MCU wafer 20, each wafer has a smaller area, which can improve the yield of MCU manufacturing products, reduce the requirement for the maximum exposure area of the MCU, and reduce the cost of a single MCU wafer.

In some embodiments, the first MCU wafer 10 and the second MCU wafer 20 are fabricated by different nano-scale fabrication processes, and a reasonable fabrication process can be employed based on different functional circuits, compared to the conventional art in which all functional circuits of the MCU are integrated on the same MCU wafer, and the same nano-scale fabrication process is employed, the whole stacked MCU100 is implemented by integrating the first MCU wafer 10 and the second MCU wafer 20, and each MCU wafer has a smaller area, which can improve the yield of MCU fabrication, reduce the requirement for the maximum exposure area of the MCU, and reduce the cost of a single MCU wafer.

In some embodiments, the first MCU wafer 10 and the second MCU wafer 20 are stacked and connected at least partially, so that the global wiring in the stacked MCU100 is shortened, the access speed between the functional circuits of the stacked MCU100 can be increased, the power consumption can be reduced, and the overall performance can be improved.

Referring to fig. 5, fig. 5 is a schematic structural diagram of another embodiment of the stacked MCU provided in the present application. The stacked MCU100 includes a first MCU wafer 10 and a second MCU wafer 20. The first MCU wafer 10 includes a first circuit. Second MCU wafer 20 includes a second circuit.

The first circuit may be a logic function circuit. The first circuit includes at least one of a processor 111, a timer 112, a bus 113, an encryption/decryption circuit 114, a memory access controller 115, and an analog controller 116.

Alternatively, the processor 111 may be an Arm Cortex.

The Bus 113 may include at least one of USB (Universal Serial Bus), USART (Universal Synchronous/Asynchronous Receiver/Transmitter), SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), AHB (Advanced High Performance Bus), and APB (Advanced Peripheral Bus).

The Encryption/decryption circuit 114 may employ AES (Advanced Encryption Standard).

The memory access controller 115 may be a direct memory access controller that allows hardware devices of different speeds to communicate without relying on the extensive interrupt load of the micro-control unit. Otherwise, the mcu needs to copy each piece of data from the source to the register and then write them back to the new place again. During this time, the micro control unit is not available for other operations.

The simulation controller 116 may implement simulation of the control operation by logic code.

Optionally, the first circuit may further include a Static Random Access Memory (SRAM).

The second circuit comprises an analog function circuit and a special function circuit. The analog function circuitry includes at least one of analog to digital conversion circuitry 211, phase locked loop 212, generator 213, sensor 214, clock circuitry 215, driver circuitry 216, general purpose input/output port 217, and memory 218. The special function circuit comprises at least one of a memory, a fuse and an inductance coil.

Wherein the sensor 214 comprises a temperature sensor and/or a capacitive sensor.

The clock circuit 215 may be a low frequency external clock and/or a high frequency external clock.

The driving circuit 216 includes an LCD (Liquid Crystal Display) driving unit and/or an LED (light emitting diode) driving unit.

The memory 218 includes a ROM unit and/or a FLASH unit.

In some embodiments, the analog function circuit further comprises a digital-to-analog conversion circuit, which is a device that converts digital quantities to analog. The digital-to-analog conversion circuit is basically composed of 4 parts, namely a weight resistor network, an operational amplifier, a reference power supply and an analog switch.

The analog-to-digital conversion circuit 211 generally includes a digital-to-analog conversion circuit, and the analog-to-digital conversion circuit 211 is an a/D converter, referred to as ADC for short, and is a device for converting a continuous analog signal into a discrete digital signal.

It can be understood that the logic function circuit has the characteristics of flexible and changeable function requirements, sensitive performance to the manufacturing process and the like. The analog function circuit has the characteristics of stable performance, insensitivity to the manufacturing process, relatively fixed function requirement and the like.

Based on this, the manufacturing process of the first MCU wafer 10 can be a 12 nm, 22 nm or 28 nm process; the second MCU wafer 20 may be fabricated by a40 nm or 65 nm process. By adopting different nanometer process procedures for different functional circuits, the manufacturing cost can be saved.

In other embodiments, the nano-scale process of the first MCU wafer 10 may be a 5 nm or 7 nm process.

The number of the circuits is set according to the actual requirement of the stacked MCU100, and the circuits are connected through reasonable wiring resources to complete configuration.

In this embodiment, the stacked MCU100 is divided into the first MCU wafer 10 and the second MCU wafer 20 according to different functions, and the first MCU wafer 10 and the second MCU wafer 20 have different nano-levels, compared to the conventional art in which all functional circuits of the MCU are integrated on the same MCU wafer, the stacked MCU100 is implemented by integrating the first MCU wafer 10 and the second MCU wafer 20, and each MCU wafer has a smaller area, which can improve the yield of MCU manufacturing, reduce the requirement for the maximum exposure area of the MCU, and reduce the cost of the single MCU wafer. Because of the first MCU wafer 10 integrated logic function circuit, then compare in the traditional technology all functional circuits of MCU integrate in same MCU wafer, the analog function circuit will also occupy the silicon chip position on the MCU wafer, the silicon chip position on the first MCU wafer 10 can all set up logic function circuit, then on the silicon chip of the same area, can realize the scale bigger, the function is abundanter logic function circuit, can promote the performance of heap MCU100, and, first MCU wafer 10 and second MCU wafer 20 are at least partly regional range upon range of setting and connect, make the global wiring in heap MCU100 shorten, can promote the access speed between each functional circuit of heap MCU100, reduce the consumption, promote the wholeness can.

Referring to fig. 6, fig. 6 is a schematic structural diagram of another embodiment of a stacked MCU provided in the present application, where the stacked MCU100 includes a first MCU wafer 10 and a second MCU wafer 20. The first MCU wafer 10 includes a first circuit. Second MCU wafer 20 includes a second circuit.

The stacked MCU100 is similar to the stacked MCU100 of any of the above embodiments, except that the first MCU wafer 10 is provided with a first communication interface 12; a second communication interface 22 is arranged on the second MCU wafer 20; the first MCU wafer 10 and the second MCU wafer 20 are stacked at least partially and connected via the first communication interface 12 and the second communication interface 22.

Compared with the conventional technology in which all functional circuits are integrated on the same MCU wafer, the first MCU wafer 10 and the second MCU wafer 20 are partially stacked, so that the connection between the first communication interface 12 and the second communication interface 22 is shortened, the access speed between the functional circuits can be increased, the power consumption can be reduced, and the overall performance can be improved.

Referring to fig. 7, fig. 7 is a schematic structural diagram of another embodiment of the stacked MCU provided in the present application. The stacked MCU100 includes a plurality of first MCU wafers 10 and a plurality of second MCU wafers 20. At least partial areas of each first MCU wafer 10 and at least two second MCU wafers 20 are stacked and connected.

It can be understood that, according to the size of the MCU wafer, the stacking relationship between the first MCU wafer 10 and the second MCU wafer 20 can be set reasonably.

By the mode, the connection between the MCU wafer and the MCU wafer is shortened, the access speed between functional circuits can be improved, the power consumption is reduced, and the overall performance is improved.

Referring to fig. 8, fig. 8 is a schematic structural diagram of another embodiment of the stacked MCU provided in the present application. The stacked MCU100 includes a plurality of first MCU wafers 10 and a plurality of second MCU wafers 20. Each second MCU wafer 20 and at least a part of the regions of at least two first MCU wafers 10 are stacked and connected.

In other embodiments, each second MCU wafer 20 and each first MCU wafer 10 are disposed on the same plane and electrically connected through a common substrate or silicon medium.

In other embodiments, the first MCU wafer 10 and the second MCU wafer 20 are stacked and spaced apart from each other and connected to each other.

In other embodiments, as shown in fig. 9, at least two first MCU wafers 10 are stacked, at least two second MCU wafers 20 are stacked, and at least two first MCU wafers 10 stacked and at least two second MCU wafers 20 stacked are stacked. By the mode, the connection between the MCU wafer and the MCU wafer is shortened, the access speed between functional circuits can be improved, the power consumption is reduced, and the overall performance is improved.

In some embodiments, the second MCU wafer 20 further includes a self-power circuit, and the first circuit and the second circuit are connected to the self-power circuit to supply power to the first circuit and the second circuit through the self-power circuit. The self-powered circuit may include a power supply, which may be a rechargeable power supply that charges when connected to an external power source to ensure sufficient power.

In some embodiments, referring to fig. 10, the stacked MCU100 includes a first MCU wafer 10, a second MCU wafer 20, and a pad 30. The bonding pad 30 is disposed on a side of the first MCU wafer 10 away from the second MCU wafer 20, and the bonding pad 30 is used to connect to an external device, which may be a memory device or a power device. The bonding pad 30 is electrically connected to a first circuit on the first MCU wafer 10, so as to enable the first MCU wafer 10 and the second MCU wafer 20 to communicate with an external device.

Referring to fig. 11, fig. 11 is a schematic structural diagram of an embodiment of an electronic device provided in the present application. The electronic device 200 comprises the stacked MCU100 as described in any of the above embodiments.

The stacked MCU100 is a stacked MCU manufactured by any of the above-mentioned methods.

Referring to fig. 12, fig. 12 is a schematic flowchart of an embodiment of a method for manufacturing a stacked FPGA provided in the present application. The method comprises the following steps:

step 301: and classifying the functional circuits of the FPGA to obtain at least a first circuit and a second circuit, wherein the parameter information of the first circuit and the second circuit is different.

In some embodiments, for example, the configurable logic circuit, the dedicated SRAM memory, the user-configurable logic circuit, the encoder, the decoder, and the Digital IP belonging to the logic function circuit are divided into a first circuit. The configurable input/output circuit, the Analog IP circuit, the phase-locked loop, the serial circuit, the deserializing circuit, the general input/output circuit and the memory belonging to the Analog function circuit are divided into a second circuit.

Step 302: and manufacturing the first circuit by adopting a first manufacturing process to obtain at least one first FPGA wafer.

For example, the first FPGA wafer may be fabricated by 12 nm, 22 nm, or 28 nm processes.

Step 303: and manufacturing the second circuit by adopting a second manufacturing process to obtain at least one second FPGA wafer.

For example, the second FPGA wafer may be fabricated by a40 nm or 65 nm process.

In some embodiments, the first manufacturing process and the second manufacturing process can be the same, and two FPGA wafers can be manufactured simultaneously, so that the manufacturing time is saved, and the manufacturing period is shortened.

Step 304: and stacking at least one first FPGA wafer and at least one second FPGA wafer to obtain the stacked FPGA.

In some embodiments, the functional circuits of the FPGA may be classified according to parameter information of the functional circuits to obtain at least a first circuit and a second circuit.

In some embodiments, at least one first FPGA wafer and at least one second FPGA wafer may be integrated or integrated, e.g., integrated or integrated into one package case, based on 3DIC packaging technology, resulting in a stacked FPGA. The Programmable Device may be an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device).

In some embodiments, the first FPGA wafer and the second FPGA wafer may be electrically connected using a 2.5D or 3DIC package format placed horizontally or vertically and then packaged.

The 2.5D packaging technique is adopted, wherein a first FPGA wafer and a second FPGA wafer are arranged in parallel on a Silicon Interposer (Silicon Interposer), and are firstly connected through Micro bumps (Micro bumps), so that the inner metal wires of the Silicon Interposer can be connected with the electronic signals of the first FPGA wafer and the second FPGA wafer; then, the metal bumps (Solder bumps) are connected to the lower portion Through Silicon Vias (TSVs), and the external metal balls are connected to the first FPGA wafer, the second FPGA wafer and the package substrate through the wire carrier, so as to achieve a tighter interconnection between the first FPGA wafer and the second FPGA wafer. The first FPGA wafer and the second FPGA wafer are packaged through a 2.5D packaging technology, and the size of the stacked FPGA can be reduced.

The 3DIC packaging technique may be to stack the first FPGA wafer and the second FPGA wafer on a Silicon Interposer (Silicon Interposer) and directly use through Silicon vias to connect the electronic signals of the stacked first FPGA wafer and the second FPGA wafer. The first FPGA wafer and the second FPGA wafer are packaged through a 3DIC packaging technology, the size of the stacked FPGA can be further reduced, and the area of the FPGA can be reduced compared with a 2.5D packaging mode.

In some embodiments, the first FPGA wafer and the second FPGA wafer may be fabricated by different foundries, that is, the first FPGA wafer and the second FPGA wafer may be fabricated at the same time, which saves the fabrication time.

In an application scenario, a logic function circuit and an analog function circuit of a stacked FPGA are determined first. And manufacturing the functional circuit corresponding to the first FPGA wafer and the functional circuit corresponding to the second FPGA wafer according to different nano-level manufacturing processes. For example, the functional circuit corresponding to the first FPGA wafer is integrated on the first FPGA wafer according to a 12 nm, 22 nm or 28 nm process; and integrating the functional circuit corresponding to the second FPGA wafer on the second FPGA wafer according to the 40-nanometer or 65-nanometer process. The first FPGA wafer and the second FPGA wafer can be designed, tested and produced respectively according to actual functional circuits. For example, the first FPGA wafer and the second FPGA wafer can be fabricated at the same time, which can save fabrication time.

After the first FPGA Wafer and the second FPGA Wafer are manufactured, a 3DIC (three-dimensional integrated circuit) packaging technology, such as D2D (Die to Die)/D2W (Die to Wafer)/W2W (Wafer to Wafer) system packaging of TSV (Through Silicon Vias), Hybrid Bonding and other processes, may be adopted to integrate the first FPGA Wafer and the second FPGA Wafer into one package, for example, at least a part of the first FPGA Wafer and the second FPGA Wafer are stacked and connected in a region, thereby completing the manufacturing of the entire stacked FPGA.

Through dividing the stack FPGA into a first FPGA wafer and a second FPGA wafer according to different attribute regions, and the nanometer level of the manufacturing process of the first FPGA wafer and the second FPGA wafer is different, compared with the traditional technology in which all functional circuits of the FPGA are integrated on the same FPGA wafer, the same nanometer level manufacturing process is adopted, the whole stack FPGA is realized by integrating the first FPGA wafer and the second FPGA wafer, the area of each FPGA wafer is small, the product yield of manufacturing the FPGA can be improved, the requirement on the maximum exposure area of the FPGA is reduced, and the cost of a single FPGA wafer is reduced. And at least partial areas of the first FPGA wafer and the second FPGA wafer are stacked and connected, so that the global wiring in the stacked FPGA is shortened, the access speed among all functional circuits of the stacked FPGA can be increased, the power consumption is reduced, and the overall performance is improved.

Furthermore, after the first FPGA wafer or the second FPGA wafer is manufactured, verified and tested successfully, the performance and the function of the first FPGA wafer or the second FPGA wafer are determined, repeated research and development are not needed to follow the migration of process nodes, a large amount of research and development cost such as manpower and hardware resources is saved, the design efficiency is improved, and the development period is shortened; meanwhile, the repeated authorization cost of certain authorized IPs can be saved.

Referring to fig. 13, fig. 13 is a schematic structural diagram of an embodiment of the stacked FPGA provided in the present application. The stacked FPGA400 includes a first FPGA wafer 40 and a second FPGA wafer 50.

Wherein, a first circuit is disposed on the first FPGA wafer 40. A second circuit is disposed on the second FPGA wafer 50. The parameter information of the first circuit and the second circuit are different.

In some embodiments, the first FPGA wafer 40 and the second FPGA wafer 50 may be stacked and connected at least in part, the first FPGA wafer 40 and the second FPGA wafer 50 may be fabricated by different nano-scale processes, and the first FPGA wafer 40 and the second FPGA wafer 50 are electrically connected to form a stacked FPGA or a stacked CPLD (Complex Programmable Logic device).

In some embodiments, first FPGA wafer 40 and second FPGA wafer 50 may be electrically connected in a 2.5D or 3DIC package that is placed horizontally or vertically and then packaged.

In some embodiments, the fabrication process of the first FPGA wafer 40 and the second FPGA wafer 50 may be the same at the nanometer scale.

The basic structure of the FPGA comprises a programmable input/output circuit, a configurable logic circuit, a digital clock management circuit, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional circuit. These modules may be classified according to logic function circuits and analog function circuits. If the configurable logic module is a logic function circuit, the phase-locked loop in the digital clock management circuit is an analog function circuit, and the clock distribution circuit in the digital clock management circuit is a logic function circuit. The programmable input and output circuit is an analog function circuit, and the embedded block RAM and the embedded special hard core are logic function circuits.

In some embodiments, the first FPGA wafer 40 and the second FPGA wafer 50 may be categorized by logic functions and analog functions. If the logic function is defined as a first circuit and the analog function is defined as a second circuit, the first circuit in the first FPGA wafer 40 corresponds to the logic function and the second circuit in the second FPGA wafer 50 corresponds to the analog function. For another example, if the logic function is defined as a second circuit and the analog function is defined as a first circuit, the first circuit in the first FPGA wafer 40 corresponds to the analog function, and the second circuit in the second FPGA wafer 50 corresponds to the logic function.

In some embodiments, the first FPGA wafer 40 and the second FPGA wafer 50 are at least partially area stacked and connected. For example, referring to fig. 14, the first FPGA wafer 40 and the second FPGA wafer 50 are partially stacked and connected. Compared with the prior art in which all functional circuits are integrated on the same FPGA wafer, the first FPGA wafer 40 and the second FPGA wafer 50 are partially stacked, so that the wiring between the corresponding functional circuits on the first FPGA wafer 40 and the second FPGA wafer 50 is shortened, the access speed between the functional circuits can be increased, the power consumption is reduced, and the overall performance is improved.

For example, referring to FIG. 15, a first FPGA wafer 40 and a second FPGA wafer 50 are stacked and connected. Compared with the prior art in which all the functional circuits are integrated on the same FPGA wafer, the first FPGA wafer 40 and the second FPGA wafer 50 are stacked, so that the wiring between the corresponding functional circuits on the first FPGA wafer 40 and the second FPGA wafer 50 is shortened, the access speed between the functional circuits can be increased, the power consumption is reduced, and the overall performance is improved.

It will be appreciated that the particular stacking pattern may be configured according to the physical dimensions of the first FPGA wafer 40 and the second FPGA wafer 50. When a plurality of first FPGA wafers 40 and a plurality of second FPGA wafers 50 are included in stacked FPGA400, first FPGA wafer 40 and second FPGA wafer 50 may be stacked on top of each other. For example, a second FPGA wafer 50 is disposed between two first FPGA wafers 40. For example, a first FPGA wafer 40 is disposed between two second FPGA wafers 50.

In this embodiment, by dividing the stacked FPGA400 into the first FPGA wafer 40 and the second FPGA wafer 50 according to different functions, compared to the conventional technology in which all functional circuits of the FPGA are integrated on the same FPGA wafer, the same nano-level manufacturing process is adopted, the entire stacked FPGA400 is realized by integrating the first FPGA wafer 40 and the second FPGA wafer 50, each FPGA wafer has a smaller area, the yield of products for manufacturing the FPGA can be improved, the requirement for the maximum exposure area of the FPGA is reduced, and the cost of a single FPGA wafer is reduced.

In some embodiments, the first FPGA wafer 40 and the second FPGA wafer 50 are fabricated by different nanoscale fabrication processes, and a reasonable fabrication process can be employed based on different functional circuits, compared to the conventional technology in which all functional circuits of the FPGA are integrated on the same FPGA wafer, and the same nanoscale fabrication process is employed, the entire stacked FPGA400 is implemented by integrating the first FPGA wafer 40 and the second FPGA wafer 50, and each FPGA wafer has a smaller area, which can improve the yield of the product for fabricating the FPGA, reduce the requirement for the maximum exposure area of the FPGA, and reduce the cost of a single FPGA wafer.

In some embodiments, the first FPGA wafer 40 and the second FPGA wafer 50 are stacked and connected at least partially, which can shorten global routing in the stacked FPGA400, improve access speed between functional circuits of the stacked FPGA400, reduce power consumption, and improve overall performance.

Referring to fig. 16, fig. 16 is a schematic structural diagram of another embodiment of the stacked FPGA provided in the present application. The stacked FPGA400 includes a first FPGA wafer 40 and a second FPGA wafer 50. First circuitry is integrated into first FPGA wafer 40. Second circuitry is integrated into the second FPGA wafer 50.

The first circuit is a logic function circuit. The first circuit includes at least one functional circuit of configurable logic circuit 411, dedicated SRAM memory 412, user configuration logic circuit 413, encoder 414, decoder 415, and Digital IP 416.

The Configurable Logic circuit 411 may be a Configurable Logic Block (CLB) and may include a Configurable switch matrix, which is composed of a selection circuit (multiplexer), a flip-flop and 4 or 6 inputs. Programming of specific logic functions may be accomplished in conjunction with the dedicated SRAM memory 412. The Dedicated SRAM Memory 412 may be a DSRAM (Dedicated Static Random Access Memory). The dedicated SRAM memory 412 may also be configured as synchronous, asynchronous, single-port, dual-port RAM or FIFO, or ROM.

The user configuration logic 413 supports the functions associated with user programming control.

The encoder 414 is capable of encoding data in accordance with the configuration of the configurable logic circuit 411.

Decoder 415 is capable of decoding data in accordance with the configuration of configurable logic circuit 411.

Digital IP 416 may include an embedded processor or the like.

The second circuit comprises an analog function circuit and a special function circuit. The Analog function circuit comprises at least one of a configurable input/output circuit 511, an Analog IP circuit 512, a phase-locked loop 513, a serial circuit 514, a deserializing circuit 515 and a general input/output circuit 516; the special function circuit mainly includes a memory, such as at least one of an EEPROM (Electrically Erasable and Programmable read only memory), a fuse, and an inductor.

The configurable input output circuit 511 supports various general IO protocols.

The phase locked loop 513 is a negative feedback control system that uses the phase synchronized generated voltage to tune the voltage controlled oscillator to generate the target frequency. The frequency and the phase of an internal oscillation signal of the loop can be controlled by using an externally input reference signal, and the automatic tracking of the frequency of an output signal to the frequency of an input signal is realized.

The serial circuit 514 is used to convert parallel data into serial data.

Deserializer circuit 515 is used to convert serial data to parallel data.

The Analog IP circuit 512 at least includes a reference source, a low dropout regulator, an Analog-to-digital converter, and an oscillator.

The low dropout regulator is an integrated circuit regulator, and is the biggest difference from a three-terminal regulator in that the low dropout regulator has low self-consumption. The low-dropout linear regulator can be used for controlling a current main channel, integrates a mos tube with an extremely low on-line on-resistance, a Schottky diode, a sampling resistor, a divider resistor and other hardware circuits, and has the functions of overcurrent protection, over-temperature protection, a precision reference source, a differential amplifier, a delayer and the like.

An oscillator is an energy conversion device that can convert dc electrical energy into an ac electrical energy circuit having a certain frequency. Oscillators can be largely divided into two categories: harmonic oscillators (harmonic oscillators) and relaxation oscillators (relaxation oscillators).

Digital-to-analog converters are devices that convert digital quantities into analog. The digital-to-analog converter is basically composed of 4 parts, namely a weight resistor network, an operational amplifier, a reference power supply and an analog switch. Analog-to-digital converters, i.e., a/D converters, referred to as ADCs for short, are generally used to convert continuous analog signals into discrete digital signals.

Based on this, the manufacturing process of the first FPGA wafer 40 can be a 12 nm, 22 nm or 28 nm process; the second FPGA wafer 50 may be fabricated by a40 nm or 65 nm process. By adopting different nanometer process procedures for different functional circuits, the manufacturing cost can be saved.

In other embodiments, the nano-scale process of the first FPGA wafer 40 may also be a 5 nm or 7 nm process.

The modules are connected through reasonable wiring resources to complete configuration.

In this embodiment, the stacked FPGA400 is divided into the first FPGA wafer 40 and the second FPGA wafer 50 according to different functional regions, and the first FPGA wafer 40 and the second FPGA wafer 50 have different nano-levels in the manufacturing process, compared with the conventional technology in which all functional circuits of the FPGA are integrated in the same FPGA wafer, the stacked FPGA400 is integrated by the first FPGA wafer 40 and the second FPGA wafer 50 by using the same nano-level manufacturing process, and each FPGA wafer has a smaller area, so that the yield of the product for manufacturing the FPGA can be improved, the requirement for the maximum exposure area of the FPGA can be reduced, and the cost of a single FPGA wafer can be reduced. Because of the first FPGA wafer 40 integrates the logic function circuit, compared with the conventional technology in which all function circuits of the FPGA are integrated on the same FPGA wafer, the analog function circuit also occupies the silicon chip position on the FPGA wafer, the logic function circuit can be set on the silicon chip position on the first FPGA wafer 40, and on the silicon chip with the same area, a larger scale and a more functional logic function circuit can be realized, the performance of the stacked FPGA400 can be improved, and at least part of the areas of the first FPGA wafer 40 and the second FPGA wafer 50 are stacked and connected, so that the global wiring in the stacked FPGA400 is shortened, the access speed between the function circuits of the stacked FPGA400 can be improved, the power consumption is reduced, and the overall performance is improved.

Referring to fig. 17, fig. 17 is a schematic structural diagram of another embodiment of a stacked FPGA provided in the present application, where the stacked FPGA400 includes a first FPGA wafer 40 and a second FPGA wafer 50. First circuitry is integrated into first FPGA wafer 40. Second circuitry is integrated into the second FPGA wafer 50.

The stacked FPGA400 is similar to the stacked FPGA400 of any of the embodiments described above, except that the first communication interface 42 is disposed on the first FPGA wafer 40; a second communication interface 52 is arranged on the second FPGA wafer 50; the first FPGA wafer 40 and the second FPGA wafer 50 are stacked at least partially and connected via the first communication interface 42 and the second communication interface 52.

Compared with the prior art in which all functional circuits are integrated on the same FPGA wafer, the first FPGA wafer 40 and the second FPGA wafer 50 are partially stacked, so that the connection between the first communication interface 42 and the second communication interface 52 is shortened, the access speed between the functional circuits can be increased, the power consumption can be reduced, and the overall performance can be improved.

Referring to fig. 18, fig. 18 is a schematic structural diagram of another embodiment of the stacked FPGA provided in the present application. Stacked FPGA400 includes a plurality of first FPGA wafers 40 and a plurality of second FPGA wafers 50. At least partial areas of each first FPGA wafer 40 and at least two second FPGA wafers 50 are stacked and connected.

It can be understood that the stacking relationship of the first FPGA wafer 40 and the second FPGA wafer 50 can be set reasonably according to the size of the FPGA wafer.

By the method, the connection between the FPGA wafer and the FPGA wafer is shortened, the access speed between functional circuits can be increased, the power consumption is reduced, and the overall performance is improved.

Referring to fig. 19, fig. 19 is a schematic structural diagram of another embodiment of the stacked FPGA provided in the present application. Stacked FPGA400 includes a plurality of first FPGA wafers 40 and a plurality of second FPGA wafers 50. Each second FPGA wafer 50 and at least a portion of the area of at least two first FPGA wafers 40 are stacked and connected.

In other embodiments, each second FPGA wafer 50 and each first FPGA wafer 40 are disposed on the same plane and electrically connected through a common substrate or silicon interposer.

In other embodiments, the first FPGA wafer 40 and the second FPGA wafer 50 are stacked and spaced apart and connected to each other.

In other embodiments, as shown in fig. 20, at least two first FPGA wafers 40 are stacked, at least two second FPGA wafers 50 are stacked, and at least two first FPGA wafers 40 in the stacked arrangement are stacked with at least two second FPGA wafers 50 in the stacked arrangement. By the method, the connection between the FPGA wafer and the FPGA wafer is shortened, the access speed between functional circuits can be increased, the power consumption is reduced, and the overall performance is improved.

In some embodiments, the second FPGA wafer 50 further includes a self-power circuit, and the first circuit and the second circuit are connected to the self-power circuit to power the first circuit and the second circuit through the self-power circuit. The self-powered circuit may include a power supply, which may be a rechargeable power supply that charges when connected to an external power source to ensure sufficient power.

In some embodiments, referring to fig. 21, the stacked FPGA400 includes a first FPGA wafer 40, a second FPGA wafer 50, and pads 30. The bonding pad 30 is disposed on a side of the first FPGA wafer 40 away from the second FPGA wafer 50, and the bonding pad 30 is used for connecting an external device, which may be a memory device or a power device. The pads 30 are electrically connected to first circuitry on the first FPGA wafer 40 for communicating the first FPGA wafer 40, the second FPGA wafer 50 with external devices.

Referring to fig. 22, fig. 22 is a schematic structural diagram of another embodiment of the electronic device provided in the present application. The electronic device 500 includes a stacked FPGA400 as in any of the embodiments described above.

The stacked FPGA400 is a stacked FPGA fabricated using the method of any of the embodiments described above.

The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.

Claims

1. A stacked device, comprising:

a first wafer comprising a first circuit;

a second wafer comprising a second circuit;

the first circuit comprises at least one of a processor, a timer, a bus, an encryption/decryption circuit, a memory access controller and an analog controller; or, the first circuit comprises at least one of a configurable logic circuit, a dedicated SRAM memory, a user-configurable logic circuit, an encoder, a decoder, and Digital IP;

the first wafer and the second wafer are stacked and connected to form the stacked device.

2. The stacked device of claim 1,

the first wafer and the second wafer are connected in a stacking and bonding mode in a three-dimensional heterogeneous integration mode.

3. The stacked device of claim 1,

the first wafer and the second wafer are stacked in a 2.5D manner.

4. The stacked device of claim 1, wherein the first wafer and the second wafer are at least two;

the first wafer and the second wafer are stacked at intervals and are connected with each other; alternatively, the first and second electrodes may be,

at least two first wafers are stacked, at least two second wafers are stacked, and at least two first wafers and at least two second wafers are stacked.

5. The stacked device as recited in claim 1 wherein the second wafer further comprises a self-powered circuit, the first circuit and the second circuit being connected to the self-powered circuit to power the first circuit and the second circuit through the self-powered circuit.

6. The stacked device of claim 1, wherein a side of the first wafer remote from the second wafer further comprises pads for connecting external devices including but not limited to memory devices, power devices.

7. The stacked device of claim 1,

the stacked device is a stacked MCU or a stacked FPGA.

8. The stacked device of claim 7,

when the stacked device is the stacked MCU, the second circuit includes at least one of an analog-to-digital conversion circuit, a phase-locked loop, a generator, a sensor, a clock circuit, a driving circuit, a general input/output port, a memory, a fuse, and an inductor.

9. The stacked device of claim 8,

the driving circuit includes an LCD driving unit and/or an LED driving unit.

10. The stacked device of claim 7,

when the stacked device is the stacked FPGA, the second circuit includes at least one of a configurable input output circuit, an Analog IP circuit, a phase locked loop, a serial circuit, a deserializing circuit, a general purpose input/output port, a memory, a fuse, and an inductor.