CN216287428U

CN216287428U - Automatic biplane information of dispatch checks device

Info

Publication number: CN216287428U
Application number: CN202122898170.4U
Authority: CN
Inventors: 张玉娟; 陈文刚; 宰洪涛; 张轲; 毛俊杰; 杨世宁; 朱剑飞; 王新瑞; 刘贺龙; 陈磊; 姚泽龙; 姬玉泽
Original assignee: Jincheng Power Supply Co of State Grid Shanxi Electric Power Co Ltd
Current assignee: Jincheng Power Supply Co of State Grid Shanxi Electric Power Co Ltd
Priority date: 2021-11-24
Filing date: 2021-11-24
Publication date: 2022-04-12
Anticipated expiration: 2031-11-24

Abstract

The utility model discloses a dispatching automation biplane information checking device which comprises a shell, wherein a liquid crystal display screen and a key are arranged on the shell, a first network port, a second network port, a power switch and a power jack are arranged at the top of the shell, and a first acquisition circuit, a second acquisition circuit, a main control circuit, a display circuit, a key circuit and a power circuit are arranged in the shell; the device receives data of two planes simultaneously, the main control circuit compares the contents, uploading time and a preset threshold value of two messages with the same point number to obtain a comparison result of the two messages, a checking person only needs to check one of the messages on a display screen of the automatic main station, and then the device checks the comparison result of the two messages to finish quick checking of two plane information.

Description

Automatic biplane information of dispatch checks device

Technical Field

The utility model belongs to the technical field of power grid dispatching, and particularly relates to a dispatching automation biplane information checking device.

Background

In recent years, with the rapid development of power grid dispatching automation, the transformer substation is in transition from being attended to being unattended, and a dispatcher can completely perform remote monitoring and basic switching operation on the transformer substation through four-remote information core of the transformer substation. Each piece of remote signaling information and remote measuring data of the transformer substation can influence the judgment of a dispatcher, so that the safe operation of the whole power grid can be influenced. Therefore, each transformer substation is subjected to strict four-remote information checking and acceptance by automatic workers from new construction, reconstruction, overhaul to operation. How to ensure the accuracy and timeliness of the four-remote information becomes the primary task of the power grid dispatching automation chemical author.

In the process of checking information in the past, the following problems are mainly included: 1. the amount of information to be checked is huge, and the station end transmits information to the dispatching data network through two planes through two remote motivations. The number of information points to be checked for each plane is thousands, and two planes need to be checked in sequence, which doubles the workload. 2. The states of the two planes cannot be verified simultaneously, and when one signal can be uploaded on one plane and the other plane fails to upload, the normal plane data checked before may be affected after the debugging personnel modify the failed plane. The check personnel can not find the defect and only carry out defect elimination work after putting into operation. 3. The information check is generally completed by a monitor, and the monitor does not need to perform the check work and also needs to complete the daily monitoring task. In the traditional checking method, slight difference may exist in signals uploaded by two planes, and a monitor is difficult to find, so that high requirements are made on checking quality.

SUMMERY OF THE UTILITY MODEL

The utility model overcomes the defects of the prior art, and solves the technical problems that: provided is a scheduling automation biplane information collating device which facilitates collation of four-remote information.

In order to solve the technical problems, the utility model adopts the technical scheme that: an automatic double-plane information checking device for dispatching comprises a shell, wherein a liquid crystal display screen and a key are arranged on the shell, the top of the shell is provided with a first net port, a second net port, a power switch and a power jack, the shell is internally provided with a first acquisition circuit, a second acquisition circuit, a main control circuit, a display circuit, a key circuit and a power circuit, the key, the first network port and the second network port are respectively connected with the input end of the key circuit, the input end of the first acquisition circuit and the input end of the second acquisition circuit, the output end of the key circuit, the output end of the first acquisition circuit and the output end of the second acquisition circuit are respectively connected with the input end of the main control circuit, the output end of the main control circuit is connected with the liquid crystal display screen through the display circuit, the power jack is connected with the power circuit through the power switch, and the power circuit provides power for the main control circuit.

Preferably, the main control circuit includes a main control chip U1, the first acquisition circuit includes a first network chip U3 and a patch socket J1 of the first network port, the PMODE0 end of the first network chip U3 is connected in series with a resistor R51 and then connected to the 3.3V power supply end, a connection line between the PMODE0 end of the first network chip U3 and the resistor R51 is connected in series with a resistor R52 and then grounded, the PMODE1 end of the first network chip U3 is connected in series with a resistor R53 and then connected to the 3.3V power supply end, a connection line between the PMODE1 end of the first network chip U3 and the resistor R51 is connected in series with a resistor R54 and then grounded, the PMODE2 end of the first network chip U3 is connected in series with a resistor R9 and then connected to the 3.3V power supply end, and a connection line between the PMODE2 end of the first network chip U3 and the resistor R55 is connected to the ground after being connected to the resistor R56; the TXN terminal of the first network chip U3 is connected to the TD-terminal of the patch socket J1, the TXP terminal of the first network chip U3 is connected to the TD + terminal of the patch socket J1, the RXN terminal of the first network chip U3 is connected to the RD-terminal of the patch socket J1, the RXP terminal of the first network chip U3 is connected to the RD + terminal of the patch socket J1, the ACTLED terminal of the first network chip U3 is connected to the tenth terminal of the patch socket J1, the linkl terminal of the first network chip U3 is connected to the eleventh terminal of the patch socket J1, the scll terminal of the first network chip U3 XI is connected to one terminal of the resistor R9, one terminal of the crystal oscillator X4, one terminal of the capacitor C57, the other terminal of the capacitor C57 is connected to the other terminal of the crystal oscillator X4 after being connected to the capacitor C56, the connection line 6867 to the other terminal of the crystal oscillator X4 is connected to the main control terminal of the resistor R59, the first network chip PA chip 59, the PA chip 59, the MISO terminal of the first network chip U3 is connected to the PA6 terminal of the main control chip U1, and the MOSI terminal of the first network chip U3 is connected to the PA7 terminal of the main control chip U1.

Preferably, the second acquisition circuit comprises a second network chip U4 and a patch socket J2 of the second network port, the PMODE0 end of the second network chip U4 is connected in series with a resistor R32 and then connected with a 3.3V power supply end, the connecting line between the PMODE0 end of the second network chip U4 and the resistor R32 is connected in series with the resistor R33 and then grounded, the PMODE1 end of the second network chip U4 is connected in series with a resistor R34 and then connected with a 3.3V power supply end, the connecting line between the PMODE1 end of the second network chip U4 and the resistor R34 is connected in series with the resistor R35 and then grounded, the PMODE2 end of the second network chip U4 is connected in series with the resistor R36 and then connected with a 3.3V power supply end, and the connecting line between the PMODE2 end of the second network chip U4 and the resistor R36 is connected in series with the resistor R37 and then grounded; the TXN terminal of the second network chip U4 is connected to the TD-terminal of the patch socket J2, the TXP terminal of the second network chip U4 is connected to the TD + terminal of the patch socket J2, the RXN terminal of the second network chip U4 is connected to the RD-terminal of the patch socket J2, the RXP terminal of the second network chip U4 is connected to the RD + terminal of the patch socket J2, the ACTLED terminal of the second network chip U4 is connected to the tenth terminal of the patch socket J2, the linkl terminal of the second network chip U4 is connected to the eleventh terminal of the patch socket J2, the second network chip U4 XI terminal is connected to one terminal of the resistor R9, one terminal of the crystal oscillator X3, one terminal of the capacitor C36, the other terminal of the capacitor C36 is connected to the other terminal of the crystal oscillator X3 after being connected to the capacitor C35, the connection line 6867 to the crystal oscillator X3 is connected to the other terminal of the resistor R40, the master control terminal of the second network chip U40, the network chip 40, the MISO end of the second network chip U4 is connected to the PB14 end of the main control chip U1, and the MOSI end of the second network chip U4 is connected to the PB15 end of the main control chip U1.

Preferably, the display circuit includes a display chip U, the LCD _ CS, WR _ CLK, and RESET terminals of the display chip U are respectively connected to the PG, PD, and NRST terminals of the main control chip U, the D, and D terminals of the display chip U are respectively connected to the PD, PE, PD, and PD terminals of the main control chip U, the BL, MISO, T _ PEN, T _ CS, T _ CLK, and T _ MOSI terminals of the display chip U are respectively connected to the PB, PF, PB, and PB terminals of the main control chip U, the D, and D terminals of the display chip U are respectively connected to the PD, PE, PD, and RS terminals of the main control chip U, the RD, and RS terminals of the display chip U are respectively connected to the RD, and RS terminals of the main control chip U, PG0 is connected at the end.

Preferably, the key circuit comprises a button K1, a button K2, a button K3, a button K4, a button K5 and a button K6, wherein one end of the button K1 is connected with a 5V power supply terminal, the other end of the button K1 is connected with a resistor R1, a photocoupler MI and a resistor R1 in series in sequence and then connected with a 3.3V power supply terminal, a connection line between the photocoupler MI and the resistor R1 is connected with a PF1 terminal of the main control chip U1, one end of the button K1 is connected with the 5V power supply terminal, the other end of the button K1 is connected with the resistor R1, the photocoupler M1 and the resistor R1 in sequence and then connected with the 3.3V power supply terminal, a connection line between the photocoupler M1 and the resistor R1 is connected with the PF1 terminal of the main control chip U1, one end of the button K1 is connected with the 5V power supply terminal, the other end of the button K1 is connected with the resistor R1 in sequence and then connected with the PF1 of the main control chip 1, one end of a button K4 is connected with a 5V power supply end, the other end of the button K4 is connected with a 3.3V power supply end after being sequentially connected with a resistor R67, a photoelectric coupler M4 and a resistor R68 in series, a connecting line between the photoelectric coupler M4 and the resistor R68 is connected with a PF3 end of a main control chip U1, one end of a button K5 is connected with the 5V power supply end, the other end of the button K5 is connected with a resistor R69, a photoelectric coupler M5 and a resistor R70 in series and then connected with the 3.3V power supply end, a connecting line between the photoelectric coupler M5 and the resistor R70 is connected with a PF4 end of a main control chip U1, one end of the button K6 is connected with the 5V power supply end, the other end of the button K6 is connected with a resistor R6, a photoelectric coupler M6 and a resistor R6 in series and then connected with the 3.3V power supply end of the main control chip U6.

Preferably, the power circuit comprises a power chip U5 and a voltage stabilizing chip U6, an anode output end of the 12V power adapter is connected in series with a switch K7 and a fuse F1 in sequence and then connected with an anode of a diode D31, a cathode of a diode D31 is connected with a cathode of a voltage stabilizing diode D32, one end of a resistor R73, one end of a capacitor C61, one end of a capacitor C62 and a VIN end of the power chip U5, the other end of a resistor R73 is connected with an anode of a light emitting diode D33, a cathode of the light emitting diode D33 is connected with an anode of the voltage stabilizing diode D32 and a cathode output end of the 12V power adapter, the other end of the capacitor C61 is connected with the other end of a capacitor C62, an ON/OFF end of the power chip U5, a GND end of the power chip U5, an anode of a voltage stabilizing diode D34, one end of a capacitor C63, one end of a capacitor C64, an anode of a voltage stabilizing diode D35, a cathode of the light emitting diode D36, One end of a capacitor C65, one end of a capacitor C66, a GND end of a voltage stabilizing chip U6, one end of a capacitor C67, one end of a capacitor C68, an anode of a voltage stabilizing diode D37 and a cathode of a light emitting diode D38 are connected, an anode of the light emitting diode D38 is connected with a resistor R75 In series and then is connected with a 3.3V power supply end, a connecting line between a resistor R75 and the 3.3V power supply end is respectively connected with an anode of a voltage stabilizing diode D37 and one end of a fuse F3, the other end of the fuse F3 is respectively connected with the other end of a capacitor C68, the other end of a capacitor C67, a TAB end of a voltage stabilizing chip U6 and an OUT end of a voltage stabilizing chip U6, an In end of the voltage stabilizing chip U6 is respectively connected with the other end of a capacitor C66, one end of a resistor R66, one end of a 5V power supply end of a voltage stabilizing diode D66, the cathode of a fuse F66 and the other end of a light emitting diode D66 are respectively connected with one end of a fuse F66, The other end of the capacitor C63, one end of the inductor L1 and the OUTPUT end of the power supply chip U5 are connected, and the other end of the inductor L1 is connected with the negative electrode of the voltage stabilizing diode D34.

Preferably, the model of the main control chip U1 is STM32F407ZET 6; the model of the first network chip U3 is W5500; the patch socket J1 is HR911105A _ C12074.

Preferably, the model of the second network chip U4 is W5500; the patch socket J2 is HR911105A _ C12074.

Preferably, the models of the photoelectric coupler MI, the photoelectric coupler M2, the photoelectric coupler M3, the photoelectric coupler M4, the photoelectric coupler M5 and the photoelectric coupler M6 are all PC817X1NSZ 9F.

Preferably, the model of the power supply chip U5 is LM 2596-5; the model of the voltage stabilizing chip U6 is AMS 1117-3.3.

Compared with the prior art, the utility model has the following beneficial effects:

the utility model relates to a dispatching automation biplane information checking device, which comprises a shell, wherein a liquid crystal display screen and a key are arranged on the shell, the top of the shell is provided with a first net port, a second net port, a power switch and a power jack, the shell is internally provided with a first acquisition circuit, a second acquisition circuit, a main control circuit, a display circuit, a key circuit and a power circuit, the device simultaneously receives data of two planes, the main control circuit compares the contents, uploading time and a preset threshold value of two messages with the same point number to obtain a comparison result of the two messages, a checker only needs to check one of the messages on a display screen of an automatic main station and then checks the comparison result of the two messages through the device, the device can complete the quick checking of the two plane information, greatly reduce the workload and the accuracy of checking the monitoring information and improve the working efficiency of monitoring personnel and field debugging personnel; the device is independent of a dispatching automation master station system, collects, analyzes and compares data uploaded by a front-end processor, and does not influence the operation of the master station system.

Drawings

The present invention will be described in further detail with reference to the accompanying drawings.

FIG. 1 is a front view of the present invention;

FIG. 2 is a top view of the present invention;

FIG. 3 is a circuit diagram of the present invention;

fig. 4 and 5 are circuit schematic diagrams of the main control circuit;

FIG. 6 is a circuit schematic of a first acquisition circuit;

FIG. 7 is a circuit schematic of a second acquisition circuit;

FIG. 8 is a circuit schematic of a display circuit;

FIG. 9 is a circuit schematic of the keying circuit;

FIG. 10 is a circuit schematic of a power circuit;

in the figure: the device comprises a shell 1, a first acquisition circuit 11, a second acquisition circuit 12, a main control circuit 13, a display circuit 14, a key circuit 15, a power circuit 16, a liquid crystal display screen 2, a key 3, a first network interface 4, a second network interface 5, a power switch 6 and a power jack 7.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments, but not all embodiments, of the present invention; all other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a front view, fig. 2 is a top view, fig. 3 is a circuit connection diagram of the present invention, and as shown in fig. 1 to fig. 3, the dispatching automation biplane information checking device includes a housing 1, a liquid crystal display 2 and a key 3 are arranged on the front side of the housing 1, a first network port 4, a second network port 5, a power switch 6 and a power jack 7 are arranged on the top of the housing 1, a circuit board is arranged in the housing 1, a first acquisition circuit 11, a second acquisition circuit 12, a main control circuit 13, a display circuit 14, a key circuit 15 and a power circuit 16 are arranged on the circuit board, the key 3, the first network port 4 and the second network port 5 are respectively connected with an input end of the key circuit 15, an input end of the first acquisition circuit 11 and an input end of the second acquisition circuit 12, an output end of the key circuit 15 and an output end of the first acquisition circuit 11, The output end of the second acquisition circuit 12 is respectively connected with the input end of the main control circuit 13, the output end of the main control circuit 13 is connected with the liquid crystal display screen 2 through the display circuit 14, the power jack 7 is connected with the power circuit 16 through the power switch 6, and the power circuit 16 provides power for the main control circuit 13.

Before the device is used, a first network port 4 and a second network port 5 of the device are respectively and electrically connected with a first plane front-end processor and a second plane front-end processor of a power dispatching data network through network cables, then a power switch is turned on, and the device is waited to be self-checked and started; after the device is started, the setting work of relevant configuration parameters can be carried out through the keys 3, such as message channels of the biplane front-end processor, such as IP addresses, port numbers and the like, message analysis protocol types, such as IEC104 protocols, IEC101 protocols and the like, delay error seconds, deviation threshold% and the like; after the key 3 configures parameters, the station end uploads messages through two front-end computers on two planes through two remote motors, a first acquisition circuit 11 and a second acquisition circuit 12 respectively acquire the messages uploaded by the front-end computers on the two planes through a first network port 4 and a second network port 5, a main control circuit 13 compares the uploading time and a preset threshold value of the two acquired message data to obtain a comparison result of the two messages, and the comparison result is sent to a liquid crystal display screen 2 through a display circuit 14 to be displayed; the collator only needs to collate one of the messages on the display screen of the automatic master station and then checks the comparison result of the two messages through the device, and therefore the quick collation of the two pieces of plane information can be completed. For example, the message data of the '1 # main transformer tap position 1' returned by a plane front-end processor is checked on the display screen of the automatic main station, and if the message data of the '1 # main transformer tap position 1' returned by the plane front-end processor is 'off', the state of the 1# main transformer tap position 1 on the power grid state diagram is also 'off', the message data returned by the front-end processor on the first plane is consistent with the state on the power grid state diagram, at the moment, the device checks the comparison result of the message data returned by the main transformer tap position 1 on the 1# through the first plane and the second plane, when the message data returned by the front-end processor on the second plane is disconnected, the message data returned by the two-plane front-end processor is consistent with the message data returned by the one-plane front-end processor, the consistency is displayed on the liquid crystal display screen 2 of the device, and the fact that the message data uploaded on the two planes are consistent with the state on the power grid state diagram is indirectly proved; if the inconsistency is displayed, the message data uploaded on the two planes at the moment can be considered to be inconsistent with the state on the power grid state diagram, and the checking personnel can contact with the field personnel in time to judge the inconsistency reason.

Furthermore, a delay error can be set for a remote signaling signal or a remote measuring signal, when one signal is uploaded through two planes and reaches a front-end processor, a time error exists, for example, the delay error is 10s, namely within 10s after one message is successfully uploaded, if the message of the other plane can also be uploaded, the signal can be considered to be uploaded through the two planes; when the interval between the two messages exceeds 10s, determining that the two messages cannot be uploaded or a channel fails, and displaying that the two messages are inconsistent in a comparison result of the device; a preset threshold value can be set for the telemetering signals, when one telemetering signal is acquired and uploaded by two remote motors and reaches a front-end processor, numerical deviation may exist, when the numerical deviation of two messages is smaller than the preset threshold value, the device can automatically determine that the two messages are consistent, otherwise, the device can automatically determine that the two messages are inconsistent; the device can realize the real-time automatic comparison function, and can also realize the data consistency comparison and result display of the point number of the designated point number or the designated range through the manual comparison function.

The device receives data of two planes simultaneously, the main control circuit 13 compares the contents, uploading time and a preset threshold value of two messages with the same point number to obtain a comparison result of the two messages, a checking person only needs to check one of the messages on a display screen of the automatic main station, and then the device checks the comparison result of the two messages to finish the quick checking of the two plane information, so that the device greatly reduces the workload and the accuracy of checking the monitoring information and improves the working efficiency of the monitoring person and the field debugging person; the device can accurately judge the non-corresponding relation of the remote measuring state and the remote signaling state in time, is beneficial to the positioning of fault points, timely informs maintenance personnel to process, shortens the fault processing time, is independent of a dispatching automation master station system, collects, analyzes and compares data uploaded by a front-end processor, and cannot influence the operation of the master station system.

Fig. 4 and 5 are schematic circuit diagrams of the main control circuit 13, and fig. 6 is a schematic circuit diagram of the first acquisition circuit 11, and as shown in fig. 4 to 6, the main control circuit 13 includes a main control chip U1, the first acquisition circuit 11 includes a first network chip U3 and a patch socket J1 of a first network port, and the main control chip U1 is model number STM32F407ZET 6; the model of the first network chip U3 is W5500; the model of the patch socket J1 is HR911105A _ C12074;

the PMODE0 end of the first network chip U3 is connected with a resistor R51 in series and then connected with a 3.3V power supply end, a connecting line between the PMODE0 end of the first network chip U3 and the resistor R51 is connected with a resistor R52 in series and then grounded, the PMODE1 end of the first network chip U3 is connected with a resistor R53 in series and then connected with a 3.3V power supply end, a connecting line between the PMODE1 end of the first network chip U3 and the resistor R51 is connected with a resistor R54 in series and then grounded, the PMODE2 end of the first network chip U3 is connected with a resistor R55 in series and then connected with a 3.3V power supply end, and a connecting line between the PMODE2 end of the first network chip U3 and the resistor R55 is connected with a resistor R56 in series and then grounded; the TXN terminal of the first network chip U3 is connected to the TD-terminal of the patch socket J1, the TXP terminal of the first network chip U3 is connected to the TD + terminal of the patch socket J1, the RXN terminal of the first network chip U3 is connected to the RD-terminal of the patch socket J1, the RXP terminal of the first network chip U3 is connected to the RD + terminal of the patch socket J1, the ACTLED terminal of the first network chip U3 is connected to the tenth terminal of the patch socket J1, the linkl terminal of the first network chip U3 is connected to the eleventh terminal of the patch socket J1, the scll terminal of the first network chip U3 XI is connected to one terminal of the resistor R9, one terminal of the crystal oscillator X4, one terminal of the capacitor C57, the other terminal of the capacitor C57 is connected to the other terminal of the crystal oscillator X4 after being connected to the capacitor C56, the connection line 6867 to the other terminal of the crystal oscillator X4 is connected to the main control terminal of the resistor R59, the first network chip PA chip 59, the PA chip 59, the MISO terminal of the first network chip U3 is connected to the PA6 terminal of the main control chip U1, and the MOSI terminal of the first network chip U3 is connected to the PA7 terminal of the main control chip U1.

Fig. 7 is a schematic circuit diagram of a second acquisition circuit 12, the second acquisition circuit 12 including a second network chip U4 and a second network port patch jack J2, the second network chip U4 having a model number W5500; the model of the patch socket J2 is HR911105A _ C12074;

the PMODE0 end of the second network chip U4 is connected with a resistor R32 in series and then connected with a 3.3V power supply end, a connecting line between the PMODE0 end of the second network chip U4 and the resistor R32 is connected with a resistor R33 in series and then grounded, the PMODE1 end of the second network chip U4 is connected with a resistor R34 in series and then connected with a 3.3V power supply end, a connecting line between the PMODE1 end of the second network chip U4 and the resistor R34 is connected with a resistor R35 in series and then grounded, the PMODE2 end of the second network chip U4 is connected with a resistor R36 in series and then connected with a 3.3V power supply end, and a connecting line between the PMODE2 end of the second network chip U4 and the resistor R36 is connected with a resistor R37 in series and then grounded; the TXN terminal of the second network chip U4 is connected to the TD-terminal of the patch socket J2, the TXP terminal of the second network chip U4 is connected to the TD + terminal of the patch socket J2, the RXN terminal of the second network chip U4 is connected to the RD-terminal of the patch socket J2, the RXP terminal of the second network chip U4 is connected to the RD + terminal of the patch socket J2, the ACTLED terminal of the second network chip U4 is connected to the tenth terminal of the patch socket J2, the linkl terminal of the second network chip U4 is connected to the eleventh terminal of the patch socket J2, the second network chip U4 XI terminal is connected to one terminal of the resistor R9, one terminal of the crystal oscillator X3, one terminal of the capacitor C36, the other terminal of the capacitor C36 is connected to the other terminal of the crystal oscillator X3 after being connected to the capacitor C35, the connection line 6867 to the crystal oscillator X3 is connected to the other terminal of the resistor R40, the master control terminal of the second network chip U40, the network chip 40, the MISO end of the second network chip U4 is connected to the PB14 end of the main control chip U1, and the MOSI end of the second network chip U4 is connected to the PB15 end of the main control chip U1.

FIG. 8 is a schematic circuit diagram of a display circuit 14, the display circuit 14 includes a display chip U2, an LCD _ CS terminal, a WR _ CLK terminal, and a RESET terminal of the display chip U2 are respectively connected to a PG 2 terminal, a PD 2 terminal, and an NRST terminal of a main control chip U2, a D2 terminal, and a D2 terminal of the display chip U2 are respectively connected to a PD 2 terminal, a PE 2 terminal, a PD 2 terminal, and a PD 2 terminal of the main control chip U2, a BL terminal, an MISO terminal, a T _ PEN terminal, a T _ CLK terminal, a T _ MOSI terminal of the display chip U2 are respectively connected to a PB terminal, a PD 2 terminal PB terminal, a PD 2 terminal, a PD end 2 terminal of the main control chip U2, a D2 terminal, a D end 2 terminal, a display chip D terminal 2 terminal, a PD end 2 terminal, a PD end 2 terminal, a PD end of the PD end 2 terminal of the main control chip D terminal of the main control chip U2 terminal, a PD end 2 terminal, a PD terminal of the main control chip U2 terminal, a PD terminal 2 terminal of the main control chip U2 terminal, a PD terminal 2 terminal, a PD terminal 2 terminal of the PD terminal of the main control chip U2 terminal, a PD terminal of the main control chip U2, a PD terminal of the main control chip U2 terminal, a PD terminal of the main control chip U2, the RD terminal and the RS terminal of the display chip U2 are respectively connected with the PD4 terminal and the PG0 terminal of the main control chip U1.

Fig. 9 is a schematic circuit diagram of a key circuit 15, where the key circuit 15 includes a button K1, a button K2, a button K3, a button K4, a button K5, and a button K6, one end of the button K1 is connected to a 5V power supply terminal, the other end of the button K1 is connected to a 3.3V power supply terminal after being connected to a resistor R1, a connection line between the photocoupler MI and the resistor R1 is connected to a PF1 terminal of a main control chip U1, one end of the button K1 is connected to the 5V power supply terminal, the other end of the button K1 is connected to a resistor R1, a photocoupler M1, and a resistor R1 in turn and then connected to a 3.3V power supply terminal, a connection line between the photocoupler M1 and the resistor R1 is connected to a PF1 terminal of the main control chip U1, one end of the button K1 is connected to the 5V power supply terminal, the other end of the button K1 is connected to the resistor M1, the photoelectric coupler M1, the other end of the button K1 is connected to the resistor M1, the PF1 is connected to the main control chip 1 after being connected to the resistor R1, one end of a button K4 is connected with a 5V power supply end, the other end of the button K4 is connected with a 3.3V power supply end after being sequentially connected with a resistor R67, a photoelectric coupler M4 and a resistor R68 in series, a connecting line between a photoelectric coupler M4 and a resistor R68 is connected with a PF3 end of a main control chip U1, one end of a button K5 is connected with the 5V power supply end, the other end of the button K5 is connected with a resistor R69, a photoelectric coupler M5 and a resistor R70 in series and then connected with the 3.3V power supply end, a connecting line between a photoelectric coupler M5 and a resistor R70 is connected with a PF4 end of a main control chip U1, one end of the button K6 is connected with the 5V power supply end, the other end of the button K6 is connected with a resistor R6, a photoelectric coupler M6 and a resistor R6 in series and then connected with the 3.3V power supply end, and a connecting line between the photoelectric coupler M6 and the resistor R6 is connected with a PF 6 end of the main control chip U6; the models of the photoelectric coupler MI, the photoelectric coupler M2, the photoelectric coupler M3, the photoelectric coupler M4, the photoelectric coupler M5 and the photoelectric coupler M6 are PC817X1NSZ 9F.

FIG. 10 is a schematic circuit diagram of the power circuit 16, wherein the power circuit 16 includes a power chip U5 and a voltage regulator chip U6, and the power chip U5 has a model number LM 2596-5; the model of the voltage stabilizing chip U6 is AMS 1117-3.3; the positive electrode output end of the 12V power adapter is connected with a switch K7 and a fuse F1 in series in sequence and then connected with the positive electrode of a diode D31, the negative electrode of a diode D31 is connected with the negative electrode of a voltage stabilizing diode D32, one end of a resistor R73, one end of a capacitor C61, one end of a capacitor C62 and the VIN end of a power chip U5, the other end of a resistor R73 is connected with the positive electrode of a light emitting diode D33, the negative electrode of a light emitting diode D33 is connected with the positive electrode of a voltage stabilizing diode D32 and the negative electrode output end of a 12V power adapter, the other end of a capacitor C61 is connected with the other end of a capacitor C62, the ON/OFF end of a power chip U5, the GND end of a power chip U5, the positive electrode of a voltage stabilizing diode D34, one end of a capacitor C63, one end of a capacitor C64, the positive electrode of a voltage stabilizing diode D35, the negative electrode of a light emitting diode D36, one end of a capacitor C36, a GND 36, One end of a capacitor C68, the anode of a voltage stabilizing diode D37 and the cathode of a light emitting diode D38 are connected, the anode of a light emitting diode D38 is connected with a 3.3V power supply end after being connected with a resistor R75 In series, a connecting line between a resistor R75 and the 3.3V power supply end is respectively connected with the cathode of a voltage stabilizing diode D37 and one end of a fuse F3, the other end of a fuse F3 is respectively connected with the other end of a capacitor C68, the other end of a capacitor C67, the TAB end of a voltage stabilizing chip U6 and the OUT end of a voltage stabilizing chip U6, the In end of a voltage stabilizing chip U6 is respectively connected with the other end of a capacitor C66, the other end of a capacitor C65, one end of a resistor R74, the 5V power supply end, the cathode of a voltage stabilizing diode D35 and one end of a fuse F2, the other end of a resistor R367 is connected with the anode of a light emitting diode D36, the other end of a fuse F2 is respectively connected with the other end of a capacitor C2, one end of a capacitor C2, the OUTPUT chip 2 and an OUTT chip 36874 end of an inductor L2, the other end of the inductor L1 is connected with the cathode of the voltage stabilizing diode D34, and the input end of the 12V power adapter is connected with the mains supply.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dispatch automation biplane information check device, includes casing (1), its characterized in that: the front surface of the shell (1) is provided with a liquid crystal display screen (2) and a key (3), the top of the shell (1) is provided with a first net port (4), a second net port (5), a power switch (6) and a power jack (7), the shell (1) is internally provided with a first acquisition circuit (11), a second acquisition circuit (12), a main control circuit (13), a display circuit (14), a key circuit (15) and a power circuit (16), the key (3), the first net port (4) and the second net port (5) are respectively connected with the input end of the key circuit (15), the input end of the first acquisition circuit (11) and the input end of the second acquisition circuit (12), the output end of the key circuit (15), the output end of the first acquisition circuit (11) and the output end of the second acquisition circuit (12) are respectively connected with the input end of the main control circuit (13), the output end of the main control circuit (13) is connected with the liquid crystal display screen (2) through the display circuit (14), the power jack (7) is connected with the power circuit (16) through the power switch (6), and the power circuit (16) provides power for the main control circuit (13).

2. The dispatch-automation biplane information collation apparatus according to claim 1, wherein: the main control circuit (13) comprises a main control chip U1, the first acquisition circuit (11) comprises a first network chip U3 and a patch socket J1 of a first network port, a PMODE0 end of the first network chip U3 is connected in series with a resistor R51 and then connected with a power supply end of 3.3V, a connecting line between a PMODE0 end of the first network chip U3 and a resistor R51 is connected in series with a resistor R52 and then grounded, a PMODE1 end of the first network chip U3 is connected in series with a resistor R53 and then connected with a power supply end of 3.3V, a connecting line between a PMODE1 end of the first network chip U3 and a resistor R51 is connected in series with a resistor R54 and then grounded, a PMODE2 end of the first network chip U3 is connected in series with a resistor R55 and then connected with a power supply end of 3.3V, and a connecting line between a PMODE2 end of the first network chip U3 and a connecting resistor R55 is connected in series with a connecting in series with a resistor R56 and then grounded; the TXN terminal of the first network chip U3 is connected to the TD-terminal of the patch socket J1, the TXP terminal of the first network chip U3 is connected to the TD + terminal of the patch socket J1, the RXN terminal of the first network chip U3 is connected to the RD-terminal of the patch socket J1, the RXP terminal of the first network chip U3 is connected to the RD + terminal of the patch socket J1, the ACTLED terminal of the first network chip U3 is connected to the tenth terminal of the patch socket J1, the linkl terminal of the first network chip U3 is connected to the eleventh terminal of the patch socket J1, the scll terminal of the first network chip U3 XI is connected to one terminal of the resistor R9, one terminal of the crystal oscillator X4, one terminal of the capacitor C57, the other terminal of the capacitor C57 is connected to the other terminal of the crystal oscillator X4 after being connected to the capacitor C56, the connection line 6867 to the other terminal of the crystal oscillator X4 is connected to the main control terminal of the resistor R59, the first network chip PA chip 59, the PA chip 59, the MISO terminal of the first network chip U3 is connected to the PA6 terminal of the main control chip U1, and the MOSI terminal of the first network chip U3 is connected to the PA7 terminal of the main control chip U1.

3. The dispatch-automation biplane information collation apparatus according to claim 2, wherein: the second acquisition circuit (12) comprises a second network chip U4 and a patch socket J2 of a second network port, a PMODE0 end of the second network chip U4 is connected with a resistor R32 in series and then is connected with a 3.3V power supply end, a connecting line between a PMODE0 end of the second network chip U4 and a resistor R32 is connected with a resistor R33 in series and then is grounded, a PMODE1 end of the second network chip U4 is connected with a resistor R34 in series and then is connected with a 3.3V power supply end, a connecting line between a PMODE1 end of the second network chip U4 and a resistor R34 is connected with a resistor R35 in series and then is grounded, a PMODE2 end of the second network chip U4 is connected with a resistor R36 in series and then is connected with a 3.3V power supply end, and a connecting line between a PMODE2 end of the second network chip U4 and a resistor R36 is connected with a resistor R37 in series and then is grounded; the TXN terminal of the second network chip U4 is connected to the TD-terminal of the patch socket J2, the TXP terminal of the second network chip U4 is connected to the TD + terminal of the patch socket J2, the RXN terminal of the second network chip U4 is connected to the RD-terminal of the patch socket J2, the RXP terminal of the second network chip U4 is connected to the RD + terminal of the patch socket J2, the ACTLED terminal of the second network chip U4 is connected to the tenth terminal of the patch socket J2, the linkl terminal of the second network chip U4 is connected to the eleventh terminal of the patch socket J2, the second network chip U4 XI terminal is connected to one terminal of the resistor R9, one terminal of the crystal oscillator X3, one terminal of the capacitor C36, the other terminal of the capacitor C36 is connected to the other terminal of the crystal oscillator X3 after being connected to the capacitor C35, the connection line 6867 to the crystal oscillator X3 is connected to the other terminal of the resistor R40, the master control terminal of the second network chip U40, the network chip 40, the MISO end of the second network chip U4 is connected to the PB14 end of the main control chip U1, and the MOSI end of the second network chip U4 is connected to the PB15 end of the main control chip U1.

4. The dispatch-automation biplane information collation apparatus according to claim 2, wherein: the display circuit (14) comprises a display chip U, wherein an LCD _ CS end, a WR _ CLK end and a RESET end of the display chip U are respectively connected with a PG end, a PD end and an NRST end of the main control chip U, a D end and a D end of the display chip U are respectively connected with a PD end, a PE end, a PD end and a PD end of the main control chip U, a BL end, a MISO end, a T _ PEN end, a T _ CS end, a T _ CLK end and a T _ MOSI end of the display chip U are respectively connected with a PB end, a PF end, a PB end and a PB end of the main control chip U, a D end and a D end of the display chip U are respectively connected with a PD end, a PE end, a PD end and a PD end of the main control chip U, a RD end of the display chip U and a RS end of the main control chip U are respectively connected with a PD end of the display chip U, PG0 is connected at the end.

5. The dispatch-automation biplane information collation apparatus according to claim 2, wherein: the key circuit (15) comprises a button K1, a button K2, a button K3, a button K4, a button K5 and a button K6, wherein one end of the button K1 is connected with a 5V power supply end, the other end of the button K1 is connected with a resistor R1, a photoelectric coupler MI and a resistor R1 in series in sequence and then connected with a 3.3V power supply end, a connecting line between the photoelectric coupler MI and the resistor R1 is connected with a PF1 end of the main control chip U1, one end of the button K1 is connected with the 5V power supply end, the other end of the button K1 is connected with the resistor R1, the photoelectric coupler M1 and the resistor R1 in series in sequence and then connected with the 3.3V power supply end, a connecting line between the photoelectric coupler M1 and the resistor R1 is connected with the PF1 end of the main control chip U1, one end of the button K1 is connected with the 5V power supply end, the other end of the button K1 is connected with the resistor R1 in sequence and the connecting line between the resistor R1 and the PF1 of the main control chip 1, one end of a button K4 is connected with a 5V power supply end, the other end of the button K4 is connected with a 3.3V power supply end after being sequentially connected with a resistor R67, a photoelectric coupler M4 and a resistor R68 in series, a connecting line between the photoelectric coupler M4 and the resistor R68 is connected with a PF3 end of a main control chip U1, one end of a button K5 is connected with the 5V power supply end, the other end of the button K5 is connected with a resistor R69, a photoelectric coupler M5 and a resistor R70 in series and then connected with the 3.3V power supply end, a connecting line between the photoelectric coupler M5 and the resistor R70 is connected with a PF4 end of a main control chip U1, one end of the button K6 is connected with the 5V power supply end, the other end of the button K6 is connected with a resistor R6, a photoelectric coupler M6 and a resistor R6 in series and then connected with the 3.3V power supply end of the main control chip U6.

6. The dispatch-automation biplane information collation apparatus according to claim 2, wherein: the power supply circuit (16) comprises a power supply chip U5 and a voltage stabilizing chip U6, the anode output end of the 12V power adapter is connected with a switch K7 and a fuse F1 in series in sequence and then connected with the anode of a diode D31, the cathode of a diode D31 is connected with the cathode of a voltage stabilizing diode D32, one end of a resistor R73, one end of a capacitor C61, one end of a capacitor C62 and the VIN end of the power chip U5, the other end of a resistor R73 is connected with the anode of a light emitting diode D33, the cathode of the light emitting diode D33 is connected with the anode of a voltage stabilizing diode D32 and the cathode output end of the 12V power adapter, the other end of a capacitor C61 is connected with the other end of a capacitor C62, the ON/OFF end of a power chip U5, the GND end of a power chip U5, the anode of a voltage stabilizing diode D34, one end of a capacitor C63, one end of a capacitor C64, the anode of a voltage stabilizing diode D35, the cathode of a light emitting diode D36, the cathode of a capacitor C634 and the cathode of a capacitor C65, One end of a capacitor C66, a GND end of a voltage stabilizing chip U6, one end of a capacitor C67, one end of a capacitor C68, an anode of a voltage stabilizing diode D37 and a cathode of a light emitting diode D38 are connected, an anode of the light emitting diode D38 is connected with a resistor R75 In series and then connected with a 3.3V power supply end, a connecting line between a resistor R75 and the 3.3V power supply end is respectively connected with a cathode of a voltage stabilizing diode D37 and one end of a fuse F3, the other end of the fuse F3 is respectively connected with the other end of a capacitor C68, the other end of a capacitor C9, a TAB end of a voltage stabilizing chip U686 6 and an OUT end of a voltage stabilizing chip U6, an In end of the voltage stabilizing chip U6 is respectively connected with the other end of a capacitor C66, the other end of a capacitor C65, one end of a resistor R74, a power supply end of a 5V power supply end, a cathode of a voltage stabilizing diode D35 and one end of a fuse F2, the other end of a resistor R2 is respectively connected with an anode of a light emitting diode D2, The other end of the capacitor C63, one end of the inductor L1 and the OUTPUT end of the power supply chip U5 are connected, and the other end of the inductor L1 is connected with the negative electrode of the voltage stabilizing diode D34.

7. The dispatch-automation biplane information collation apparatus according to claim 2, wherein: the model of the main control chip U1 is STM32F407ZET 6; the model of the first network chip U3 is W5500; the patch socket J1 is HR911105A _ C12074.

8. A dispatch automated biplane information verification apparatus as claimed in claim 3, wherein: the model of the second network chip U4 is W5500; the patch socket J2 is HR911105A _ C12074.

9. The dispatch automated biplane information verification apparatus of claim 5, wherein: the models of the photoelectric coupler MI, the photoelectric coupler M2, the photoelectric coupler M3, the photoelectric coupler M4, the photoelectric coupler M5 and the photoelectric coupler M6 are PC817X1NSZ 9F.

10. The dispatch automated biplane information verification apparatus of claim 6, wherein: the model of the power supply chip U5 is LM 2596-5; the model of the voltage stabilizing chip U6 is AMS 1117-3.3.