CN216216838U

CN216216838U - Phase-locked detection circuit

Info

Publication number: CN216216838U
Application number: CN202121510054.4U
Authority: CN
Inventors: 赵照
Original assignee: Hefei Xinfoo Sensor Technology Co ltd
Current assignee: Hefei Xinfoo Sensor Technology Co ltd
Priority date: 2021-07-05
Filing date: 2021-07-05
Publication date: 2022-04-05
Anticipated expiration: 2031-07-05

Abstract

The application discloses phase-locked detection circuit, including state detection circuit, be connected with phase frequency detector output in the phase-locked loop, state detection circuit is used for following first phase discrimination signal and second phase discrimination signal are received to the phase frequency detector, to first phase discrimination signal with the second phase discrimination signal carries out logical operation, according to the signal after logical operation and the first threshold value of preset, confirms and output decision signal; and the counting circuit is connected with the output end of the state detection circuit and is used for receiving the judgment signal from the state detection circuit, counting the judgment signal and outputting a phase-locked detection signal. The phase-locked detection circuit provided by the utility model has the advantages of short timing period, fewer elements contained in the circuit and simpler circuit structure.

Description

Phase-locked detection circuit

Technical Field

The application relates to the technical field of circuits, in particular to a phase-locked detection circuit.

Background

The phase-locked loop becomes one of the core components in modern electronic systems, and can be widely applied to the fields of communication, aviation, radar, automobile electronics and the like. A phase-locked loop typically includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. The main function of the phase locked loop is to output a stable and reliable clock feedback signal in a locked state, which maintains the same frequency and constant phase difference with the input reference signal. However, when the phase-locked loop is applied in the out-of-lock state, a system fault is easily caused, so that a phase-locked detection circuit needs to be added to the phase-locked loop circuit to detect the working state of the phase-locked loop, so as to detect the phase-locked loop in the out-of-lock state in time, and to perform maintenance to prevent the system fault.

The traditional phase-locked detection circuit respectively counts the reference signal input by the phase frequency detector and the feedback signal of the voltage-controlled oscillator simultaneously through the counter, if the reference signal and the feedback signal are equal in count within a certain count period, the frequency of the reference signal and the frequency of the feedback signal are consistent, the phase-locked loop completes locking, and in order to improve the detection precision, the locking can be judged to be completed only by more count periods, and longer time is consumed.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application provides a phase lock detection circuit, which detects a phase relationship of an input signal of a phase frequency detector, and determines that a phase lock loop has completed phase lock if a phase difference is continuously stabilized within a certain threshold.

In order to solve the technical problem, the following technical scheme is adopted in the application: the application provides a phase-locked detection circuit, phase-locked detection circuit includes: the phase frequency detector is used for receiving a first phase discrimination signal and a second phase discrimination signal from the phase frequency detector, performing logic operation on the first phase discrimination signal and the second phase discrimination signal, and determining and outputting a judgment signal according to the signal after the logic operation and a preset first threshold; and the counting circuit is connected with the output end of the state detection circuit and is used for receiving the judgment signal from the state detection circuit, counting the judgment signal and outputting a phase-locked detection signal.

Preferably, the state detection circuit includes: the first input end and the second input end of the AND gate are connected with the phase frequency detector and are respectively used for receiving the first phase detection signal and the second phase detection signal, and the AND gate performs AND logic operation on the first phase detection signal and the second phase detection signal and outputs a first logic signal; the first input end and the second input end of the or gate are connected with the phase frequency detector and are respectively used for receiving the first phase detection signal and the second phase detection signal, and the or gate performs or logical operation on the first phase detection signal and the second phase detection signal and outputs a second logical signal; the input end of the delay circuit is connected with the output end of the OR gate, and is used for delaying the second logic signal and outputting a third logic signal, and the delay time is a first threshold value; and a clock end of the sampling trigger is connected with the output end of the AND gate and is used for receiving the first logic signal, a data end of the sampling trigger is connected with the output end of the delay circuit and is used for receiving the third logic signal, an SET end of the sampling trigger is connected with a reset signal, and the sampling trigger outputs the judgment signal according to the first logic signal and the third logic signal.

Preferably, the counting circuit comprises N +1 flip-flops, where N is a positive integer greater than 1, the N +1 flip-flops comprising: the clock end of the first trigger is connected with the output end of the AND gate; the clock end of the Nth trigger is connected with the inverted output end of the (N-1) th trigger; a clock end of the (N + 1) th flip-flop is connected with a non-inverting output end of the (N) th flip-flop, a data end of the (N + 1) th flip-flop is connected with a high level, and the (N + 1) th flip-flop is used for outputting the phase-locked detection signal; the data ends of the first trigger to the Nth trigger are connected with the inverted output end of the trigger, and the first trigger to the Nth trigger are used for counting; and the reset ends of the N +1 triggers are connected with the positive phase output end of the sampling trigger and used for receiving the judgment signal.

Preferably, the flip-flop is a D flip-flop.

Compared with the prior art, the method has the following beneficial effects:

based on the above technical solution, the phase-locked detection circuit provided in the present application obtains a determination signal corresponding to a working state of a phase-locked loop by performing logic operation, delay and sampling on a phase demodulation signal at an output end of a phase frequency demodulator in the phase-locked loop, and if the determination signal satisfies a corresponding locking state within a certain time, it is determined that the phase-locked loop is in the locking state, otherwise, the phase-locked loop is in an out-of-lock state. Compared with the traditional phase-lock detection circuit, the phase-lock detection circuit provided by the utility model has the advantages of short timing period, fewer elements contained in the circuit and simpler circuit structure.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of a phase-locked loop structure according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of an input/output signal waveform of a phase frequency detector according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of a phase lock detection circuit according to an embodiment of the present disclosure.

Fig. 4 is a diagram of a phase lock detection logic circuit according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a signal waveform in a phase lock detection circuit according to an embodiment of the present disclosure.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

Fig. 1 is a schematic structural diagram of a phase-locked loop according to an embodiment of the present disclosure, where the phase-locked loop includes a crystal buffer, a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider. The crystal oscillator buffer is used for buffering an original signal generated by a crystal oscillator, generating a reference signal and outputting the reference signal to the phase frequency detector, the phase frequency detector is used for detecting the phase difference between the reference signal and a feedback signal, the phase-locked loop comprises a charge pump, a low-pass filter, a frequency divider and a phase-locked loop, wherein the charge pump is used for generating charging or discharging current according to the first phase discrimination signal and the second phase discrimination signal, the low-pass filter is used for outputting control voltage to a voltage-controlled oscillator according to the current generated by the charge pump, the voltage-controlled oscillator is used for generating oscillating voltage according to the control voltage, the frequency divider is used for generating a feedback signal according to the oscillating voltage in a frequency division mode to form a closed-loop feedback control system, the phase-locked loop can adjust the phase and the frequency of the feedback signal so that the feedback signal and a reference signal have the same frequency and a constant phase difference, and the phase-locked loop works in a locked state at the moment.

Fig. 2 is a schematic diagram of waveforms of input and output signals of a phase frequency detector provided in an embodiment of the present application, as shown in fig. 2, according to a working principle of the phase frequency detector, a first phase detection signal and a second phase detection signal have a falling edge at the same time, and a time difference between rising edges of the first phase detection signal and the second phase detection signal is a time difference between rising edges of an input reference signal and a feedback signal.

Fig. 3 is a schematic structural diagram of a phase-lock detection circuit provided in an embodiment of the present application, where the phase-lock detection circuit includes two parts, namely a state detection circuit and a timing circuit, where the state detection circuit is coupled to an output end of a phase frequency detector in a phase-lock loop, and the state detection circuit is configured to receive a first phase detection signal and a second phase detection signal from the phase frequency detector, perform a logic operation on the first phase detection signal and determine and output a determination signal according to the phase detection signal after the logic operation and a preset first threshold; the counting circuit is coupled with the output end of the state detection circuit and is used for receiving the output judgment signal from the state detection circuit, counting the judgment signal and outputting a phase-locked detection signal when the counting time exceeds a second threshold value.

Specifically, referring to fig. 4, the state detection circuit includes an and gate, an or gate, a delay circuit, and a sampling D flip-flop, and first, the and gate performs an and logic operation on the first phase detection signal and the second phase detection signal to obtain a first logic signal, and the or gate performs an or logic operation on the first phase detection signal and the second phase detection signal to obtain a second logic signal.

After the second logic signal is obtained, the second logic signal is delayed by a delay circuit, for example, the delay time is set to a first threshold, for example, the first threshold may be set to 2ns, and a third logic signal is obtained after the delay.

The clock end of the sampling D trigger is connected with the output end of the AND gate and used for receiving the first logic signal, the data end of the sampling D trigger is connected with the output end of the delay circuit and used for receiving the third logic signal, therefore, when the rising edge moment of the first logic signal arrives, the sampling D trigger outputs the third logic signal, the function of sampling the third logic signal by using the rising edge moment of the first logic signal is realized, the judgment signal is output, and the SET end of the D trigger is connected with the reset signal.

Referring to fig. 5, if the determination signal of the sampling output is at a high level, it indicates that the time difference between the rising edges of the first phase detection signal and the second phase detection signal is greater than a preset first threshold, then the time difference of the rising edge of the reference signal and the feedback signal at the input end of the phase frequency detector is larger than a preset first threshold value according to the specific relation of the input and output signals of the phase frequency detector on the time difference by mapping the phase frequency detector, if the judgment signal of the sampling output is low level, it is indicated that the time difference between the rising edges of the first phase detection signal and the second phase detection signal is smaller than a preset first threshold value, the time difference between the rising edges of the reference signal and the feedback signal at the input end of the phase frequency detector is smaller than a preset first threshold value.

Through analysis, if the judgment signal output by the sampling D trigger is in a low level, the phase difference is within a certain threshold value, but the judgment phase-locked loop needs to complete phase locking, the judgment signal is required to be in a low level in a plurality of continuous periods, and therefore a counting circuit is added at the rear stage of the state detection circuit to detect the state of the judgment signal in a plurality of continuous periods of timing.

The counting circuit is composed of N + 1D flip-flops, as shown in fig. 4, wherein the first to nth flip-flops are used for counting to form an N-bit counter, and the N +1 th flip-flop is used for outputting a phase-locked detection signal, where N is a positive integer greater than 1. The number N of flip-flops for counting in the counting circuit may be adaptively configured according to a predetermined counting time.

The clock end of the first trigger is connected with the output end of the AND gate, the clock end of the Nth trigger is connected with the inverted output end of the (N-1) th trigger, the data ends from the first trigger to the Nth trigger are connected with the inverted output end of the trigger, the clock end of the (N + 1) th trigger is connected with the non-inverted output end of the Nth trigger, and the data end of the (N + 1) th trigger is connected with the high level. The reset ends of all the N +1 triggers in the counting circuit are connected with the positive phase output end of the sampling D trigger and used for receiving the judgment signal.

If the judgment signal output by the state detection circuit is high level, the counter is immediately reset, the (N + 1) th trigger is also in a reset state, and the phase-locked detection signal is low level and indicates that the phase-locked loop circuit is in a phase-locked state and does not complete locking. When the judgment signal is low level, the counter realizes continuous counting, after the set counting time is reached, namely when the most significant bit signal finishes the state inversion from 0 to 1, the output end of the Nth trigger generates a rising edge to drive the (N + 1) th trigger to output high level, namely the phase-locked detection signal is high level, which indicates that the phase-locked loop circuit is in a locked state.

The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims

1. A lock-in detection circuit, the lock-in detection circuit comprising:

the phase frequency detector is used for receiving a first phase discrimination signal and a second phase discrimination signal from the phase frequency detector, performing logic operation on the first phase discrimination signal and the second phase discrimination signal, and determining and outputting a judgment signal according to the signal after the logic operation and a preset first threshold;

and the counting circuit is connected with the output end of the state detection circuit and is used for receiving the judgment signal from the state detection circuit, counting the judgment signal and outputting a phase-locked detection signal.

2. The lock-in detection circuit according to claim 1, wherein the state detection circuit comprises:

the first input end and the second input end of the AND gate are connected with the phase frequency detector and are respectively used for receiving the first phase detection signal and the second phase detection signal, and the AND gate performs AND logic operation on the first phase detection signal and the second phase detection signal and outputs a first logic signal;

the first input end and the second input end of the or gate are connected with the phase frequency detector and are respectively used for receiving the first phase detection signal and the second phase detection signal, and the or gate performs or logical operation on the first phase detection signal and the second phase detection signal and outputs a second logical signal;

the input end of the delay circuit is connected with the output end of the OR gate, and is used for delaying the second logic signal and outputting a third logic signal, and the delay time is a first threshold value;

and a clock end of the sampling trigger is connected with the output end of the AND gate and is used for receiving the first logic signal, a data end of the sampling trigger is connected with the output end of the delay circuit and is used for receiving the third logic signal, an SET end of the sampling trigger is connected with a reset signal, and the sampling trigger outputs the judgment signal according to the first logic signal and the third logic signal.

3. The lock-in detection circuit according to claim 2, wherein the counting circuit comprises N +1 flip-flops, where N is a positive integer greater than 1, the N +1 flip-flops comprising:

the clock end of the first trigger is connected with the output end of the AND gate;

the clock end of the Nth trigger is connected with the inverted output end of the (N-1) th trigger;

a clock end of the (N + 1) th flip-flop is connected with a non-inverting output end of the (N) th flip-flop, a data end of the (N + 1) th flip-flop is connected with a high level, and the (N + 1) th flip-flop is used for outputting the phase-locked detection signal;

the data ends of the first trigger to the Nth trigger are connected with the inverted output end of the trigger, and the first trigger to the Nth trigger are used for counting;

and the reset ends of the N +1 triggers are connected with the positive phase output end of the sampling trigger and used for receiving the judgment signal.

4. The lock-in detection circuit according to claim 3, wherein the flip-flop is a D flip-flop.