CN216213447U

CN216213447U - Power module package

Info

Publication number: CN216213447U
Application number: CN202122467735.3U
Authority: CN
Inventors: 李衡; 韩伟国; 张景尧; 张道智; 邱柏凯; 李泰广; 张孝民
Original assignee: Wenhao Electronics Co ltd; Industrial Technology Research Institute ITRI
Current assignee: Wenhao Electronics Co ltd; Industrial Technology Research Institute ITRI
Priority date: 2020-10-13
Filing date: 2021-10-13
Publication date: 2022-04-05
Anticipated expiration: 2031-10-13
Also published as: DE202021105530U1; TWM622999U

Abstract

A power module package includes a substrate, a ground pattern, a plurality of first wiring patterns, a plurality of gate driving elements, and a plurality of active elements. The ground pattern is disposed on the substrate. The first wiring pattern is provided on the substrate and spaced apart from the ground pattern in the first direction. The first wiring patterns are arranged in a second direction different from the first direction and spaced apart from each other. The gate driving elements are respectively disposed on the ground patterns and arranged in the second direction and spaced apart from each other. The gate driving elements have a common ground plane through a ground pattern. The active elements are respectively disposed on the first wiring patterns and each include a first transistor and a second transistor. The active elements are electrically connected to the corresponding gate driver elements and the corresponding first wiring patterns, respectively.

Description

Power module package

Technical Field

The utility model relates to a power module package.

Background

In recent years, the demand for low carbon emission has been emphasized, and the demand for electrically driven transportation has been increased. In electrically driven vehicles, a power module is one of the cores of electrical energy conversion and circuit control. However, the conventional discrete power devices (discrete power devices) have not been able to meet the current requirements in terms of heat dissipation and performance, and how to improve the performance of the power module is one of the major points in research and development.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to a power module package to solve the above problems.

To achieve the above object, the present invention provides a power module package, wherein the power module package can reduce noise (noise) of a digital signal by designing a common ground plane through the same ground pattern for a gate driving device, so as to improve performance of the power module package.

An embodiment of the present invention provides a power module package. The power module package includes a substrate, a ground pattern, a plurality of first wiring patterns, a plurality of gate driving elements, and a plurality of active elements. The substrate has a first surface and a second surface opposite to each other. The ground pattern is disposed on the first surface of the substrate. The plurality of first wiring patterns are provided on the substrate and spaced apart from the ground pattern in the first direction. The plurality of first wiring patterns are arranged in a second direction different from the first direction and spaced apart from each other. The plurality of gate driving elements are respectively disposed on the ground patterns and arranged in the second direction and spaced apart from each other. The plurality of gate driving elements have a common ground plane through a ground pattern. The plurality of active elements are respectively disposed on the first wiring patterns and each include a first transistor and a second transistor. The plurality of active elements are each independently electrically connected to the corresponding gate driver element and the corresponding first wiring pattern.

Each of the plurality of first wiring patterns includes a high-side region and a low-side region, wherein the first transistor and the second transistor are disposed in the high-side region and the low-side region, respectively.

The power module package further includes: a first passive element disposed between and electrically connected to the gate driving element and the first transistor; and a second passive element disposed between and electrically connected to the gate driver element and the second transistor.

The gate driving element transfers a signal to the first transistor through the first passive element, and the gate driving element transfers a signal to the second transistor through the second passive element.

The plurality of first wiring patterns are identical to each other in shape and size.

The power module package further includes: a heat dissipation structure disposed on the second surface of the substrate.

The power module package further includes: a first lead frame group connected to one of the gate driving elements; and a plurality of second lead frame groups respectively connected to other gate driving devices among the plurality of gate driving devices, wherein the first lead frame group includes a lead frame connected to the ground pattern, and at least one of the plurality of second lead frame groups does not include a lead frame connected to the ground pattern.

The power module package further includes: a plurality of third lead frame groups respectively electrically connected to the plurality of active elements, wherein widths of the lead frames in the third lead frame groups in the second direction are greater than widths of the lead frames in the first lead frame group and the second lead frame group in the second direction.

The ground pattern includes: a first portion in contact with one of the gate driving elements; a second portion in contact with another one of the gate driving elements, and the another one of the gate driving elements is adjacent to the one of the gate driving elements; and a third portion connecting the first portion and the second portion.

The power module package further includes: a plurality of second wiring patterns provided below and electrically connected to the corresponding gate driving elements, respectively, wherein the second wiring patterns are arranged in the second direction and spaced apart from each other, and the second wiring patterns are spaced apart from the ground pattern and the first wiring patterns; wherein the third portion of the ground pattern is arranged between the first wiring pattern and the second wiring pattern. Based on the above, the power module package of the present invention has an advantage in that the power module package can reduce noise of the digital signal by designing the gate driving element to have the common ground plane through the same ground pattern, so as to improve performance of the power module package.

In order to make the aforementioned and other features and advantages of the utility model more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic top view of a power module package according to an embodiment of the utility model;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

fig. 3 is a circuit diagram of a power module package of an embodiment of the present invention.

Detailed Description

The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numbers refer to the same or similar elements, and the following paragraphs will not be repeated.

It will be understood that when an element such as it is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. If an element is referred to as being "directly on" or "directly connected" to another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections, and "electrically connected" or "coupled" may mean that there are other elements between the two.

As used herein, "about," "approximately," or "substantially" includes the recited value and the average value over an acceptable range of deviation of the specified value as can be determined by one of ordinary skill in the art, taking into account the particular number of measurements in question and the errors associated with the measurements (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated values, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about", "approximately" or "substantially" may be selected based on optical properties, etching properties or other properties to select a more acceptable range of deviation or standard deviation, and not to apply one standard deviation to all properties.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. In this case, the singular form includes the plural form unless the context otherwise explains.

Fig. 1 is a schematic top view of a power module package according to an embodiment of the utility model. Fig. 2 is a schematic cross-sectional view of fig. 1 taken along the sectional line a-a'. Fig. 3 is a circuit diagram of a power module package according to an embodiment of the utility model.

Referring to fig. 1 and 2, a power module package (power module package) 10 includes a substrate 100, a ground pattern GND, a plurality of

first wiring patterns

110, 112, 114, a plurality of

gate driving elements

120a, 120b, 120c, and a plurality of

active elements

130, 132, 134.

The substrate 100 has a first surface S1 and a second surface S2 opposite to each other. The substrate 100 may include an insulating material having good thermal conductivity. For example, the substrate 100 may include a ceramic material such as alumina, aluminum nitride, or silicon nitride, or an insulating material such as epoxy. In some embodiments, the substrate 100 may be, for example, a ceramic substrate.

The ground pattern GND is disposed on the first surface S1 of the substrate 100. The material of the ground pattern GND may include a conductive material. For example, the conductive material may be a metal material such as copper, aluminum, other suitable metal materials, or alloys thereof.

The first wiring traces 110, 112, and 114 are provided on the substrate 100 and spaced apart from the ground pattern GND in the first direction D1. The

first wiring patterns

110, 112, 114 are arranged in a second direction D2 different from the first direction D1 and spaced apart from each other. In some embodiments, the first direction D1 and the second direction D2 are parallel to the first surface S1 of the substrate 100. In some embodiments, the first direction D1 is perpendicular to the second direction D2. The material of the

first wiring patterns

110, 112, 114 may include a conductive material. For example, the conductive material may be a metal material such as copper.

The

gate driving elements

120a, 120b, and 120c are respectively disposed on the ground patterns GND and arranged in the second direction D2 while being spaced apart from each other. The

gate driving elements

120a, 120b, and 120c have a common ground plane through the same ground pattern GND, so that noise of the digital signal can be reduced to improve performance of the power module package 10. If the ground signals of the

gate driving elements

120a, 120b, and 120c are connected by wiring, a potential drop (ground level) occurs due to the impedance of the loop, so that the ground layouts of the

gate driving elements

120a, 120b, and 120c have different ground levels. Therefore, the ground pattern GND is designed as a whole pattern (e.g., a continuous film), which can reduce the loop impedance and at the same time contribute to the heat dissipation performance of the

gate driving devices

120a, 120b, 120 c.

In some embodiments, the ground pattern GND may include a first portion (e.g., a portion in contact with the gate driving element 120a) in contact with one of the

gate driving elements

120a, 120b, and 120c, a second portion (e.g., a portion in contact with the gate driving element 120b) in contact with another one of the

gate driving elements

120a, 120b, and 120c, and a third portion connecting the first portion and the second portion. In some embodiments, one of the

gate drive elements

120a, 120b, 120c (e.g., gate drive element 120a) may be adjacent to another of the

gate drive elements

120a, 120b, 120c (e.g., gate drive element 120 b). In some embodiments, the third portion may extend along the arrangement direction (e.g., the second direction D2) of the

gate driving elements

120a, 120b, 120 c. In some embodiments, the areas of the first and second portions of the ground pattern GND may be greater than the area of the third portion of the ground pattern GND. In some embodiments, the power module package 10 may include a pad (not shown) connected to the

gate driving elements

120a, 120b, and 120c and the ground pattern GND.

The

active elements

130, 132, 134 are respectively disposed on the

first wiring patterns

110, 112, 114 and each include

first transistors

130a, 132a, 134a and

second transistors

130b, 132b, 134 b. The

active elements

130, 132, 134 are each independently electrically connected to the corresponding

gate drive element

120a, 120b, 120c and the corresponding

first wiring pattern

110, 112, 114. In some embodiments, the

active elements

130, 132, 134 may further include diodes (as shown in fig. 3) electrically connected to the

first transistors

130a, 132a, 134a and the

second transistors

130b, 132b, 134 b.

In some embodiments, the

first transistors

130a, 132a, 134a and the

second transistors

130b, 132b, 134b may constitute a half-bridge structure (half-bridge). That is, each of the

first wiring patterns

110, 112, 114 may include a high side region (high side region)110a, 112b, 114a and a low side region (low side region)110b, 112b, 114 b. The

first transistors

130a, 132a, 134a may be disposed in the

high side regions

110a, 112b, 114a, and the

second transistors

130b, 132b, 134b may be disposed in the

low side regions

110b, 112b, 114 b. In some embodiments, the

first transistors

130a, 132a, 134a in the

high side regions

110a, 112b, 114a can be electrically connected to the

second transistors

130b, 132b, 134b in the

low side regions

110b, 112b, 114b by wire bonding. For example, the

first transistors

130a, 132a, 134a in the high-

side regions

110a, 112b, 114a may be electrically connected to the

second transistors

130b, 132b, 134b in the low-

side regions

110b, 112b, 114b by a conductive line WL 1. In some embodiments, the

active devices

130, 132, 134 may be connected to the

first wiring patterns

110, 112, 114 through the pads 135. That is, the

first transistors

130a, 132a, 134a and the

second transistors

130b, 132b, 134b may be connected to the

first wiring patterns

110, 112, 114 through the pads 135.

In some embodiments, the

active elements

130, 132, 134 may be electrically connected to the corresponding

gate driving elements

120a, 120b, 120c and the corresponding

first wiring patterns

110, 112, 114 independently of each other, and the shapes and sizes of the

first wiring patterns

110, 112, 114 are substantially the same as each other (e.g., the area difference of the

first wiring patterns

110, 112, 114 is within a variation range of ± 10%), such that the

active elements

130, 132, and 134 have the same path layout as each other, resulting in the

active elements

130, 132, and 134 having similar parasitic inductances. Therefore, when the active element 130, the active element 132, and the active element 134 are respectively electrically connected to three phases (for example, U-phase, V-phase, W-phase) having a phase offset by 120 degrees, the loss of three-phase switching can be balanced.

In table 1 below, example 1 to example 3 show simulation results of parasitic inductances of the

active elements

130, 132, 134 in the high-

side regions

110a, 112a, 114a, respectively. The path may refer to the contents shown in fig. 1 and 3. The parasitic inductance difference is based on example 1 as a comparison.

TABLE 1

	Route of travel	Parasitic inductance (nH)	Parasitic inductance difference (%)
				Example 1	Terminal Pu → output terminal U	13.39	0
Example 2	Terminal Pv → output terminal V	13.319	-0.53
				Example 3	Terminal Pw → output terminal W	13.343	-0.35

In some embodiments, the power module package 10 may further include a plurality of

second wiring patterns

140, 142, 144. The

second wiring patterns

140, 142, 144 may be disposed below the corresponding

gate driving elements

120a, 120b, 120c, respectively, and electrically connected to the corresponding

gate driving elements

120a, 120b, 120 c. The

second wiring patterns

140, 142, 144 may be spaced apart from the ground pattern GND and the

first wiring patterns

110, 112, 114. In some embodiments, the

second wiring patterns

140, 142, 144 may be arranged in the second direction D2 and spaced apart from each other. In some embodiments, the third portion of the ground pattern GND described above may be arranged between the first wiring pattern and the second wiring pattern (e.g., between the first wiring pattern 112 and the second wiring pattern 142, or between the first wiring pattern 114 and the second wiring pattern 144). In some embodiments, the main

gate driving elements

120a, 120b, and 120c may be connected to the

second wiring patterns

140, 142, and 144 through the connection pads 135. The material of the

second wiring patterns

140, 142, 144 may include a conductive material. For example, the conductive material may be a metal material such as copper.

In some embodiments, the power module package 10 may further include a first passive element 150a and a second passive element 150 b. The first passive element 150a may be disposed between the

gate driving elements

120a, 120b, and 120c and the

first transistors

130a, 132a, and 134a and electrically connected to the

gate driving elements

120a, 120b, and 120c and the

first transistors

130a, 132a, and 134 a. The second passive element 150b may be disposed between the

gate driving elements

120a, 120b, and 120c and the

second transistors

130b, 132b, and 134b and electrically connected to the

gate driving elements

120a, 120b, and 120c and the

second transistors

130b, 132b, and 134 b. As such, the

gate driving devices

120a, 120b, and 120c can have enhanced driving capability or stable driving voltage when driving the

first transistors

130a, 132a, and 134a in the high-

side regions

110a, 112a, and 114a and the

second transistors

130b, 132b, and 134b in the low-

side regions

110b, 112b, and 114 b. In this embodiment, the

gate driving elements

120a, 120b, 120c may transfer signals to the

first transistors

130a, 132a, 134a through the first passive element 150a, and the

gate driving elements

120a, 120b, 120c may transfer signals to the

second transistors

130b, 132b, 134b through the second passive element 150 b. The first passive element 150a and the second passive element 150b may be, for example, resistors or capacitors.

In some embodiments, when the first passive element 150a and the second passive element 150b are resistors, the driving capability of the

gate driving elements

120a, 120b, 120c can be enhanced. In other embodiments, when the first passive element 150a and the second passive element 150b are capacitors, the driving voltages of the

gate driving elements

120a, 120b, and 120c can be stabilized.

In some embodiments, the power module package 10 may further include the

wiring patterns

143 and 145 disposed on the substrate 100 and spaced apart from the

first wiring patterns

110, 112, 114, the

second wiring patterns

140, 142, 144, and the ground pattern GND. The

wiring patterns

143 and 145 may be connected to the high-

side regions

110a, 112a, 114a and the low-

side regions

110b, 112b, 114b of the

first wiring patterns

110, 112, 114, respectively, via wires WL 2.

In some embodiments, the first passive element 150a and the second passive element 150b may be disposed on the

wiring patterns

143 and 145, respectively. One ends of the first and second

passive elements

150a and 150b may be connected with the

second wiring patterns

140, 142, 144, and the other ends of the first and second

passive elements

150a and 150b may be connected with the

wiring patterns

143 and 145, respectively. In this embodiment, signals from the

gate driving elements

120a, 120b, 120c can be transferred to the first passive element 150a and the second passive element 150b via the

second wiring patterns

140, 142, 144. The signal may then be transferred to the

active elements

130, 132, 134 via the

wiring patterns

143, 145, the wire WL2, and the

first wiring patterns

110, 112, 114.

In some embodiments, the power module package 10 may further include a first lead frame group LF1 and a plurality of second lead frame groups LF 2. The first lead frame group LF1 is connected to one of the

gate driving elements

120a, 120b, and 120c (e.g., the gate driving element 120 c). The plurality of second lead frame groups LF2 are respectively connected to other gate driving elements (e.g., the gate driving element 120a and the gate driving element 120b) of the plurality of

gate driving elements

120a, 120b, and 120 c. The first lead frame set LF1 may include a lead frame 160 connected to the ground pattern GND and a lead frame 162 connected to the gate driving device 120 c. The second lead frame sets LF2 may include lead frames 162 connected to the

gate driving devices

120a, 120 b. At least one of the second lead frame sets LF2 may not include the lead frame 160 connected to the ground pattern GND. In some embodiments, the plurality of second lead frame sets LF2 may not include the lead frame 160 connected to the ground pattern GND. In some embodiments, the lead frame 162 may be electrically connected to the

second wiring patterns

140, 142, and 144 through the pads 135. The lead frames 160, 162 may be made of a conductive material such as metal, but not limited thereto.

Referring to fig. 1 and 3, the first and second lead frame sets LF1 and LF2 may include lead frames 162 to which boosting voltages vb (u), vb (v), vb (w) are applied, lead frames 162 to which operating voltages vcc (u), vcc (v), vcc (w) are applied, lead frames 162 to which high side driving signals hin (u), hin (v), hin (w) are input, and lead frames 162 to which low side driving signals lin (u), lin (v), lin (w) are input. The first lead frame group LF1 may include a lead frame 160 connected to the ground pattern GND (corresponding to the ground signal COM shown in fig. 3). In some embodiments, the

second wiring patterns

140, 142, 144 may include a plurality of sub-wiring patterns (not shown) spaced apart from each other or a plurality of wirings independent from each other, so that the lead frame 162 for the boost voltages vb (u), vb (v), vb (w), the operating voltages vcc (u), vcc (v), vcc (w), the input high-side driving signals hin (u), hin (v), hin (w), and the input low-side driving signals (u), lin (v), lin (w) can be connected to the

gate driving elements

120a, 120b, 120c via the independent sub-wiring patterns or wirings of the

second wiring patterns

140, 142, 144, respectively.

In some embodiments, the power module package 10 may further include a plurality of third lead frame groups LF 3. The third lead frame groups LF3 may be electrically connected to the

active elements

130, 132, 134, respectively. Each of the third lead frame group LF3 may include a plurality of lead frames 170 connected with the

first wiring patterns

110, 112, 114. In some embodiments, the lead frame 170 may be connected to the

first wiring patterns

110, 112, 114 through the pads 135. The lead frame 170 may be made of a conductive material such as metal, but not limited thereto. In some embodiments, the width of the lead frame 170 in the second direction D2 of the third lead frame group LF3 is greater than the width of the lead frames 160 and 162 in the second direction D2 of the first lead frame group LF1 and the width of the lead frame 162 in the second direction D2 of the second lead frame group LF 2.

Referring to fig. 1 and 3, the third lead frame set LF3 may include a lead frame 170 (corresponding to terminals Pu, Pv, Pw) connected to the

first transistors

130a, 132a, 134a, a lead frame 170 (corresponding to the output terminal U, V, W) connected to the

first transistors

130a, 132a, 134a and the

second transistors

130b, 132b, 134b, and a lead frame 170 (corresponding to terminals Nu, Nv, Nw) connected to the

second transistors

130b, 132b, 134 b.

Referring to fig. 2, in some embodiments, the power module package 10 may further include a heat dissipation structure 180 disposed on the second surface S2 of the substrate 100, so as to improve performance of the power module package 10 by increasing heat transfer efficiency of the power module package 10. In some embodiments, the heat dissipation structure 180 may be, for example, a copper layer, but not limited thereto.

In summary, in the embodiments of the utility model, the power module package can reduce the noise of the digital signal by designing the gate driving device to have the common ground plane through the same ground pattern, so as to improve the performance of the power module package.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power module package, comprising:

a substrate having a first surface and a second surface opposite to each other;

a ground pattern disposed on the first surface of the substrate;

a plurality of first wiring patterns provided on the substrate and spaced apart from the ground pattern in a first direction, wherein the plurality of first wiring patterns are arranged in a second direction different from the first direction and spaced apart from each other;

a plurality of gate driving elements respectively disposed on the ground patterns and arranged in the second direction and spaced apart from each other, wherein the plurality of gate driving elements have a common ground plane through the ground patterns; and

a plurality of active elements respectively provided on the plurality of first wiring patterns and each including a first transistor and a second transistor, wherein the plurality of active elements are each independently electrically connected to the corresponding gate driver element and the corresponding first wiring pattern.

2. The power module package according to claim 1, wherein each of the plurality of first wiring patterns includes a high-side region and a low-side region, wherein the first transistor and the second transistor are provided in the high-side region and the low-side region, respectively.

3. The power module package of claim 2, further comprising:

a first passive element disposed between and electrically connected to the gate driving element and the first transistor; and

and a second passive element disposed between the gate driver element and the second transistor and electrically connected to the gate driver element and the second transistor.

4. The power module package of claim 3, wherein the gate drive element passes a signal to the first transistor through the first passive element and the gate drive element passes a signal to the second transistor through the second passive element.

5. The power module package according to claim 1, wherein shapes and sizes of the plurality of first wiring patterns are identical to each other.

6. The power module package of claim 1, further comprising:

a heat dissipation structure disposed on the second surface of the substrate.

7. The power module package of claim 1, further comprising:

a first lead frame group connected to one of the gate driving elements; and

a plurality of second lead frame groups respectively connected with other gate driving elements in the plurality of gate driving elements,

the first lead frame set includes a lead frame connected to the ground pattern, and at least one of the second lead frame sets does not include a lead frame connected to the ground pattern.

8. The power module package of claim 7, further comprising:

a plurality of third lead frame groups electrically connected to the plurality of active elements, respectively,

wherein a width of the lead frames in the third lead frame group in the second direction is greater than a width of the lead frames in the first and second lead frame groups in the second direction.

9. The power module package of claim 1, wherein the ground pattern comprises:

a first portion in contact with one of the gate driving elements;

a second portion in contact with another one of the gate driving elements, and the another one of the gate driving elements is adjacent to the one of the gate driving elements; and

a third portion connecting the first portion and the second portion.

10. The power module package of claim 9, further comprising:

a plurality of second wiring patterns provided below and electrically connected to the corresponding gate driving elements, respectively, wherein the second wiring patterns are arranged in the second direction and spaced apart from each other, and the second wiring patterns are spaced apart from the ground pattern and the first wiring patterns;

wherein the third portion of the ground pattern is arranged between the first wiring pattern and the second wiring pattern.