CN216213375U - Carrier substrate, separation apparatus and memory device - Google Patents

Abstract

The present disclosure provides a carrier substrate. The carrier substrate includes: a body having a first surface and a second surface opposite to the first surface, and a plurality of side surfaces surrounding the first and second surfaces; a plurality of through holes vertically extending from the first surface to the second surface, arranged in an array on the body, thereby dividing the body into a plurality of cells arranged in an array; and a plurality of recesses arranged in the plurality of side surfaces and each recessed inward from a side surface of the body. The present disclosure also provides a separation apparatus and a memory device.

Description

Carrier substrate, separation apparatus and memory device

Technical Field

The disclosed embodiments relate to a carrier substrate, a separation apparatus, and a memory device.

Background

The strong growth in demand for portable consumer electronics has driven the need for high capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, have been widely used to meet the increasing demand for digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, make such storage devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs and cellular telephones.

As technology continues to evolve, smaller packages with better performance are needed. As the wafer side is limited due to its complexity, innovations and improvements to the back end of the line are critical to technological breakthroughs.

SUMMERY OF THE UTILITY MODEL

At least one embodiment of the present disclosure provides a carrier substrate, including: a body having a first surface and a second surface opposite to the first surface, and a plurality of side surfaces surrounding the first surface and the second surface; a plurality of through holes vertically extending from the first surface to the second surface, arranged in an array on the body, thereby dividing the body into a plurality of cells arranged in an array; and a plurality of notches arranged in the plurality of side surfaces and each recessed toward the inside of the body.

For example, in a carrier substrate provided in at least one embodiment of the present disclosure, each of the plurality of cells is for a substrate of a separate chip.

For example, in a carrier substrate provided in at least one embodiment of the present disclosure, the plurality of recesses respectively correspond to rows and columns of the array of the plurality of through holes.

For example, in the carrier substrate provided in at least one embodiment of the present disclosure, the plurality of through holes further includes one or more additional through holes, and the one or more additional through holes are equidistantly arranged on at least one side to further separate the plurality of cells.

For example, in a carrier substrate provided in at least one embodiment of the present disclosure, the plurality of through holes are substantially the same in shape and size.

For example, in the carrier substrate provided in at least one embodiment of the present disclosure, a cross-sectional shape of the through-hole may be selected from one of the following: circular, polygonal, and polygonal.

For example, in the carrier substrate provided in at least one embodiment of the present disclosure, the cross-sectional shape of the notch may be selected from one of the following: triangle, U-shape, trapezoid, drop shape and trapezoid-like with two narrowed sides.

For example, in a carrier substrate provided in at least one embodiment of the present disclosure, the size of the through-hole is less than 80 μm.

At least one embodiment of the present disclosure also provides a separation apparatus configured to separate the carrier substrate as above, the separation apparatus including: a mechanical cutting module configured to partially mechanically cut the plurality of notches in the carrier substrate; and a separation module configured to break the carrier substrate in a direction of a row or a column of the through holes of the carrier substrate by changing a temperature of the carrier substrate or applying vibration to the carrier substrate, thereby forming a plurality of separation units.

At least one embodiment of the present disclosure also provides a memory device including a separation unit formed by separating the carrier substrate as above, and a three-dimensional NAND memory die disposed on the separation unit.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1A shows a top view of a first embodiment of a carrier substrate of the present disclosure.

Fig. 1B illustrates a cross-sectional side view of the carrier substrate of fig. 1A taken along section line L-L' of fig. 1A.

Fig. 2A shows a top view of a second embodiment of a carrier substrate of the present disclosure.

Fig. 2B illustrates a cross-sectional side view of the carrier substrate of fig. 2A taken along section line a-a' of fig. 2A.

Fig. 3A shows a top view of a third embodiment of a carrier substrate of the present disclosure.

Fig. 3B illustrates a cross-sectional side view of the carrier substrate of fig. 3A taken along section line B-B' of fig. 3A.

Fig. 4 shows a schematic of various cross-sectional shapes of vias in a carrier substrate of the present disclosure.

Fig. 5 shows a schematic of various cross-sectional shapes of a recess in a carrier substrate of the present disclosure.

Fig. 6 shows a top view of a fourth embodiment of the carrier substrate of the present disclosure.

Fig. 7 shows a side view and a top view of a first embodiment of a memory device of the present disclosure.

Fig. 8 shows a side view and a top view of a second embodiment of a memory device of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "coupled," "connected," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In packaging technology, to carry semiconductor die, the semiconductor die is attached to a tape-shaped carrier substrate. Next, the semiconductor die undergoes subsequent wire bonding, molding, solder ball attachment, and other common packaging techniques. Finally, the carrier substrate is mechanically cut to obtain separated chip units. However, such a dicing process using only mechanical dicing to obtain the separation units has to require a large space between the die and the separation units due to the large tolerance of the mechanical dicing, so as to avoid the mechanical dicing damaging the already attached die.

To further reduce the size of the carrier substrate and yield loss from mechanical dicing, the present disclosure provides a carrier substrate. A body having a first surface and a second surface opposite to the first surface, and a plurality of side surfaces surrounding the first surface and the second surface; a plurality of through holes vertically extending from the first surface to the second surface, arranged in an array on the body, thereby dividing the body into a plurality of cells arranged in an array; and a plurality of recesses arranged in the plurality of side surfaces and each recessed inward from the side surface of the body. A plurality of through holes and notches may provide a frangible location. The through hole portion can be stressed by only adopting mechanical cutting on the notch portion through the positions of the through hole and the notch, so that the spacing between the bare chip and the separation unit is smaller and smoother. Therefore, the carrier substrate of the present disclosure can greatly reduce the package pitch, thereby reducing the package size and the footprint size of the discrete unit.

Fig. 1A shows a top view of a first embodiment of a carrier substrate 100 of the present disclosure. Fig. 1B illustrates a cross-sectional side view of the carrier substrate 100 of fig. 1A taken along section line L-L' of fig. 1A.

As shown in fig. 1A, the carrier substrate 100 includes a body 110, a plurality of through-holes 120, a plurality of recesses 130, and a plurality of cells 140. The body 110 has a first surface 112, a second surface 114 opposite to the first surface 112, and a plurality of side surfaces 116 surrounding the first surface 112 and the second surface 114, as shown in fig. 1B. The plurality of through-holes 120 extend perpendicularly from the first surface 112 to the second surface 114 and are arranged in an array on the body 110, thereby dividing the body into a plurality of cells 140 (a plurality of cells 240, 340 as shown by the dotted-dashed area in fig. 1A and as shown by the dotted-dashed area to be described in fig. 2A and 3A) arranged in an array. A plurality of recesses 130 are disposed in the plurality of side surfaces 116 and each recess 130 is recessed inwardly from the side surface 116 of the body 110.

For example, the body 110 may be shaped as a strip (i.e., rectangular) as shown, and may be constructed of a dielectric material. The dielectric material may comprise one of the following materials: phenolic resin, epoxy resin, polyester resin and the like. Optionally, the carrier substrate 100 is optionally covered with a conductive material. The conductive material may be copper or other metallic material. Optionally, electrically conductive vias are optionally disposed in the carrier substrate 100. The live channel may be filled with copper or other metallic material. Alternatively, the carrier substrate 100 may be made of a semiconductor material such as silicon or silicon carbide. Further, one of the first surface 112 and the second surface 114 of the body 110 can be attached with a die unit.

In some examples, the plurality of through-holes 120 may extend perpendicularly from the first surface 112 to the second surface 114 and be arranged in an array on the body 110. For example, a plurality of through holes arranged in an array form rows and columns, respectively (rows and columns divided by dotted lines in fig. 1), thereby partitioning the regions of the cells 140. In the case where a small-sized through-hole (such as on the order of micrometers) is required, a high-precision through-hole is obtained using, for example, an instrument that generates a high-energy photon beam or ion beam such as a laser, a plasma generator, or the like. The vias 120 may also be formed using methods now commonly used or later developed and are not intended to be limiting of the present disclosure.

In some examples, the plurality of recesses 130 may be arranged in the plurality of side surfaces 116 and each recess 130 is recessed inwardly from the side surface 116 of the body 110. As shown in fig. 1A and 1B, the recess 130 does not extend completely through the carrier substrate 100. The notch 130 provides a location mark for a subsequent mechanical cutting process. Also, since the recess 130 does not completely penetrate the carrier substrate 100, the overall mechanical strength of the carrier substrate 100 is maintained. For example, each of the plurality of notches can be achieved by a punch, drill, or the like machine. In some examples, each of the plurality of notches may also be obtained using a laser, a plasma generator, or the like that generates a high energy photon beam or ion beam. The recess 130 may also be formed using methods now commonly used or later developed, and the present disclosure is not limited thereto.

In the carrier substrate 100 of fig. 1A, each of the plurality of cells 140 corresponds to a substrate of an individual chip. As shown in fig. 1A, each cell is obtained by dividing a row-column distribution of through holes. The substrate of the individual chips can ensure that each cell 140 carries a respective individual chip. In some examples, the footprint area of an individual chip may be slightly smaller than the footprint area of each cell, so as to leave sufficient spacing for separating each cell. In some examples, the individual chips may be semiconductor chips, such as a stack of memory dies. For example, the material of the substrate of the individual chip may be a semiconductor such as silicon. But the individual chip, the substrate of the individual chip of the present disclosure is not limited thereto.

In the embodiment of fig. 1A and 1B, the arrangement of the vias 120 and recesses 130 in the carrier substrate 100 can facilitate fracturing between multiple units, greatly reducing the pitch required for fracturing, thereby reducing the package size and footprint size of the singulated units.

Fig. 2A shows a top view of a second embodiment of a carrier substrate 200 of the present disclosure. And fig. 2B shows a cross-sectional side view of the carrier substrate 200 of fig. 2A taken along section line a-a' of fig. 2A.

As shown in fig. 2A and 2B, the substrate 200 has notches 230 distributed on the side surface of the carrier substrate 200. The plurality of notches 230 correspond to rows and columns, respectively, of the array of the plurality of through holes 220. Specifically, notches 230 are respectively arranged on the four side surfaces 216 of the carrier substrate 200 at positions corresponding to each row and each column of the through holes 220. In this way, the notches 230 are disposed at both ends of each row and each column of the array of through-holes 220, facilitating separation of the carrier substrates 200 by the shortest distance between the through-holes 220 of each row or each column. In the example of fig. 2A, the notch 230 extends vertically through the substrate 200. In other words, the recess 230 may be formed from through the carrier substrate 200 as well as the through-hole 220. The carrier substrate 200 in fig. 2A and 2B is substantially the same as the carrier substrate 100 in fig. 1 in other features, and thus will not be described again here.

In this embodiment, the corresponding arrangement of the through-holes 220 and the notches 230 makes the carrier substrate susceptible to breakage along the rows and columns. Also, visualization of the through-going recess may intuitively locate the starting position of the separation of the plurality of units.

Fig. 3A shows a top view of a third embodiment of a carrier substrate 300 of the present disclosure. And fig. 3B shows a cross-sectional side view of the carrier substrate 300 of fig. 3A taken along section line B-B' of fig. 3A.

As shown in fig. 3A, in the body 310, the through-holes 320 include through-holes 320a located at the apexes of the plurality of cells 340, the positions of which are the same as the plurality of through- holes 120 and 220 in fig. 1 and 2A described previously. In addition, in the present embodiment, the through holes 320 further include one or more additional through holes 320b, and the one or more additional through holes 320b are equidistantly disposed on at least one side of the cell 340, further dividing the plurality of cells 340. In some examples, one or more additional vias 320b are also disposed between any notch 330 and the via 320a at the cell vertex closest to that notch 330. In some examples, a plurality of additional vias 320b are arranged equidistantly per side of the cell, wherein the number of additional vias 320b may be 1, 2, 3, or even more.

In the present embodiment, the distance between the through holes 320 becomes significantly shorter so that the carrier substrate is more easily broken. Furthermore, the equidistant arrangement of the through-holes can promote the same or close conditions of the fracture, so that the homogenization of the fracture of the separation unit is achieved.

In some examples, the plurality of vias 320 are substantially identical in shape and size. As shown in fig. 3B, the diameter of the through-hole 320a at the apex is d1, and the diameter of the additional through-hole 320B is d 2. For example, the diameter d1 of the through-hole 320a at the apex is equal to the diameter d2 of the additional through-hole 320 b.

In some examples, the cross-sectional shape of the through-hole 320 includes a circle, a polygon, or a polygon. Fig. 4 shows a schematic view of various cross-sectional shapes of vias 120, 220, and 230 in various embodiments of the carrier substrate of the present disclosure. As shown in fig. 4, for example, the cross-sectional shape of the through-hole 420 may be selected from one of a polygon or a polygon of: diamond, hexagonal, octagonal, and tetragonal. For example, the through- holes 120, 220, 320 are designed as columns extending perpendicularly from the upper surface 112, 212, 312 to the lower surface 114, 214, 314. For example, the cross-sectional shape of the through-hole may also have any other shape. In some examples, the size of the via is less than 80 μm, preferably less than 50 μm, more preferably less than 40 μm or less.

In this embodiment, a cross-sectional shape other than circular may help to create a larger footprint area after a substrate carrier fracture occurs.

Fig. 5 shows a schematic of various cross-sectional shapes of a notch in a carrier substrate of the present disclosure. As shown in fig. 5, the cross-sectional shape of the notch may be selected from one of the following: a triangle, a U shape, a trapezoid, a drop shape, a trapezoid-like shape with narrowed side edges, and the like. According to the tapering shape of these recesses, the recesses are in such a way that the cross-sectional dimension of the side surface is larger than the cross-sectional dimension away from the side surface, thereby facilitating mechanical cutting apart of the side surface of the carrier substrate with larger tolerances. The cross-sectional dimension of the recess away from the side surface 516 is less than 80 μm, preferably less than 50 μm, more preferably less than 40 μm or less.

In this embodiment, the different cross-sectional shapes of the notches may facilitate separation of the plurality of cells with less precision at larger cross-sectional dimensions of the proximal surface of the notch, and with greater precision at smaller interface dimensions away from the side surface.

The carrier substrate 300 shown in fig. 3A and 3B is substantially the same as the carrier substrate 100 shown in fig. 1A and 1B in other features, and thus will not be described again.

As previously indicated, a chip manufacturing company may attach singulated die or three-dimensionally stacked semiconductor devices in each unit within a carrier substrate and separate the carrier substrate carrying the die using a separation apparatus. A schematic view of a carrier substrate 600 of the present disclosure is shown in fig. 6.

As shown in fig. 6, the carrier substrate 600 includes a central portion 660 and a peripheral portion 650 around the central portion 660. For example, the central portion 660 encompasses multiple units 640, where each unit 640 can be a separate die substrate to which the die is attached, as previously described. The peripheral portion 650 and the central portion 660 in the carrier substrate 600 may be separated into a plurality of separation units, respectively, using a separation apparatus (not shown) to be described in detail below. The peripheral portion 650 and the central portion 660 shown in fig. 6 are merely schematic to illustrate the use of different separation devices for the two portions. The separation apparatus used in the present disclosure is set forth in detail below.

In some examples, a separation apparatus configured to separate a carrier substrate as above is provided. The separation apparatus comprises: a mechanical cutting module configured to partially mechanically cut the plurality of notches in the carrier substrate; and a separation module configured to break the carrier substrate in a direction of a row or a column of the through holes of the carrier substrate by changing a temperature of the carrier substrate or applying vibration to the carrier substrate, thereby forming a plurality of separation units.

The operation of the separating apparatus will now be further described with reference to figure 6. First, the mechanical cutting module is configured to sequentially mechanically cut portions of the body of the carrier substrate in areas covering the notches. For example, the peripheral portion 650 of the carrier substrate 600 may be mechanically cut. Alternatively, the mechanical cutting may be performed only for the vicinity of the opening of the notch.

Next, the carrier substrate is further decomposed using a separation module. In some examples, the separation module may be a thermal separation module, i.e., configured to change the temperature of the carrier substrate 600 over a temperature range, thereby applying thermal stress to the carrier substrate 600. For example, the thermal separation module applies thermal cycles to the carrier substrate 600, such that the stress of the carrier substrate 600 is periodically changed accordingly. For example, the carrier substrate 600 may experience thermal expansion and contraction effects during heating or cooling. By utilizing the effects of volume expansion at high temperatures and volume contraction at low temperatures, the stress of each cut notch and through hole in the carrier substrate 600 varies periodically, so that the material of the carrier substrate 600 between the rows and columns of the array of the plurality of through holes is broken in the direction of the rows and columns (e.g., dotted lines schematically shown in fig. 6) by the thermal stress, forming a plurality of discrete units. The temperature range can be maintained within the temperature range of normal operation of the chip, so that the chip is not damaged. By using the mechanical cutting module first and then the thermal separation module, it is possible to achieve a gap of 50 μm or less between the respective units, which is much smaller than the size of the gap of the unit separated by mechanical cutting alone.

In addition, the thermal separation module may be configured to provide temperature control to the entire carrier substrate, or to only the central region 660 of the carrier substrate. For example, the thermal separation module may include a heater or heating mat, a temperature controller, and the like.

Alternatively, in some embodiments, the separation apparatus may also be a vibratory separation module and configured to continuously apply vibrations to the central portion 660 of the carrier substrate 600 to break the carrier substrate 600 in the direction of the rows or columns of through-holes, forming a plurality of separation units. For example, when the vibration separation module applies vibration at a certain frequency, the carrier substrate may be made to form a smoother split gap along the shortest distance between the through holes. The vibration isolation module may include other vibration elements such as a vibrator that generates high frequency micro-amplitude vibrations. The high frequency vibrations may be of the order of kHz or higher. Therefore, as the vibration frequency is increased, the breaking speed of the carrier substrate is faster, so that the separation unit having a smoother split gap can be formed by the combination of the mechanical cutting module and the vibration separation module. The gap between the plurality of separated units thus obtained is 50 μm or less, which is much smaller than that of the separated units by mechanical cutting alone.

With the carrier substrate and the separation apparatus of the present disclosure, a memory device as shown in fig. 7 and 8 can be obtained. Fig. 7 shows a first embodiment of a memory device 1000 of the present disclosure. And figure 8 shows a second embodiment of a memory device 1000 of the present disclosure.

As shown in fig. 7 and 8, the memory device 1000 includes separation units 1100, 1300 formed by separating the aforementioned carrier substrate, and three-dimensional NAND memory dies 1200 arranged on the separation units 1100, 1300. The separation unit 1100 in fig. 7 can be obtained by separating, for example, the carrier substrate 200 of the second embodiment. Similarly, the separation unit 1300 in fig. 8 can be obtained by separating, for example, the carrier substrate 300 of the third embodiment.

Three-dimensional NAND memory die 1200 may refer to a three-dimensional stacked NAND memory die. For example, the memory die 1200 may include multiple memory dies stacked one on top of the other. The three-dimensionally stacked NAND memory in the drawings is merely exemplary, and other three-dimensionally stacked semiconductor devices are also possible. The memory 1200 and the separation units 1100 and 1300 may be connected by adhesion, welding, and the like, which are not described in detail herein.

As shown in the top view of fig. 7, after the plurality of through holes of the carrier substrate are broken, the size of the arc boundary formed may be smaller than the interval between the edge of the memory 1200 and the edge of the separation unit 1100. The above-described spacing formed with the through holes is smaller compared to mechanical dicing alone, thereby facilitating a significant reduction in the size of the package and thus the footprint area of the three-dimensional NAND memory.

Similarly, as shown in the top view of fig. 8, after the additional through-holes and the through-holes at the vertices in the second embodiment of the carrier substrate 300 are broken, the size of the arc boundary formed may be smaller than the interval between the edge of the memory 1200 and the edge of the separation unit 1300. In addition, the size of the vias of fig. 8 may be chosen to be smaller than the size of the vias of fig. 7, because the shorter distance between the vias in fig. 8 makes them more prone to breakage under the action of the separation module. Thus, the memory device 1000 of FIG. 8 facilitates further reduction in the size of the package, thereby reducing the footprint area of the three-dimensional NAND memory, as compared to the memory device 1000 shown in FIG. 7.

The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.

It is noted that the description in this application is merely an illustrative example and is not intended to require or imply that the steps of the various embodiments must be performed in the order presented, and that certain steps may be performed in parallel, independently of each other, or in other suitable orders. Additionally, words such as "next," "then," "next," etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods.

The block diagrams of devices, apparatuses, systems referred to in this application are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. It should also be noted that in the apparatus and devices of the present application, the components may be disassembled and/or reassembled. These decompositions and/or recombinations are to be considered as equivalents of the present application.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.

Claims (10)

1. A carrier substrate is characterized by comprising

A body having a first surface and a second surface opposite the first surface, and a plurality of side surfaces surrounding the first and second surfaces;

a plurality of through holes vertically extending from the first surface to the second surface, arranged in an array on a body, thereby dividing the body into a plurality of cells arranged in an array; and

a plurality of recesses arranged in the plurality of side surfaces and each recessed inward from a side surface of the body.

2. The carrier substrate of claim 1, wherein each of the plurality of cells is for a substrate of a separate chip.

3. The carrier substrate of claim 2, wherein the plurality of notches correspond to rows and columns, respectively, of the array of the plurality of vias.

4. The carrier substrate of claim 3, wherein the plurality of vias further comprises one or more additional vias disposed equidistantly on at least one side of the cells, further separating the plurality of cells.

5. The carrier substrate of claim 1, 2 or 4 wherein the plurality of through holes are substantially identical in shape and size.

6. The carrier substrate of claim 1, wherein the cross-sectional shape of the through-hole is selected from one of: circular, polygonal, and polygonal.

7. The carrier substrate of claim 1, wherein the cross-sectional shape of the recess is selected from one of: triangle, U-shape, trapezoid, drop shape and trapezoid-like with two narrowed sides.

8. The carrier substrate of claim 1, wherein the size of the through-hole is less than 80 μ ι η.

9. A separation apparatus characterized by being configured to separate the carrier substrate of any one of claims 1 to 8, the separation apparatus comprising:

a mechanical cutting module configured to partially mechanically cut a plurality of notches in the carrier substrate; and

a separation module configured to break the carrier substrate in a direction of a row or a column of the through holes of the carrier substrate by changing a temperature of the carrier substrate or applying vibration to the carrier substrate, thereby forming a plurality of separation units.

10. A memory device comprising a singulated unit formed by separating the carrier substrate of any of claims 1-8, and NAND memory die disposed on the singulated unit.

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