CN216146315U - Isolation device - Google Patents

Abstract

The utility model discloses an isolating device which comprises a processor and a plurality of isolating circuits with enabling ends, wherein the processor can output enabling signals based on the setting of a user, so that information interaction is carried out between the isolating circuits receiving the enabling signals and a rear-stage controlled module, and the isolating circuits not receiving the enabling signals cannot realize the information interaction. It can be seen that, this application can control the isolating circuit through exporting enabling signal to make the treater only carry out the information interaction with the back level controlled module that the isolating circuit that receives enabling signal corresponds, and the back level controlled module that the isolating circuit that does not receive enabling signal corresponds can not receive the information that the treater sent, also can not send information to the treater, also can not lead to the data confusion, satisfies user's demand.

Description

Isolation device

Technical Field

The utility model relates to the technical field of power electronics, in particular to an isolating device.

Background

In the prior art, a processor generally needs to communicate with a rear-stage controlled module, so that the processor can control the rear-stage controlled module to execute certain tasks, and process information output after the rear-stage controlled module executes the tasks, in order to avoid the influence of the processor on the normal work of the rear-stage controlled module when the processor fails and outputs a large voltage, and in order to avoid information interaction between rear-stage controlled modules when the number of the rear-stage controlled modules is large, isolating devices are arranged between the processor and the rear-stage controlled modules, and each isolating device is connected to the same information interaction end of the processor. However, when the processor only needs to perform information interaction with one rear-stage controlled module, other isolation devices can also send signals output by the processor to the rear-stage controlled module connected to the processor, and also send signals output by the rear-stage controlled module connected to the processor, so that the processor performs information interaction with other rear-stage controlled modules at the same time, and finally data in the processor is mistaken.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide an isolating device which can control an isolating circuit by outputting an enabling signal, so that a processor only carries out information interaction with a rear-stage controlled module corresponding to the isolating circuit which receives the enabling signal, and the rear-stage controlled module corresponding to the isolating circuit which does not receive the enabling signal does not receive information sent by the processor and send the information to the processor, namely, the data confusion is not caused, and the requirements of users are met.

In order to solve the above technical problem, the present invention provides an isolation device, comprising:

the processor is used for carrying out information interaction with each rear-stage controlled module and outputting an enabling signal according to the setting of a user;

the first information interaction end is connected with the information interaction end of the processor, the second information interaction ends are respectively connected with the rear-stage controlled modules in a one-to-one correspondence mode, the enabling ends are respectively connected with the enabling signal output ends of the processor in a one-to-one correspondence mode, the isolating circuits are used for conducting circuits between the processor and the rear-stage controlled modules connected with the processor when the enabling signals are received, so that the processor and the rear-stage controlled modules connected with the processor are subjected to information interaction, the processor and the rear-stage controlled modules connected with the processor are isolated, and the rear-stage controlled modules are isolated.

Preferably, the information interaction end of the processor is a Serial Peripheral Interface (SPI);

the SPI comprises a chip selection signal output end, a clock signal output end, a data output end and a data input end;

the first input end of each isolation circuit is connected with a chip selection signal output end of the processor, the second input end of each isolation circuit is connected with a clock signal output end of the processor, the third input end of each isolation circuit is connected with a data output end of the processor, the fourth input end of each isolation circuit is connected with a data output end of the rear-stage controlled module, the first output end of each isolation circuit is connected with a chip selection input end of the rear-stage controlled module, the second output end of each isolation circuit is connected with a clock signal input end of the rear-stage controlled module, the third output end of each isolation circuit is connected with a data input end of the rear-stage controlled module, and the fourth output end of each isolation circuit is connected with a data input end of the processor;

the enabling ends of the isolation circuits are respectively connected with enabling signal output ends of the processors in a one-to-one correspondence mode, and are specifically used for sending chip selection signals, clock signals and first data information output by the processors to the rear-stage controlled modules connected with the processors when the enabling signals are received, sending second data information output by the rear-stage controlled modules connected with the processors to the processors, isolating the processors and the rear-stage controlled modules connected with the processors, and isolating the rear-stage controlled modules.

Preferably, the rear-stage controlled module is provided with a reset signal input end;

the isolation circuit comprises a three-in one-out isolation chip and a two-in zero-out isolation chip;

the first input end of the three-in one-out isolation chip is a first input end of the isolation circuit, the second input end of the three-in one-out isolation chip is a second input end of the isolation circuit, the third input end of the three-in one-out isolation chip is connected with the reset signal output end of the processor, the fourth input end of the three-in one-out isolation chip is a fourth input end of the isolation circuit, the first output end of the three-in one-out isolation chip is a first output end of the isolation circuit, the second output end of the three-in one-out isolation chip is a second output end of the isolation circuit, the third output end of the three-in one-out isolation chip is connected with the reset signal input end of the rear-stage controlled module, the fourth output end of the three-in one-out isolation chip is a fourth output end of the isolation circuit, the first enable end of the three-in one-out isolation chip is connected with the enable signal output end of the processor, the fourth output end of the three-in one-out isolation chip is controlled to normally output when the enable signal is received, the second data information output by the rear-stage controlled module connected with the processor is sent to the processor; the second enabling end is connected with the second output end of the two-in zero-out isolation chip and used for controlling the first output end, the second output end and the third output end of the three-in one-out isolation chip to normally output when the enabling signal is received so as to send the chip selection signal, the clock signal and the reset signal to the rear-stage controlled module connected with the second enabling end, isolate the processor from the rear-stage controlled module connected with the second enabling end and isolate the rear-stage controlled modules;

the first input end of the two-in zero-out isolation chip is a third input end of the isolation circuit, the second input end of the two-in zero-out isolation chip is connected with an enabling signal output end of the processor, the first output end of the two-in zero-out isolation chip is a third output end of the isolation circuit and is used for sending first data information output by the processor to the rear-stage controlled module connected with the first input end of the two-in zero-out isolation chip, sending the enabling signal to the second enabling end of the three-in one-out isolation chip, isolating the processor from the rear-stage controlled module connected with the processor, and isolating the rear-stage controlled modules;

the processor is specifically configured to send the chip selection signal, the clock signal, and the first data information, output the enable signal according to a setting of a user, and read the second data information sent by the rear-stage controlled module;

the processor is further configured to send a reset signal, so that the subsequent controlled module receiving the reset signal sends the second data information to the processor based on the chip selection signal, the clock signal, and the first data information sent by the processor.

Preferably, the rear-stage controlled module is provided with a data ready signal output end;

the isolation circuit comprises a two-in two-out isolation chip and a two-in zero-out isolation chip;

the first input end of the two-in and two-out isolation chip is the first input end of the isolation circuit, the second input end is the second input end of the isolation circuit, the third input end is connected with the data ready signal output end of the rear-stage controlled module connected with the first input end and the fourth input end is the fourth input end of the isolation circuit, the first output end is the first output end of the isolation circuit, the second output end is the second output end of the isolation circuit, the third output end is connected with the data ready signal input end of the processor, the fourth output end is the fourth output end of the isolation circuit, the first enabling end is connected with the enabling signal output end of the processor, the first output end and the second output end of the two-in two-out isolation chip are controlled to normally output when the enable signal is received, the chip selection signal and the clock signal are sent to the rear-stage controlled module connected with the chip selection signal and the clock signal; the second enabling end is connected with the second output end of the two-in zero-out isolation chip and used for controlling a third output end and a fourth output end to normally output when the enabling signal is received, so that the data ready signal and second data information output by the rear-stage controlled module connected with the second enabling end are sent to the processor, the processor and the rear-stage controlled module connected with the second enabling end are isolated, and all the rear-stage controlled modules are isolated;

the first input end of the two-in zero-out isolation chip is a third input end of the isolation circuit, the second input end of the two-in zero-out isolation chip is connected with an enabling signal output end of the processor, the first output end of the two-in zero-out isolation chip is a third output end of the isolation circuit and is used for sending first data information output by the processor to the rear-stage controlled module connected with the first input end of the two-in zero-out isolation chip, sending the enabling signal to the second enabling end of the three-in one-out isolation chip, isolating the processor from the rear-stage controlled module connected with the processor, and isolating the rear-stage controlled modules;

the processor is specifically configured to send the chip selection signal, the clock signal, and the first data information, output the enable signal according to a setting of a user, and read the second data information sent by the rear-stage controlled module that sends the data ready signal when receiving the data ready signal.

Preferably, the method further comprises the following steps:

the first end of the resistor is connected with a power supply, and the second end of the resistor is connected with the power supply input end of each isolation circuit in a one-to-one correspondence manner and is used for limiting current;

the first end of the capacitor is connected with the second end of the resistor, and the second end of the capacitor is connected with the grounding ends of the isolation circuits in a one-to-one correspondence mode and is grounded.

Preferably, the capacitor includes:

the first end is the first end of the capacitor, and the second end is the first capacitor of the second end of the capacitor and is used for high-frequency filtering;

the first end is the first end of the capacitor, and the second end is the second capacitor of the second end of the capacitor and is used for low-frequency filtering;

the capacitance value of the first capacitor is smaller than that of the second capacitor.

Preferably, the method further comprises the following steps:

the control end is connected with the control signal output end of the processor, the enable signal input end is connected with the enable signal output end of the processor, and each enable signal output end corresponds to the analog switch connected with the enable end of each isolation circuit one by one respectively and is used for sending the enable signal to the isolation circuit corresponding to the control signal based on the control signal sent by the processor;

the processor is also used for outputting the control signal according to the setting of a user.

The application provides an isolating device, including treater and a plurality of isolator that have the enable end, the treater can export the enable signal based on user's settlement to carry out the information interaction through isolator and the back level controlled module who receives the enable signal, the isolator that does not receive the enable signal can't realize the interaction of information. It can be seen that, this application can control the isolating circuit through exporting enabling signal to make the treater only carry out the information interaction with the back level controlled module that the isolating circuit that receives enabling signal corresponds, and the back level controlled module that the isolating circuit that does not receive enabling signal corresponds can not receive the information that the treater sent, also can not send information to the treater, also can not lead to the data confusion, satisfies user's demand.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an isolation device according to the present invention;

FIG. 2 is a schematic diagram of a processor and its port structure according to the present invention;

FIG. 3 is a schematic diagram of a three-in one-out isolation chip and its ports according to the present invention;

FIG. 4 is a schematic structural diagram of a two-in zero-out isolation chip and its ports according to the present invention;

fig. 5 is a schematic structural diagram of a rear-stage controlled module and a port thereof according to the present invention;

fig. 6 is a schematic structural diagram of a three-in one-out isolation chip according to the present invention;

fig. 7 is a schematic structural diagram of a two-in zero-out isolation chip according to the present invention.

Detailed Description

The core of the utility model is to provide an isolating device, which can control an isolating circuit by outputting an enabling signal, so that a processor only performs information interaction with a rear-stage controlled module corresponding to the isolating circuit which receives the enabling signal, and the rear-stage controlled module corresponding to the isolating circuit which does not receive the enabling signal does not receive information sent by the processor and send information to the processor, namely, data confusion is not caused, and the requirements of users are met.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an isolation device provided in the present invention, the isolation device includes:

the processor 1 is used for carrying out information interaction with each rear-stage controlled module and outputting an enabling signal according to the setting of a user;

the first information interaction end is connected with the information interaction end of the processor 1, the second information interaction ends are respectively connected with the rear-stage controlled modules in a one-to-one correspondence mode, the enabling ends are respectively connected with the enabling signal output ends of the processor 1 in a one-to-one correspondence mode, the isolating circuits 2 are used for conducting circuits between the processor 1 and the rear-stage controlled modules connected with the processor 1 when enabling signals are received, information interaction is conducted between the processor 1 and the rear-stage controlled modules connected with the processor 1, the processor 1 and the rear-stage controlled modules connected with the processor are isolated, and isolation is conducted between the rear-stage controlled modules.

In this embodiment, in order to avoid interference between signals of each rear-stage controlled module and avoid that the processor 1 fails, a large voltage is input into the rear-stage controlled module, which causes the rear-stage controlled module to also fail, an isolation circuit 2 is respectively arranged between the processor 1 and each rear-stage controlled module, a first information interaction end of each isolation circuit 2 is connected with the same information interaction end of the processor 1, and information interaction is performed between the processor 1 and each rear-stage controlled module through the corresponding isolation circuit 2. And the enable terminals of the isolation circuits 2 are respectively connected with the enable signal output ends of the processor 1 in a one-to-one correspondence manner, so that the processor 1 can control the isolation circuits 2 based on the setting of a user, for example, when the setting of the user is that the processor 1 sequentially outputs enable signals through the enable signal output ends of the processor according to a preset sequence and a preset frequency, the processor 1 can sequentially perform information interaction with the controlled modules at the rear stages according to the preset sequence and the preset frequency, and the condition of disordered control over the isolation circuits 2 is avoided.

It can be seen that, the processor 1 in the present application can output the enable signal through the corresponding enable signal output end according to the setting of the user, so that the processor 1 and the rear-stage controlled module corresponding to the isolation circuit 2 that receives the enable signal can perform information interaction, and the processor 1 cannot perform information interaction with the rear-stage controlled module corresponding to the isolation circuit 2 that does not receive the enable signal, and the rear-stage controlled module corresponding to the isolation circuit 2 that does not receive the enable signal cannot send information to the processor 1, so that data errors of the processor 1 cannot be caused, and normal operation of the entire system is ensured.

Specifically, the processor 1 may send an enable signal to the isolation circuit 2 connected to the first rear-stage controlled module set by the user according to the setting of the user, and after receiving the data information sent by the first rear-stage controlled module, send an enable signal to the isolation circuit 2 connected to the second rear-stage controlled module set by the user, and so on.

The processor 1 may be, but is not limited to, an MCU (micro controller Unit), which is not limited in this application.

For example, the subsequent controlled module may be a detection device, and when the processor 1 performs information interaction with the detection device, the detection device may detect the device under test, so as to send the detection data to the processor 1.

To sum up, this application can control isolating circuit 2 through exporting enabling signal to make treater 1 only carry out the information interaction with the rear stage controlled module that isolating circuit 2 received enabling signal corresponds, and the rear stage controlled module that isolating circuit 2 that has not received enabling signal corresponds can not receive the information that treater 1 sent, also can not send information to treater 1, also can not lead to the data confusion, satisfies user's demand.

On the basis of the above-described embodiment:

as a preferred embodiment, the information interaction end of the processor 1 is an SPI (Serial Peripheral Interface);

the SPI comprises a chip selection signal output end, a clock signal output end, a data output end and a data input end;

the first input end of each isolation circuit 2 is connected with the chip selection signal output end of the processor 1, the second input end is connected with the clock signal output end of the processor 1, the third input end is connected with the data output end of the processor 1, the fourth input end is connected with the data output end of the rear-stage controlled module, the first output end is connected with the chip selection input end of the rear-stage controlled module, the second output end is connected with the clock signal input end of the rear-stage controlled module, the third output end is connected with the data input end of the rear-stage controlled module, and the fourth output end is connected with the data input end of the processor 1;

the enabling ends of the isolating circuits 2 are respectively connected with the enabling signal output ends of the processors 1 in a one-to-one correspondence manner, and are specifically used for sending chip selection signals, clock signals and first data information output by the processors 1 to the rear-stage controlled modules connected with the processors when the enabling signals are received, sending second data information output by the rear-stage controlled modules connected with the processors to the processors 1, isolating the processors 1 and the rear-stage controlled modules connected with the processors, and isolating the rear-stage controlled modules.

In this embodiment, the information interaction terminal of the processor 1 is an SPI, which is one of the most widely used interfaces between a microcontroller and a peripheral IC (Integrated Circuit) (e.g., a sensor, an ADC (Analog-to-Digital Converter), a DAC (Digital-to-Analog Converter), a shift register, and an SRAM (Static Random-Access Memory), and the SPI includes a chip select signal output terminal, i.e., an SPI _ SS, a clock signal output terminal, i.e., an SPI _ SCLK, a data output terminal, i.e., an SPI _ MISO, and a data input terminal, i.e., an SPI _ MOSI. SPI _ SS, SPI _ SCLK and SPI _ MISO are the ports that processor 1 outputs signals to the controlled module of the back level, SPI _ MOSI is the ports that the controlled module of the back level inputs signals to processor 1, and processor 1 carries out information interaction with the controlled module of the back level corresponding to isolation circuit 2 that receives the enabling signal through the above-mentioned ports.

Of course, the information interaction end of the processor 1 in this application is not limited to the SPI, and it is sufficient to implement corresponding information interaction, but it should be noted that no matter which information interaction end is used, each information interaction end needs to be isolated, and accordingly, the isolation circuit 2 also needs to be adjusted along with the change of the first information interaction end.

As a preferred embodiment, the rear-stage controlled module is provided with a reset signal input end;

the isolation circuit 2 comprises a three-in one-out isolation chip U1 and a two-in zero-out isolation chip U2;

the first input end of the three-in one-out isolation chip U1 is a first input end of the isolation circuit 2, the second input end is a second input end of the isolation circuit 2, the third input end is connected with the reset signal output end of the processor 1, the fourth input end is a fourth input end of the isolation circuit 2, the first output end is a first output end of the isolation circuit 2, the second output end is a second output end of the isolation circuit 2, the third output end is connected with the reset signal input end of the rear-stage controlled module, the fourth output end is a fourth output end of the isolation circuit 2, the first enable end is connected with the enable signal output end of the processor 1, and the three-in one-out isolation chip U1 is controlled to normally output when receiving an enable signal, so that second data information output by the rear-stage controlled module connected with the three-in one-out isolation chip U1 is sent to the processor 1; the second enabling end is connected with the second output end of the two-in zero-out isolation chip U2 and is used for controlling the first output end, the second output end and the third output end of the three-in one-out isolation chip U1 to normally output when an enabling signal is received, so that a chip selection signal, a clock signal and a reset signal are sent to a rear-stage controlled module connected with the second enabling end, the processor 1 and the rear-stage controlled module connected with the second enabling end are isolated, and all the rear-stage controlled modules are isolated;

the first input end of the two-in zero-out isolation chip U2 is a third input end of the isolation circuit 2, the second input end is connected with an enable signal output end of the processor 1, the first output end is a third output end of the isolation circuit 2 and is used for sending first data information output by the processor 1 to a rear-stage controlled module connected with the first input end and sending an enable signal to a second enable end of the three-in one-out isolation chip U1, the processor 1 is isolated from the rear-stage controlled module connected with the first input end and each rear-stage controlled module is isolated from each other;

the processor 1 is specifically configured to send a chip selection signal, a clock signal and first data information, and read second data information sent by a rear-stage controlled module according to a set output enable signal of a user;

the processor 1 is further configured to send a reset signal, so that the subsequent controlled module receiving the reset signal sends the second data information to the processor 1 based on the chip select signal, the clock signal and the first data information sent by the processor 1.

The applicant considers that information interaction with the processor 1 is performed only when a reset signal is input to the rear-stage controlled module, therefore, the isolation circuit 2 in the present application needs to have three input terminals connected to the processor 1, that is, connected to the chip selection signal output terminal, the clock signal output terminal, the data output terminal and the reset signal output terminal of the processor 1, so as to send the signals to the rear-stage controlled module connected to the isolation circuit 2, and the isolation circuit 2 needs to further have an input terminal connected to the data output terminal of the rear-stage controlled module connected to the isolation circuit, so as to send the second data information output by the rear-stage controlled module to the processor 1.

Referring to fig. 2, fig. 3, fig. 4 and fig. 5, fig. 2 is a schematic diagram of a processor and a port thereof provided by the present invention, fig. 3 is a schematic diagram of a three-in one-out isolation chip and a port thereof provided by the present invention, fig. 4 is a schematic diagram of a two-in zero-out isolation chip and a port thereof provided by the present invention, and fig. 5 is a schematic diagram of a rear-stage controlled module and a port thereof provided by the present invention. The ports of the processor 1 connected to the three-in and three-out isolation chip include SPI _ SS, SPI _ SCLK, RESET, SPI _ MISO, and EN 1-1 to EN 1-N, where EN 1-1 to EN 1-N are enable signal output terminals of the processor 1. Fig. 3 is a schematic port diagram of one of the three-in one-out isolation chips U1, fig. 4 is a schematic port diagram of one of the two-in zero-out isolation chips U2, SPI1_ SS, SPI1_ SCLK, RESET1 and SPI1_ MISO in fig. 3 are ports connected to the rear-stage controlled module, EN 2-1 is a port connected between the two-in zero-out isolation chip U2 and the three-in one-out isolation chip U1 and used for transmitting an enable signal, and SPI1_ MOSI in fig. 4 is a port connected between the two-in zero-out isolation chip U2 and the rear-stage controlled module. In the figure, INA is a first input terminal, INB is a second input terminal, INC is a third input terminal, IND is a fourth output terminal, OUTA is a first output terminal, OUTB is a second output terminal, OUTC is a third output terminal, OUTD is a fourth output terminal, VDD1 and VDD2 are power supply terminals, and GND1 and GND2 are ground terminals.

Referring to fig. 6 and 7, fig. 6 is a schematic structural diagram of a three-in one-out isolation chip provided by the present invention, and fig. 7 is a schematic structural diagram of a two-in zero-out isolation chip provided by the present invention.

Based on this, the isolation circuit 2 in this application includes a three-in one-out isolation chip U1 and a two-in zero-out isolation chip U2, wherein the three-in one-out isolation chip U1 includes two enable terminals, the first enable terminal is directly connected to the enable signal output terminal of the processor 1, the second enable terminal is connected to the enable signal output terminal of the processor 1 through the two-in zero-out isolation chip U2, and the first enable terminal and the second enable terminal are connected to the same enable signal output terminal of the processor 1, the first enable terminal can control the fourth output terminal of the three-in one-out isolation chip U1, the second enable terminal can control the first output terminal, the second output terminal and the third output terminal of the three-in one-out isolation chip U1, when the first enable terminal of the three-in one-out isolation chip U1 receives an enable signal, the fourth output terminal of the three-in one-out isolation chip U1 can normally output, and the second enable terminal of the three-in one-out isolation chip U1 can receive an enable signal, the first output end, the second output end and the third output end of the three-in one-out isolation chip U1 can output normally, and the processor 1 can perform information interaction with the rear-stage controlled module connected with the isolation circuit 2.

However, the two-in zero-out isolation chip U2 does not have an enable end, and the applicant considers that the rear-stage controlled module does not receive the chip select signal sent by the SPI _ SS port of the processor 1 and the clock signal output by the SPI _ SCLK port, but does not affect the normal operation of the rear-stage controlled module when receiving the SPI _ MOSI. If the slave module in the next stage receives a signal output from any one of the two ports SPI _ SS and SPI _ SCLK, but does not receive other signals, the normal operation of the slave module in the next stage may be affected, and therefore, the input terminal of the two-input zero-output isolation chip U2 is connected to the SPI _ MOSI port of the processor 1 and the enable signal output terminal of the processor 1.

It should be noted that, in the present application, when the three-in one-out isolation chip U1 is connected to the processor 1, three input terminals are connected to the output terminal of the processor 1, and one output terminal is connected to the input terminal of the processor 1, that is, the three-in one-out isolation chip U1; the two-in zero-out isolation chip U2 has two input terminals connected to the output terminal of the processor 1 when connected to the processor 1, and zero output terminals connected to the input terminal of the processor 1, that is, the two-in zero-out isolation chip U2.

As a preferred embodiment, the rear-stage controlled module is provided with a data ready signal output end;

the isolation circuit 2 comprises a two-in two-out isolation chip and a two-in zero-out isolation chip U2;

the first input end of the two-in and two-out isolation chip is the first input end of the isolation circuit 2, the second input end is the second input end of the isolation circuit 2, the third input end is connected with the data ready signal output end of the rear-stage controlled module connected with the first input end and the fourth input end is the fourth input end of the isolation circuit 2, the first output end is the first output end of the isolation circuit 2, the second output end is the second output end of the isolation circuit 2, the third output end is connected with the data ready signal input end of the processor 1, the fourth output end is the fourth output end of the isolation circuit 2, the first enable end is connected with the enable signal output end of the processor 1, the first output end and the second output end of the two-in two-out isolation chip are controlled to normally output when the enable signal is received, so that a chip selection signal and a clock signal are sent to a rear-stage controlled module connected with the chip selection signal and the clock signal; the second enabling end is connected with the second output end of the two-in zero-out isolation chip U2 and is used for controlling the third output end and the fourth output end to normally output when receiving an enabling signal so as to send a data ready signal and second data information output by a rear-stage controlled module connected with the second enabling end and the fourth output end to the processor 1, isolate the processor 1 from the rear-stage controlled module connected with the second enabling end and isolate all rear-stage controlled modules;

the first input end of the two-in zero-out isolation chip U2 is a third input end of the isolation circuit 2, the second input end is connected with an enable signal output end of the processor 1, the first output end is a third output end of the isolation circuit 2 and is used for sending first data information output by the processor 1 to a rear-stage controlled module connected with the first input end and sending an enable signal to a second enable end of the three-in one-out isolation chip U1, the processor 1 is isolated from the rear-stage controlled module connected with the first input end and each rear-stage controlled module is isolated from each other;

the processor 1 is specifically configured to send a chip select signal, a clock signal, and first data information, output an enable signal according to a setting of a user, and read second data information sent by a subsequent controlled module that sends a data ready signal when receiving the data ready signal.

The applicant considers that when the data of the rear-stage controlled module is ready, a data ready signal is output, and when the data is ready, the data is normally interacted with the processor 1, therefore, the isolation circuit 2 in the present application needs to have three input ends connected to the processor 1, namely, a chip selection signal output end, a clock signal output end, a data output end and a reset signal output end of the processor 1, so as to send the signals to the rear-stage controlled module connected to the isolation circuit 2, and the isolation circuit 2 also needs to have two input ends connected to the data output end and the data ready pin of the rear-stage controlled module connected to the isolation circuit 2, so as to send the second data information and the data ready signal output by the rear-stage controlled module to the processor 1.

Based on this, the isolation circuit 2 in this application includes a two-in two-out isolation chip and a two-in zero-out isolation chip U2, wherein the two-in two-out isolation chip includes two enable terminals, the first enable terminal is directly connected to the enable signal output terminal of the processor 1, the second enable terminal is connected to the enable signal output terminal of the processor 1 through the two-in zero-out isolation chip U2, and the first enable terminal and the second enable terminal are connected to the same enable signal output terminal of the processor 1, the first enable terminal can control the first output terminal and the second output terminal of the two-in two-out isolation chip, the second enable terminal can control the third output terminal and the fourth output terminal of the two-in two-out isolation chip, when the first enable terminal of the two-in two-out isolation chip receives the enable signal, the first output terminal and the second output terminal of the two-in two-out isolation chip normally output, the second enable terminal of the two-in two-out isolation chip can receive the enable signal, the third output end and the fourth output end of the two-in two-out isolation chip can normally output, the processor 1 can perform information interaction with a rear-stage controlled module connected with the isolation circuit 2, and in addition, when the processor 1 receives a data ready signal sent by the rear-stage controlled module, the processor 1 can receive second data information sent by the rear-stage controlled module sending the data ready signal.

However, the two-in zero-out isolation chip U2 does not have an enable end, and the applicant considers that the rear-stage controlled module does not receive the chip select signal sent by the SPI _ SS port of the processor 1 and the clock signal output by the SPI _ SCLK port, but does not affect the normal operation of the rear-stage controlled module when receiving the SPI _ MOSI. If the slave module in the next stage receives a signal output from any one of the two ports SPI _ SS and SPI _ SCLK, but does not receive other signals, the normal operation of the slave module in the next stage may be affected, and therefore, the input terminal of the two-input zero-output isolation chip U2 is connected to the SPI _ MOSI port of the processor 1 and the enable signal output terminal of the processor 1.

It should be noted that, in the present application, when the two-in two-out isolation chip is connected to the processor 1, two input ends are connected to the output end of the processor 1, and two output ends are connected to the input end of the processor 1, which is the two-in two-out isolation chip; the two-in zero-out isolation chip U2 has two input terminals connected to the output terminal of the processor 1 when connected to the processor 1, and zero output terminals connected to the input terminal of the processor 1, that is, the two-in zero-out isolation chip U2.

As a preferred embodiment, the method further comprises the following steps:

the first end of the resistor is connected with a power supply, and the second end of the resistor is connected with the power supply input end of each isolation circuit 2 in a one-to-one correspondence manner and is used for limiting current;

the first end is connected with the second end of the resistor, and the second end is connected with a plurality of capacitors which are connected with the grounding ends of the isolation circuits 2 in a one-to-one correspondence mode and are grounded, and the capacitors are used for filtering and storing energy.

In this embodiment, the current limiting resistor is provided to limit the flow of the current input to the isolation circuit 2, and the capacitor capable of filtering and storing energy is provided to ensure the normal operation of the isolation circuit 2.

Referring to fig. 3 and 4, capacitors C1, C2, C3, C4, C5, C6, C7 and C8 and resistors R1, R2, R3 and R4 are shown, wherein the capacitance values of C1, C3, C5 and C7 in the figure may be but are not limited to 1 μ F, the capacitance values of C2, C4, C6 and C8 may be but are not limited to 100nF, and the resistance values of R1, R2, R3 and R4 may be but are not limited to 100 Ω. The voltage value of the power supply may be, but is not limited to, 3.3V.

As a preferred embodiment, the capacitor comprises:

the first end is the first end of the capacitor, and the second end is the first capacitor of the second end of the capacitor, and the first capacitor is used for high-frequency filtering;

the first end is the first end of the capacitor, and the second end is the second capacitor of the second end of the capacitor, and is used for low-frequency filtering;

the capacitance value of the first capacitor is smaller than that of the second capacitor.

Specifically, the capacitor includes a first capacitor and a second capacitor, which can perform high-frequency filtering and low-frequency filtering, so as to further ensure the normal operation of the isolation circuit 2.

As a preferred embodiment, the method further comprises the following steps:

the control end is connected with the control signal output end of the processor 1, the enable signal input end is connected with the enable signal output end of the processor 1, and the enable signal output ends respectively correspond to the analog switches connected with the enable ends of the isolation circuits 2 one by one and are used for sending the enable signals to the isolation circuits 2 corresponding to the control signals based on the control signals sent by the processor 1;

the processor 1 is also arranged to output a control signal in accordance with a user setting.

In order to solve the above technical problem, the applicant considers that when the number of the controlled modules in the subsequent stage is larger, the processor 1 needs more enable signal output terminals, but the processor 1 may not be provided with a larger number of enable signal output terminals, and in the present application, an analog switch is provided, and the processor 1 outputs a control signal, so as to control the analog switch to send an enable signal to the isolation circuit 2 corresponding to the control signal.

Specifically, the processor 1 only needs to be provided with a signal interaction terminal, an enable signal output terminal and a control signal output terminal to be connected with the analog switch. For example, the number of the control signal output terminals of the processor 1 may be four, and the decimal signals 0 to 15, that is, 16 signals may be output by outputting the digital signals 0000 to 1111, that is, the processor 1 may control 16 isolation circuits 2 by four control signal output terminals and one enable signal output terminal; the control signal output terminals of the processor 1 may also be set to five, and the decimal signals 0 to 31, that is, 32 numbers, may be corresponded by outputting the digital signals 00000 to 11111, that is, the processor 1 may control 32 isolation circuits 2 by five control signal output terminals and one enable signal output terminal. By analogy, the number of controllable isolation circuits 2 increases exponentially every time a control signal output is added to the processor 1, reducing the need for the number of pins of the processor 1.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. An isolation device, comprising:

the processor is used for carrying out information interaction with each rear-stage controlled module and outputting an enabling signal according to the setting of a user;

the first information interaction end is connected with the information interaction end of the processor, the second information interaction end is respectively connected with the rear-stage controlled modules in a one-to-one correspondence mode, the enabling ends are respectively connected with the enabling signal output ends of the processor in a one-to-one correspondence mode, and the isolating circuits are used for conducting circuits between the processor and the rear-stage controlled modules connected with the processor when the enabling signals are received, so that the processor and the rear-stage controlled modules connected with the processor are subjected to information interaction, isolating the processor and the rear-stage controlled modules connected with the processor, and isolating the rear-stage controlled modules.

2. The isolation device of claim 1, wherein the information interaction end of the processor is a Serial Peripheral Interface (SPI);

the SPI comprises a chip selection signal output end, a clock signal output end, a data output end and a data input end;

the first input end of each isolation circuit is connected with a chip selection signal output end of the processor, the second input end of each isolation circuit is connected with a clock signal output end of the processor, the third input end of each isolation circuit is connected with a data output end of the processor, the fourth input end of each isolation circuit is connected with a data output end of the rear-stage controlled module, the first output end of each isolation circuit is connected with a chip selection input end of the rear-stage controlled module, the second output end of each isolation circuit is connected with a clock signal input end of the rear-stage controlled module, the third output end of each isolation circuit is connected with a data input end of the rear-stage controlled module, and the fourth output end of each isolation circuit is connected with a data input end of the processor;

the enabling ends of the isolation circuits are respectively connected with enabling signal output ends of the processors in a one-to-one correspondence mode, and are specifically used for sending chip selection signals, clock signals and first data information output by the processors to the rear-stage controlled modules connected with the processors when the enabling signals are received, sending second data information output by the rear-stage controlled modules connected with the processors to the processors, isolating the processors and the rear-stage controlled modules connected with the processors, and isolating the rear-stage controlled modules.

3. The isolation device of claim 2, wherein the rear stage controlled module is provided with a reset signal input terminal;

the isolation circuit comprises a three-in one-out isolation chip and a two-in zero-out isolation chip;

the first input end of the three-in one-out isolation chip is a first input end of the isolation circuit, the second input end of the three-in one-out isolation chip is a second input end of the isolation circuit, the third input end of the three-in one-out isolation chip is connected with the reset signal output end of the processor, the fourth input end of the three-in one-out isolation chip is a fourth input end of the isolation circuit, the first output end of the three-in one-out isolation chip is a first output end of the isolation circuit, the second output end of the three-in one-out isolation chip is a second output end of the isolation circuit, the third output end of the three-in one-out isolation chip is connected with the reset signal input end of the rear-stage controlled module, the fourth output end of the three-in one-out isolation chip is a fourth output end of the isolation circuit, the first enable end of the three-in one-out isolation chip is connected with the enable signal output end of the processor, the fourth output end of the three-in one-out isolation chip is controlled to normally output when the enable signal is received, the second data information output by the rear-stage controlled module connected with the processor is sent to the processor; the second enabling end is connected with the second output end of the two-in zero-out isolation chip and used for controlling the first output end, the second output end and the third output end of the three-in one-out isolation chip to normally output when the enabling signal is received so as to send the chip selection signal, the clock signal and the reset signal to the rear-stage controlled module connected with the second enabling end, isolate the processor from the rear-stage controlled module connected with the second enabling end and isolate the rear-stage controlled modules;

the first input end of the two-in zero-out isolation chip is a third input end of the isolation circuit, the second input end of the two-in zero-out isolation chip is connected with an enabling signal output end of the processor, the first output end of the two-in zero-out isolation chip is a third output end of the isolation circuit and is used for sending first data information output by the processor to the rear-stage controlled module connected with the first input end of the two-in zero-out isolation chip, sending the enabling signal to the second enabling end of the three-in one-out isolation chip, isolating the processor from the rear-stage controlled module connected with the processor, and isolating the rear-stage controlled modules;

the processor is specifically configured to send the chip selection signal, the clock signal, and the first data information, output the enable signal according to a setting of a user, and read the second data information sent by the rear-stage controlled module;

the processor is further configured to send a reset signal, so that the subsequent controlled module receiving the reset signal sends the second data information to the processor based on the chip selection signal, the clock signal, and the first data information sent by the processor.

4. The isolation device of claim 2, wherein the rear stage controlled module is provided with a data ready signal output;

the isolation circuit comprises a two-in two-out isolation chip and a two-in zero-out isolation chip;

the first input end of the two-in and two-out isolation chip is the first input end of the isolation circuit, the second input end is the second input end of the isolation circuit, the third input end is connected with the data ready signal output end of the rear-stage controlled module connected with the first input end and the fourth input end is the fourth input end of the isolation circuit, the first output end is the first output end of the isolation circuit, the second output end is the second output end of the isolation circuit, the third output end is connected with the data ready signal input end of the processor, the fourth output end is the fourth output end of the isolation circuit, the first enabling end is connected with the enabling signal output end of the processor, the first output end and the second output end of the two-in two-out isolation chip are controlled to normally output when the enable signal is received, the chip selection signal and the clock signal are sent to the rear-stage controlled module connected with the chip selection signal and the clock signal; the second enabling end is connected with the second output end of the two-in zero-out isolation chip and used for controlling a third output end and a fourth output end to normally output when the enabling signal is received, so that the data ready signal and second data information output by the rear-stage controlled module connected with the second enabling end are sent to the processor, the processor and the rear-stage controlled module connected with the second enabling end are isolated, and all the rear-stage controlled modules are isolated;

the first input end of the two-in zero-out isolation chip is a third input end of the isolation circuit, the second input end of the two-in zero-out isolation chip is connected with an enabling signal output end of the processor, the first output end of the two-in zero-out isolation chip is a third output end of the isolation circuit and is used for sending first data information output by the processor to the rear-stage controlled module connected with the first input end of the two-in zero-out isolation chip, sending the enabling signal to the second enabling end of the two-in two-out isolation chip, isolating the processor from the rear-stage controlled module connected with the processor, and isolating the rear-stage controlled modules;

the processor is specifically configured to send the chip selection signal, the clock signal, and the first data information, output the enable signal according to a setting of a user, and read the second data information sent by the rear-stage controlled module that sends the data ready signal when receiving the data ready signal.

5. The isolation device of claim 1, further comprising:

the first end of the resistor is connected with a power supply, and the second end of the resistor is connected with the power supply input end of each isolation circuit in a one-to-one correspondence manner and is used for limiting current;

the first end of the capacitor is connected with the second end of the resistor, and the second end of the capacitor is connected with the grounding ends of the isolation circuits in a one-to-one correspondence mode and is grounded.

6. The isolation device of claim 5, wherein the capacitance comprises:

the first end is the first end of the capacitor, and the second end is the first capacitor of the second end of the capacitor and is used for high-frequency filtering;

the first end is the first end of the capacitor, and the second end is the second capacitor of the second end of the capacitor and is used for low-frequency filtering;

the capacitance value of the first capacitor is smaller than that of the second capacitor.

7. The isolation device of any one of claims 1 to 6, further comprising:

the control end is connected with the control signal output end of the processor, the enable signal input end is connected with the enable signal output end of the processor, and each enable signal output end corresponds to the analog switch connected with the enable end of each isolation circuit one by one respectively and is used for sending the enable signal to the isolation circuit corresponding to the control signal based on the control signal sent by the processor;

the processor is also used for outputting the control signal according to the setting of a user.

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