CN216117897U - 一种集成电路制程布局可靠性的测试装置 - Google Patents
一种集成电路制程布局可靠性的测试装置 Download PDFInfo
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Effective date of registration: 20231218 Address after: 200120 building 3, No. 1558, Pingzhuang East Road, Lingang xinpian District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Shanghai Nuozhangqiang Technology Co.,Ltd. Patentee after: Liu Yingguo Patentee after: Chen Huacheng Address before: 518107 4th floor, building 18, shatouxiang Industrial Zone, Changzhen community, Yutang street, Guangming District, Shenzhen, Guangdong Patentee before: Shenzhen Huasi Ketai Electronics Co.,Ltd. |
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Effective date of registration: 20240307 Address after: No.26-1 Xiexin West Road, Liujiagang, Fuqiao Town, Taicang City, Suzhou City, Jiangsu Province, 215000 Patentee after: Zhuoxinjie (Suzhou) Semiconductor Materials Technology Co.,Ltd. Country or region after: China Address before: 200120 building 3, No. 1558, Pingzhuang East Road, Lingang xinpian District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee before: Shanghai Nuozhangqiang Technology Co.,Ltd. Country or region before: China Patentee before: Liu Yingguo Patentee before: Chen Huacheng |