CN216086654U - Optical module testing arrangement - Google Patents

Abstract

The utility model discloses an optical module testing device which comprises an upper computer, a main board and a sub-board, wherein the upper computer is provided with an interface a, the main board is provided with an FPGA main board and a connector, the FPGA main board is provided with an interface b and a serial transceiver, the interface a is connected with the interface b, the connector is connected with the serial transceiver, the sub-board is provided with an electric signal transceiving interface, a signal processing module and an optical fiber transceiving interface, the electric signal transceiving interface is connected with the connector, the electric signal transceiving interface is connected with the signal processing module, the signal processing module is connected with the optical fiber transceiving interface, the optical fiber transceiving interface is connected with an optical loop, and the optical fiber transceiving interface and the optical loop form an optical path loop. The utility model has the beneficial effects that: the frequency of the hardware disassembly and assembly of the test cable is reduced, and the test efficiency of the optical module is improved.

Description

Optical module testing arrangement

Technical Field

The utility model relates to the test of an optical module, in particular to an optical module testing device.

Background

In the prior art, one error code detector is required to be used for testing error codes, at least 4 high-speed coaxial cables are required, one end of each cable is connected with the error code detector, and the other end of each cable is connected with an optical module test board. The optical fiber transmitting ends are required to be respectively connected to the signal input interfaces of the oscillograph for testing the eye pattern. This solution has the following drawbacks:

1. testing one channel, namely, a pair of cables needs to be installed, testing 12 light emitting modules and 12 light receiving modules needs to be installed, 24 pairs of cables, namely 48 (secondary) cables need to be installed, and the installation of high-speed cables is time-consuming and labor-consuming;

2. the eye diagram of the sending end and the error code of the receiving end need to be operated and switched on different terminal devices, so that the efficiency is low;

3. the cost of error detectors and oscilloscopes is relatively high.

SUMMERY OF THE UTILITY MODEL

The utility model aims to overcome the defects of the prior art and provide an optical module testing device with high testing efficiency.

The purpose of the utility model is realized by the following technical scheme: the utility model provides an optical module testing arrangement, including the host computer, mainboard and daughter board, interface an has on the host computer, FPGA mainboard and connector have on the mainboard, interface b and serial transceiver have on the FPGA mainboard, interface a and interface b connect, the connector is connected with serial transceiver, the daughter board has signal of telecommunication receiving and dispatching interface, signal processing module and optic fibre receiving and dispatching interface, signal of telecommunication receiving and dispatching interface is connected with the connector, signal of telecommunication receiving and dispatching interface is connected with signal processing module, signal processing module and optic fibre receiving and dispatching interface are connected, optic fibre receiving and dispatching interface is connected with the light return circuit, and optic fibre receiving and dispatching interface and light return circuit form the light path and return circuit.

Optionally, the connector has multiple sets of electrical signal channels thereon.

Optionally, the signal channels of the connector are 12 groups.

Optionally, the interface a is a JTAG interface.

Optionally, interface b is a JTAG interface.

Optionally, the serial transceiver is a serial GTX transceiver interface.

The utility model has the following advantages: the optical module testing device reduces the frequency of the hardware disassembly and assembly of the testing cable and improves the testing efficiency of the optical module.

Drawings

FIG. 1 is a schematic structural view of the present invention;

in the figure, 1-an upper computer, 2-a main board, 3-a sub-board, 11-an interface a, 21-an FPGA main board, 22-a connector, 23-a serial transceiver, 24-an interface b, 31-an electric signal transceiving interface, 32-an optical fiber transceiving interface and 33-an optical loop.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

In addition, the embodiments of the present invention and the features of the embodiments may be combined with each other without conflict.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, or orientations or positional relationships that are conventionally placed when the products of the present invention are used, or orientations or positional relationships that are conventionally understood by those skilled in the art, and are used only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element that is referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

As shown in fig. 1, an optical module testing apparatus includes an upper computer 1, a main board 2 and a daughter board 3, in this embodiment, the upper computer 1, the daughter board 3 and the daughter board 3 are all existing devices, and may be implemented in one upper computer 1 device through commercially available activities, preferably, when the upper computer 1 is selected, the upper computer 1 having control and display functions is selected, so that error code and eye pattern testing may be implemented in one upper computer 1 device through the upper computer 1, in this embodiment, the upper computer 1 has an interface a11, preferably, the interface a11 is a JTAG interface, the main board 2 has an FPGA main board 21 and a connector 22, the FPGA main board 21 has an interface b24 and a serial transceiver 23, the interface a11 is connected with the interface b24, the connector 22 is connected with the serial transceiver 23, preferably, the serial transceiver 23 is a serial GTX transceiver interface, the FPGA main board 21 is commercially available, in the prior art, an iberto tool is provided for performing high-speed hardware level testing on an Xilinx FPGA chip 23, by IBERT, the bit error rate can be obtained, the eye diagram can be observed, and the parameters of the serial transceiver 23 can be adjusted, so that the possible problems can be judged, and the hardware stability and the signal integrity can be conveniently verified.

In this embodiment, the daughter board 3 is an optical module, the daughter board 3 has an electrical signal transceiving interface 31, a signal processing module and an optical fiber transceiving interface 32, the electrical signal transceiving interface 31 is connected to the connector 22, the electrical signal transceiving interface 31 is connected to the signal processing module, the signal processing module is connected to the optical fiber transceiving interface 32, the optical fiber transceiving interface 32 is connected to the optical loop 33, the optical fiber transceiving interface 32 and the optical loop 33 form an optical loop, the electrical signal is converted into an optical signal by the signal processing module and transmitted to the optical loop 33 through the optical fiber transceiving interface 32, similarly, the optical signal in the optical loop 33 is transmitted to the signal processing module through the optical fiber transceiving interface 32, the signal processing module converts the optical signal into an electrical signal, and then transmits the electrical signal to the FPGA motherboard 21 through the connector 22, and then interacts with the upper computer 1 through the JTAG interface, further, the connector 22 has a plurality of sets of electrical signal channels, and the connector 22 is available in the prior art, and may be manufactured by itself or by a commercially available method, for example, the following application numbers are selected: 202110466273.5, the signal channel of the connector 22 is selected to be 12 groups, and correspondingly, the electrical signal receiving interface and the optical fiber transceiving interface 32 also have 12 groups of channels, so that the daughter board 3 can be responsible for 12-transmission 12-reception optical path loops, thereby realizing self-transmission and self-reception.

The working process of the utility model is as follows: during testing, the upper computer 1 is connected with a JTAG interface of the FPGA mainboard 2, then an interface of a serial GTX transceiver of the mainboard 2 is connected with one end of a connector 22, and the other end of the connector 22 is connected with an electric signal interface of the daughter board 3; the optical fiber transceiving interface 32 and the optical loop 33 are connected to form an optical loop, then the upper computer 1 is operated, the mainboard 2 starts to work, channels are selected to observe the error rate and the eye pattern index, the optical module test is completed, one-time assembly can be performed, the test of 12 groups of optical modules can be completed, and only one-time access is needed without multiple plugging, so that the test efficiency of the optical module is improved.

Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the utility model can be made, and equivalents and modifications of some features of the utility model can be made without departing from the spirit and scope of the utility model.

Claims (6)

1. An optical module testing device, characterized in that: including host computer, mainboard and daughter board, interface an has on the host computer, FPGA mainboard and connector have on the mainboard, interface b and serial transceiver have on the FPGA mainboard, interface an with interface b connects, the connector with serial transceiver connects, the daughter board has signal of telecommunication receiving and dispatching interface, signal processing module and optic fibre receiving and dispatching interface, signal of telecommunication receiving and dispatching interface with the connector is connected, signal of telecommunication receiving and dispatching interface with signal processing module connects, signal processing module with optic fibre receiving and dispatching interface connects, optic fibre receiving and dispatching interface connects with the optical circuit, just optic fibre receiving and dispatching interface forms the light path loop with the optical circuit.

2. A light module testing device according to claim 1, characterized in that: the connector has a plurality of sets of electrical signal channels thereon.

3. A light module testing device according to claim 2, characterized in that: the signal channels of the connector are 12 groups.

4. A light module testing device according to claim 1, characterized in that: the interface a is a JTAG interface.

5. A light module testing device according to claim 2, characterized in that: the interface b is a JTAG interface.

6. A light module testing device according to claim 1, characterized in that: the serial transceiver is a serial GTX transceiver.

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