CN216056425U - Divide disconnected negative pole scheme BMS's charging voltage wake-up circuit - Google Patents
Divide disconnected negative pole scheme BMS's charging voltage wake-up circuit Download PDFInfo
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- CN216056425U CN216056425U CN202122496408.0U CN202122496408U CN216056425U CN 216056425 U CN216056425 U CN 216056425U CN 202122496408 U CN202122496408 U CN 202122496408U CN 216056425 U CN216056425 U CN 216056425U
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Abstract
The utility model discloses a charging voltage wake-up circuit of a cathode-breaking scheme BMS, which comprises a voltage comparator U1, resistors R1, R2, R3, R4, R5, R6 and R7, capacitors C1, C2 and C3, and diodes D1, D2 and D3.
Description
Technical Field
The utility model relates to the technical field of electrical cabinets, in particular to a charging voltage wake-up circuit of a cathode breaking scheme BMS.
Background
A Battery Management System (Battery Management System), which is a System for managing a Battery, referred to as BMS for short, mainly aims to prevent the Battery from being excessively charged and discharged, reduce safety risks, and prolong the service life of the Battery.
After the battery PACK (a term of art, which may be roughly understood as grouping or assembling) and the test are completed, the BMS consumes the battery power while generating the power consumption, so the BMS needs to enter a sleep mode with lower power consumption to reduce the battery power consumption meaningless during the storage and transportation stages as much as possible; when the battery power is too low, the BMS also enters a sleep mode, the power consumption is reduced, and the time from the battery power supporting to the charging is prolonged as far as possible. Therefore, there is a need for a technical means for waking up (also called activating) after the BMS enters the sleep mode, which has various technical means, such as ACC signal wake-up, load access wake-up, charging wake-up, etc., but has more or less following disadvantages: need external voltage to insert to awaken up BMS and get into the mode of charging, need the negative pressure of quantitative detection PACK-interface, need introduce extra electric wiring, the work consumption of circuit itself is high, and reverse withstand voltage is low, and barrier propterty is poor.
SUMMERY OF THE UTILITY MODEL
In view of the defects of the prior art, the utility model provides a charging voltage wake-up circuit of a disconnected negative pole scheme BMS, which solves the problems in the background art.
In order to achieve the purpose, the utility model is realized by the following technical scheme: a charging voltage wake-up circuit of a disconnected negative pole scheme BMS comprises a voltage comparator U1, resistors R1, R2, R3, R4, R5, R6 and R7, capacitors C1, C2 and C3, diodes D1, D2 and D3, and is characterized in that: the IN-end of the U1 is connected with the anode of the D1 after being connected with the R5 IN series, the cathode of the D1 is connected with the cathode of a charger PACK after being connected with the R4 IN series, and the IN + end of the U1 is connected with the cathode of a battery BAT after being connected with the R7 IN series; one end of the C2 is connected with the negative electrode of the battery BAT, and the other end is connected with the positive electrode of D1; the positive electrode of the D2 is connected with the negative electrode of the battery pack BAT, and the negative electrode of the D2 is connected with the positive electrode of the D1; one end of the R3 is connected with the anode of the D1, and the other end of the R3 is connected with the output voltage LpVcc of the comparator after being connected with R1 in series; one end of the R2 is connected between the R1 and the R3, and the other end is grounded; the VCC end of the U1 is the output voltage LpVcc of the comparator; one end of the C1 is connected with the output voltage LpVcc of the comparator, and the other end is grounded; the serial resistor R6 at the OUT end of the U1 is connected with ChgWkupDet; one end of the C3 is connected with ChgWkupDet, and the other end is grounded; the GND terminal of the U1 is grounded.
Preferably, the resistors R1, R2 and R3 are bias voltage dividing resistors, and R4 is a current limiting resistor.
Preferably, the capacitor C2 is a filter capacitor.
Preferably, the diode D3 is a back-end voltage comparator protection diode.
Preferably, the resistor R3 and the capacitor C3 form an output RC filter circuit of the voltage comparator.
The utility model provides a charging voltage wake-up circuit of a cathode-breaking scheme BMS, which has the following beneficial effects: the charging voltage is connected into the wake-up BMS to enter a charging mode, external voltage does not need to be introduced, the negative pressure of a PACK-interface does not need to be quantitatively detected, extra electric wiring does not need to be introduced, the circuit works and is in an ultra-low power consumption mode, the introduced extra power consumption is extremely low, the reverse voltage resistance is high, and the protection performance is good.
Drawings
FIG. 1 is a circuit diagram of a wake-up circuit of the present invention;
fig. 2 is a diagram of a divided negative electrode BMS architecture according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
As shown in fig. 1, the present invention provides a technical solution: a charging voltage wake-up circuit of a disconnected negative pole scheme BMS comprises a voltage comparator U1, resistors R1, R2, R3, R4, R5, R6 and R7, capacitors C1, C2 and C3, diodes D1, D2 and D3, and is characterized in that: the IN-end of the U1 is connected with the anode of the D1 after being connected with the R5 IN series, the cathode of the D1 is connected with the cathode of a charger PACK after being connected with the R4 IN series, and the IN + end of the U1 is connected with the cathode of a battery BAT after being connected with the R7 IN series; one end of the C2 is connected with the negative electrode of the battery BAT, and the other end is connected with the positive electrode of D1; the positive electrode of the D2 is connected with the negative electrode of the battery pack BAT, and the negative electrode of the D2 is connected with the positive electrode of the D1; one end of the R3 is connected with the anode of the D1, and the other end of the R3 is connected with the output voltage LpVcc of the comparator after being connected with R1 in series; one end of the R2 is connected between the R1 and the R3, and the other end is grounded; the VCC end of the U1 is the output voltage LpVcc of the comparator; one end of the C1 is connected with the output voltage LpVcc of the comparator, and the other end is grounded; the serial resistor R6 at the OUT end of the U1 is connected with ChgWkupDet; one end of the C3 is connected with ChgWkupDet, and the other end is grounded; the GND terminal of the U1 is grounded.
In the utility model, U1 is a voltage comparator; the resistors R1, R2 and R3 are bias voltage dividing resistors; d1 and D2 are charging wake-up loop diodes; r4 is a current limiting resistor; c2 is a filter capacitor for filtering the interference of the charger from AC coupling of the mains supply to DC charging voltage to prevent false triggering; d3 is a rear-end voltage comparator protection diode and a protection resistor; r3 and C3 form an output RC filter circuit of the voltage comparator; c1 is the voltage comparator power supply filter capacitor.
The wake-up circuit is applied to a segmented negative electrode BMS as shown in fig. 2, and the framework comprises a BMS mainboard, a charger PACK, a fusing fuse F1 and a battery PACK BAT, wherein the BMS mainboard is provided with a charging switch Qc (chgMos) and a discharging switch Qd (DsgMos), the G pole of the charging switch Qc and the G pole of the discharging switch Qd are both connected to the BMS mainboard, the D pole of the charging switch Qc is connected with the D pole of the discharging switch Qd, the S pole of the charging switch Qc is connected with the negative electrode of the charger, the S pole of the discharging switch Qd is connected with the negative electrode of the battery PACK after being connected with a series resistor Rs, and the positive electrode of the charger PACK is connected with the positive electrode of the fusing fuse F1 in series and then connected with the positive electrode of the battery PACK BAT.
After the BMS enters the sleep mode, the charging switch Qc is turned off, and at this time, the voltage comparator U1 is biased by the R1, R2, and R3, the voltage at the inverting input terminal is higher than the voltage at the non-inverting input terminal, and the comparator outputs a low level.
When the charger is connected, the direct current output by the charger flows out from the positive electrode of the charger, and returns to the negative electrode of the charger after passing through a battery positive electrode connecting wire, a battery pack negative electrode, D2, D1 and R4, at the moment, a forward voltage is generated at two ends of a diode D2, the voltage of the same-phase input end of a voltage comparator U1 is higher than that of the reverse input end, the voltage comparator outputs voltage LpVcc, and the voltage signal is used for waking up a rear-end microprocessor so as to activate the BMS and enter a charging state.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and equivalent alternatives or modifications according to the technical solution of the present invention and the inventive concept thereof should be covered by the scope of the present invention.
Claims (5)
1. A charging voltage wake-up circuit of a disconnected negative pole scheme BMS comprises a voltage comparator U1, resistors R1, R2, R3, R4, R5, R6 and R7, capacitors C1, C2 and C3, diodes D1, D2 and D3, and is characterized in that: the IN-end of the U1 is connected with the anode of the D1 after being connected with the R5 IN series, the cathode of the D1 is connected with the cathode of a charger PACK after being connected with the R4 IN series, and the IN + end of the U1 is connected with the cathode of a battery BAT after being connected with the R7 IN series; one end of the C2 is connected with the negative electrode of the battery BAT, and the other end is connected with the positive electrode of D1; the positive electrode of the D2 is connected with the negative electrode of the battery pack BAT, and the negative electrode of the D2 is connected with the positive electrode of the D1; one end of the R3 is connected with the anode of the D1, and the other end of the R3 is connected with the output voltage LpVcc of the comparator after being connected with R1 in series; one end of the R2 is connected between the R1 and the R3, and the other end is grounded; the VCC end of the U1 is the output voltage LpVcc of the comparator; one end of the C1 is connected with the output voltage LpVcc of the comparator, and the other end is grounded; the serial resistor R6 at the OUT end of the U1 is connected with ChgWkupDet; one end of the C3 is connected with ChgWkupDet, and the other end is grounded; the GND terminal of the U1 is grounded.
2. The charging voltage wake-up circuit of the split cathode scheme BMS according to claim 1, wherein: the resistors R1, R2 and R3 are bias voltage dividing resistors, and R4 is a current limiting resistor.
3. The charging voltage wake-up circuit of the split cathode scheme BMS according to claim 1, wherein: the capacitor C2 is a filter capacitor.
4. The charging voltage wake-up circuit of the split cathode scheme BMS according to claim 1, wherein: the diode D3 is a back-end voltage comparator protection diode.
5. The charging voltage wake-up circuit of the split cathode scheme BMS according to claim 1, wherein: the resistor R3 and the capacitor C3 form an output RC filter circuit of the voltage comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122496408.0U CN216056425U (en) | 2021-10-18 | 2021-10-18 | Divide disconnected negative pole scheme BMS's charging voltage wake-up circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122496408.0U CN216056425U (en) | 2021-10-18 | 2021-10-18 | Divide disconnected negative pole scheme BMS's charging voltage wake-up circuit |
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| CN216056425U true CN216056425U (en) | 2022-03-15 |
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| CN202122496408.0U Active CN216056425U (en) | 2021-10-18 | 2021-10-18 | Divide disconnected negative pole scheme BMS's charging voltage wake-up circuit |
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