CN216054702U - Display device - Google Patents

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Publication number
CN216054702U
CN216054702U CN202121056985.1U CN202121056985U CN216054702U CN 216054702 U CN216054702 U CN 216054702U CN 202121056985 U CN202121056985 U CN 202121056985U CN 216054702 U CN216054702 U CN 216054702U
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display device
metal film
conductive layer
led chip
array substrate
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CN202121056985.1U
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Chinese (zh)
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山田一幸
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Japan Display Inc
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Japan Display Inc
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Abstract

Provided is a display device provided with a heat dissipation mechanism that efficiently dissipates heat generated by an LED chip. The display device includes an array substrate having a pixel circuit including 1 or more LED chips on a 1 st surface side, and an uneven portion exposed in a space on a 2 nd surface side opposite to the 1 st surface side. The array substrate may include a metal film provided on the 2 nd surface side, and a surface of the metal film may be exposed in the space. The array substrate may include an insulating substrate and a metal film, the insulating substrate may be provided on the 1 st surface side, the metal film may be provided on the 2 nd surface side, and the unevenness may be a shape reflecting a shape of the insulating substrate.

Description

Display device
Technical Field
The present invention relates to a display device. In particular, the present invention relates to a display device mounted with an LED chip.
Background
Display devices using liquid crystal or oled (organic Light Emitting diode) have been commercialized as small and medium-sized display devices such as smart phones. In particular, an OLED display device using an OLED as a self-luminous element has advantages of higher contrast and no need for a backlight, compared with a liquid crystal display device. However, since the OLED is composed of an organic compound, it is difficult to secure high reliability of the OLED display device due to deterioration of the organic compound.
In recent years, development of display devices (so-called micro LED display devices or mini LED display devices) having a micro LED chip mounted as a pixel circuit of an array substrate has been advanced as a next-generation display device (for example, patent documents 1 and 2). LEDs are self-luminous elements like OLEDs. However, unlike OLEDs, LEDs are composed of inorganic compounds including gallium (Ga), indium (In), and the like. Thus, the micro LED display device can obtain higher reliability compared to the OLED display device. Further, the LED chip has higher luminous efficiency and luminance than the OLED display device. Therefore, the micro LED display device is expected as a next-generation display device having features of high reliability, high brightness, and high contrast.
Documents of the prior art
Patent document
Patent document 1: specification of U.S. Pat. No. 10090335
Patent document 2: chinese patent application publication No. 110190085 specification
SUMMERY OF THE UTILITY MODEL
Technical problem to be solved by the utility model
Unlike OLED displays, micro LED displays not only release light energy but also dissipate heat energy when emitting light. If a large current is supplied to the LED chip in order to achieve high luminance, large heat energy occurs. If the arrangement density of the LED chips is made high in order to achieve high contrast, the total amount of heat energy becomes large. If the thermal energy generated by the LED chip increases, the temperature of the entire display device increases, and the reliability of the LED chip and the reliability of the transistor of the pixel circuit and the like deteriorate. Therefore, in the micro LED display device, a mechanism for releasing thermal efficiency generated by the LED chip is required.
In view of the above problems, it is an object of the present invention to provide a display device provided with a heat dissipation mechanism that favorably dissipates heat generated by an LED chip.
Means for solving the problems
A display device according to an embodiment of the present invention includes an array substrate including a pixel circuit including 1 or more LED chips on a 1 st surface side, and an uneven portion exposed in a space on a 2 nd surface side opposite to the 1 st surface side.
In the display device, the array substrate may include a metal film provided on the 2 nd surface side, and a surface of the metal film may be exposed in the space.
In the display device, the array substrate may include an insulating substrate and a metal film, the insulating substrate may be provided on the 1 st surface side, the metal film may be provided on the 2 nd surface side, and the unevenness may be a shape reflecting a shape of the insulating substrate.
In the display device, the LED chips may be provided in plurality, the LED chips may be arranged periodically in the 1 st direction, and the irregularities may be provided in the 1 st direction at a period different from that of the LED chips.
In the display device, the irregularities may be irregularly provided.
In the display device, the metal film may be electrically connected to a part of a wiring provided in the pixel circuit.
In the display device, a fixed reference voltage may be supplied to the metal film and the wiring.
In the display device, the metal film may be connected to a part of a wiring provided in the pixel circuit via a 3 rd surface connecting the 1 st surface and the 2 nd surface.
Effect of the utility model
According to the display device of the present invention, thermal efficiency generated by the LED chip can be released well.
Drawings
Fig. 1 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
Fig. 2 is a schematic plan view of a display device according to an embodiment of the present invention.
Fig. 3 is a schematic plan view of a display device according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
Fig. 7 is a plan view showing the entire configuration of a display device according to an embodiment of the present invention.
Fig. 8 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention.
Fig. 9 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.
Fig. 10 is a sectional view of a display device according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present disclosure is merely an example. It is needless to say that the configuration which can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the present invention is included in the scope of the present invention. In the drawings, the width, thickness, shape, and the like of each portion are schematically shown as compared with the actual form in order to make the description clearer. However, the illustrated shape is merely an example, and does not limit the explanation of the present invention. In the present specification and the drawings, the same elements as those described above with respect to the existing drawings are denoted by the same reference numerals and are denoted by roman letters, and detailed description thereof may be omitted as appropriate.
In each embodiment of the present invention, a direction from the array substrate toward the LED chip is referred to as up or above. In contrast, a direction from the LED chip toward the array substrate is referred to as downward or below. In this way, for convenience of explanation, the description will be made using the terms upper or lower, but for example, the array substrate and the LED chip may be arranged so that the vertical relationship therebetween is reversed from that shown in the drawings. In the following description, for example, the expression of the LED chip on the array substrate is merely the above-described relationship between the array substrate and the LED chip. That is, other components may be disposed between the array substrate and the LED chip. The upper side or the lower side represents a lamination order in a structure in which a plurality of layers are laminated. That is, in the case where the pixel electrode is present above the transistor, the transistor and the pixel electrode may be in a positional relationship such that they do not overlap with each other in a plan view. On the other hand, the pixel electrode vertically above the transistor means a positional relationship in which the transistor and the pixel electrode overlap each other in a plan view.
In the present specification, the expression "a includes A, B or C", "a includes A, B and C" a includes one selected from the group consisting of A, B and C "does not exclude a combination of a plurality of a to C unless otherwise specified. Further, these expressions do not exclude the case where α includes other elements.
The following embodiments can be combined with each other as long as technical contradictions do not occur.
< embodiment 1 >
[ Structure of display device 10 ]
A display device 10 according to an embodiment of the present invention will be described with reference to fig. 1 to 3. Fig. 1 to 3 illustrate a pixel structure of a part of the display device 10. Fig. 1 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. As shown in fig. 1, the display device 10 includes an array substrate 100 and an LED chip 200. The array substrate 100 includes a 1 st surface 101 and a 2 nd surface 103. The 1 st surface 101 and the 2 nd surface 103 are opposite surfaces. In the present embodiment, the array substrate 100 is composed of an insulating substrate 109. That is, in the present embodiment, the array substrate 100 may be referred to as the insulating substrate 109 instead. The array substrate 100 includes conductive layers 114 and 116 on the 1 st surface 101 side. These conductive layers 114 and 116 are part of wirings provided in the pixel circuit 110, which will be described in detail later. The conductive layer 116 is a connection member connecting the conductive layer 114 and the LED chip 200. That is, the pixel circuit 110 is provided on the 1 st surface 101 side of the array substrate 100. The 2 nd surface 103 is provided with irregularities 120. The irregularities 120 are exposed in the space 129 below the display device 10.
In the case where the display device 10 is arranged in the interior of the housing, the irregularities 120 are exposed in the space 129 between the display device 10 and the housing. In other words, the irregularities 120 come into contact with the gas between the display device 10 and the casing. It is not necessary that the entire area of the irregularities 120 is exposed to the space 129, and at least a part of the irregularities 120 may be exposed to the space 129 as long as the effect of the present embodiment is obtained. For example, a double-sided tape or an adhesive resin may be provided at the lower end of the concave-convex portion 120, and the display device 10 may be bonded to the case by these adhesive members. In this case, the region other than the region where the adhesive member contacts in the unevenness 120 is exposed in the space 129. However, the space 129 in this case is a space surrounded by the display device 10, the case, and the adhesive member. In order to improve the heat dissipation efficiency of the array substrate 100, a through hole (air hole) may be provided in the case.
In the present embodiment, the example in which the unevenness 120 is formed by a protruding portion protruding downward in a semicircular shape from the 2 nd surface 103 of the array substrate 100 is shown, but the present invention is not limited to this configuration. For example, the shape of the concave-convex may be a cone or a rectangle. The unevenness 120 may be formed of a groove formed from the 2 nd surface 103 toward the inside of the array substrate 100. The cross-sectional shape of the groove may be semicircular, tapered, or rectangular, as in the case of the protrusion described above.
The irregularities 120 can be formed by etching, cutting, molding, laser processing, or the like of the insulating substrate 109. That is, the irregularities 120 may be formed by processing the 2 nd surface 103 side of the insulating substrate 109, or may be formed at the time of manufacturing the insulating substrate 109.
LED chip 200 is disposed over conductive layer 116. In the present embodiment, an anode electrode is provided at the lower portion of the LED chip 200, and a cathode electrode is provided at the upper portion of the LED chip 200. The anode electrode of the LED chip 200 is connected to the conductive layer 116. Although not shown, the cathode electrode of the LED chip 200 is connected to a conductive layer (e.g., a conductive layer 420D (see fig. 10) described later) provided above the cathode electrode. The LED chip 200 emits light by a current flowing in the LED chip 200 from the anode electrode toward the cathode electrode. In the present embodiment, the LED chip 200 emits light upward. A reflective member is provided on a side wall of the LED chip 200. The reflecting member is inclined so that the inclined surface faces upward, and reflects light emitted laterally from the light emitting portion of the LED chip 200 upward. The conductive layer 114 functions as a reflecting member, and reflects upward light emitted from the LED chip 200 toward the array substrate 100. The LED chip 200 is not limited to the above-described structure, and may have a structure in which a reflective member is not formed on a side wall. Further, the LED chip 200 may be a flip-chip type (lateral type) LED chip having an anode electrode and a cathode electrode provided on the lower portion thereof.
Fig. 2 is a schematic plan view of a display device according to an embodiment of the present invention, as viewed from below. The LED chip 200 is provided in plurality. For example, the LED chip 200 includes a red LED chip 201, a green LED chip 203, and a blue LED chip 205. The LED chips 200 are periodically arranged at a pitch P1 in the 1 st direction D1 and the 2 nd direction D2. The convex portion 121 of the unevenness 120 has a length in the 2 nd direction D2. The convex portions 121 and the concave portions 123 are alternately arranged in the 1 st direction D1. The irregularities 120 have a periodic shape with a pitch P2 in the 1 st direction D1. Pitch P1 is a different pitch than pitch P2. That is, the pitch P1 is a pitch that is not an integral multiple of the pitch P2. Since the pitch P1 and the pitch P2 have the above-described relationship, interference due to both pitches is suppressed. The color and the arrangement of the color of the LED chips arranged are not limited to those shown in fig. 1.
In fig. 2, the convex portion 121 has a length in the 2 nd direction D2 as an example, but the configuration is not limited to this. For example, as shown in fig. 3, the convex portion 121 may be circular. In fig. 3, the circular protrusions 121 are periodically arranged at a pitch P2 in the 1 st direction D1 and the 2 nd direction D2. However, the pitch of the 1 st direction D1 and the pitch of the 2 nd direction D2 may be different. The shape of the convex portion 121 may be a triangle, a quadrangle, another polygon, an ellipse, or a curved shape in a ring (ring) shape (closed shape or loop shape), in addition to the circular shape.
[ Material of Components of display device 10 ]
As the insulating substrate 109, a light-transmitting insulating substrate such as a glass substrate, a quartz substrate, or a plastic substrate (resin substrate) is used. As the plastic substrate, a substrate having flexibility such as a polyimide substrate, an acrylic substrate, a silicone substrate, or a fluororesin substrate is used. As the insulating substrate 109, a metal substrate such as a stainless steel substrate or an aluminum substrate is used. As the insulating substrate 109, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate is used. As the insulating substrate 109, a substrate having a thin film formed on a surface thereof is used as described below.
The conductive layer 114 functions as a pad for forming a connection member (conductive layer 116). The connection member is a member for mounting the LED chip 200. As the conductive layer 114, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and an alloy or a compound thereof are used. The conductive layer 114 may be formed using a single layer of the above-described material or may be formed using a stacked layer.
The conductive layer 116 functions as a connecting member for mounting the LED chip 200. As the conductive layer 116, for example, silver paste, solder, or Anisotropic Conductive Film (ACF) is used.
As described above, according to the display device 10 of the present embodiment, the surface area of the 2 nd surface 103 is increased by providing the irregularities 120 on the 2 nd surface 103 side of the array substrate 100. Thus, heat generated by the LED chip 200 is efficiently released. If a heat dissipation mechanism such as a heat sink (e.g., a metal member having copper seed crystals and irregularities) is attached to the display device 10 in order to dissipate heat, there is a problem that the thickness and manufacturing cost of the display device 10 increase. However, the display device 10 according to the present embodiment can form the irregularities 120 by processing the array substrate 100. Thus, an increase in the thickness and manufacturing cost of the display device 10 is suppressed. The display device 10 is configured to avoid the problem caused by the adhesiveness between the display device and the cooling mechanism.
< embodiment 2 >
A display device 10A according to an embodiment of the present invention will be described with reference to fig. 4. Fig. 4 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. The display device 10A shown in fig. 4 is similar to the display device 10 shown in fig. 1. However, the array substrate 100A is different from the array substrate 100 in that the 2 nd surface 103A side includes the metal film 130A. In the following description of the display device 10A, description of features similar to those of the display device 10 of fig. 1 will be omitted, and differences from the display device 10 will be mainly described.
[ Structure of display device 10A ]
As shown in fig. 4, the array substrate 100A includes an insulating substrate 109A and a metal film 130A. The LED chip 200A is provided on the 1 st surface 101A side of the insulating substrate 109A. The metal film 130A is provided on the 2 nd surface 103A side of the insulating substrate 109A. The array substrate 100A has irregularities 120A on the 2 nd surface 103A. Specifically, the insulating substrate 109A has a concave-convex shape, and the metal film 130A is formed substantially uniformly under the concave-convex shape of the insulating substrate 109A, whereby the metal film 130A is exposed in the space 129A on the surface of the concave-convex 120A. That is, the unevenness 120A is a shape reflecting the shape of the 2 nd surface 103A side of the insulating substrate 109A.
Here, the substantially uniform formation means that the metal film 130A is not intentionally formed so that the film thickness of the metal film 130A is different depending on the position where the metal film 130A is formed when the metal film 130A is formed. The metal film 130A is formed substantially uniformly, and the film thickness of the metal film 130A is not necessarily the same at all positions. That is, the thickness of the metal film 130A of the convex portion 121A and the thickness of the metal film 130A of the concave portion 123A may be different.
[ Material of Components of display device 10A ]
As the metal film 130A, Al, Ti, Cr, Co, Ni, Mo, Hf, Ta, W, Bi, Ag, Cu, and alloys or compounds thereof are used. The metal film 130A may be formed using the above-described material in a single layer or stacked layers. The thickness of the metal film 130A is 50nm to 5 μm or less or 100nm to 1 μm or less. However, the thickness of the metal film 130A is preferably 1 μm or more and 5 μm or less as long as the production cost is acceptable. As the metal film 130A, a material having higher thermal conductivity than the insulating substrate 109A is used.
As described above, according to the display device 10A of the present embodiment, even when heat is generated in a part of the array substrate 100A, the heat can be quickly diffused to the entire surface of the 2 nd surface 103A of the array substrate 100A through the metal film 130A. As a result, the entire 2 nd surface 103A can efficiently dissipate heat. Therefore, according to the present embodiment, in addition to the same effects as those of embodiment 1, an effect of further improving the heat radiation efficiency can be obtained.
< embodiment 3 >
A display device 10B according to an embodiment of the present invention will be described with reference to fig. 5. Fig. 5 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. The display device 10B shown in fig. 5 is similar to the display device 10A shown in fig. 4. However, the array substrate 100B is different from the array substrate 100A in that the 3 rd surface 105B side includes the metal film 140B. In the following description of the display device 10B, description of features similar to those of the display device 10A of fig. 4 will be omitted, and differences from the display device 10A will be mainly described.
[ Structure of display device 10B ]
As shown in fig. 5, the array substrate 100B includes an insulating substrate 109B, a metal film 130B, and a metal film 140B. The array substrate 100B includes conductive layers 114B and 116B on the 1 st surface 101B. The metal film 140B is disposed on the 3 rd surface 105B of the array substrate 100B. The 3 rd surface 105B is a surface connecting the 1 st surface 101B and the 2 nd surface 103B. In other words, the 3 rd surface 105B is a side surface of the array substrate 100B. The metal film 140B is connected to the conductive layer 114B (a part of a wiring provided in the pixel circuit 110B) on the 1 st surface 101B side, and is connected to the metal film 130B on the 2 nd surface 103B side. That is, the metal film 130B is electrically connected to the conductive layer 114B.
The metal film 140B may be provided on the entire 3 rd surface 105B, or may be provided on a part of the 3 rd surface 105B. That is, the metal film 140B may continuously surround the 3 rd surface 105B around the array substrate 100B, or may be discretely provided on the 3 rd surface 105B. The insulating substrate 109B may be provided with a through hole. The metal film 140B may connect the conductive layer 114B and the metal film 130B via the through hole. The metal film 140B may also be connected to the conductive layer 116B or the LED chip 200B.
The metal film 140B and the conductive layer 116B may be supplied with a reference voltage fixed to the ground potential (GND), for example.
[ Material of Components of display device 10B ]
As the metal film 140B, Al, Ti, Cr, Co, Ni, Mo, Hf, Ta, W, Bi, Ag, Cu, and alloys or compounds thereof are used. The metal film 140B may be formed using a single layer of the above-described material or may be formed using a stacked layer. The thickness of the metal film 140B is 50nm to 5 μm or less or 100nm to 1 μm or less. However, the thickness of the metal film 140B is preferably 1 μm or more and 5 μm or less as long as the production cost is acceptable. As the metal film 140B, a material having higher thermal conductivity than the insulating substrate 109A is used. The metal film 140B may be made of the same material as the metal film 130B or may be made of a material different from the metal film 130B. Further, the metal film 140B may be a conductive material that is not formed as a metal film, but is adhered and applied, such as a conductive tape or a conductive paste.
As described above, according to the display device 10B of the present embodiment, heat generated by the LED chip 200B can be efficiently transferred to the metal film 130B via the metal film 140B. As a result, according to the present embodiment, in addition to the same effects as those of embodiment 2, an effect of further improving the heat radiation efficiency can be obtained. In this embodiment, the potential connected to the metal film 140B is further stabilized. This embodiment also provides advantageous effects as a countermeasure against static electricity in the manufacturing process.
< embodiment 4 >
A display device 10C according to an embodiment of the present invention will be described with reference to fig. 6. Fig. 6 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. The display device 10C shown in fig. 6 is similar to the display device 10A shown in fig. 4. However, the array substrate 100C is different from the array substrate 100A in that the irregularities 120C are irregularly provided. In the following description of the display device 10C, description of features similar to those of the display device 10A of fig. 6 is omitted, and differences from the display device 10A will be mainly described.
[ Structure of display device 10C ]
As shown in fig. 6, the array substrate 100C has irregularities 120C on the 2 nd surface 103C. The pitch of the convex portions 121C and the concave portions 123C of the unevenness 120C is irregular. The height of the convex portion 121C from the 2 nd surface 103C and the width of the convex portion 121C in the 1 st direction D1 are also irregular. There is a correlation between the height and the width of the convex portion 121C. If the height of the convex portion 121C is large, the width of the convex portion 121C is also large, and if the height of the convex portion 121C is small, the width of the convex portion 121C is also small. However, the present invention is not limited to this configuration. For example, the height of the convex portion 121C may be substantially constant, and the width of the convex portion 121C may be irregular. On the contrary, the width of the convex portion 121C may be substantially constant, and the height of the convex portion 121C may be irregular. There may be no correlation between the height and the width of the convex portion 121C.
As described above, according to the display device 10C of the present embodiment, the same effects as those of embodiment 2 can be obtained.
< embodiment 5 >
The overall configuration of a display device according to an embodiment of the present invention will be described with reference to fig. 7 to 10. In the following embodiments, the overall configuration of the display device described in the above-described embodiments 1 to 4 will be described.
[ outline of the display device 20D ]
Fig. 7 is a plan view showing the entire configuration of a display device according to an embodiment of the present invention. As shown in fig. 7, the display device 20D includes an array substrate 100D, a flexible printed circuit board 600D (FPC600D), and an IC chip 700D. The display device 20D is divided into a display region 22D, a peripheral region 24D, and a terminal region 26D. The display region 22D is a region in which the pixel circuits 110D including the LED chips 200D are arranged in a matrix, and displays an image. The peripheral region 24D is a region around the display region 22D, and is a region where a driver circuit for controlling the pixel circuit 110D is provided. The terminal region 26D is a region where the FPC600D is provided. The side surface of the array substrate 100D at the outer edges of the peripheral region 24D and the terminal region 26D is the 3 rd surface 105D. The IC chip 700D is provided on the FPC 600D. The IC chip 700D supplies a signal for driving each pixel circuit 110D. The IC Chip 700D may be a Chip On Glass (COG) structure mounted on the array substrate 100D, for example.
[ Circuit Structure of display device 20D ]
Fig. 8 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. As shown in fig. 8, a source driver circuit 520D is provided at a position adjacent to the display region 22D in which the pixel circuit 110D is disposed in the 2 nd direction D2 (column direction). The gate driver circuit 530D is provided at a position adjacent to the display region 22D in the 1 st direction D1 (row direction). The source driver circuit 520D and the gate driver circuit 530D are disposed in the peripheral region 24D. However, the region in which the source driver circuit 520D and the gate driver circuit 530D are provided is not limited to the peripheral region 24D, and may be any region outside the region in which the pixel circuit 110D is provided.
The source wiring 521D extends from the source driver circuit 520D in the 2 nd direction D2, and is connected to the plurality of pixel circuits 110D arranged in the 2 nd direction D2. The gate wiring 531D extends from the gate driver circuit 530D in the 1 st direction D1 and is connected to the plurality of pixel circuits 110D arranged in the 1 st direction D1.
Terminal portions 533D are provided in the terminal region 26D. The terminal portion 533D and the source driver circuit 520D are connected by a connection wiring 541D. Similarly, the terminal portion 533D and the gate driver circuit 530D are connected by a connection wiring 541D. The FPC600D is connected to the terminal portion 533D, an external device connected to the FPC600D is connected to the display device 20D, and each pixel circuit 110D provided in the display device 20D is driven by a signal from the external device.
The display devices 10 to 10C shown in embodiments 1 to 4 correspond to a part of the pixel circuit 110D of the display device 20D shown in embodiment 5.
[ Pixel Circuit 110D of display device 20D ]
Fig. 9 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. As shown in fig. 9, the pixel circuit 110D includes elements such as a driving transistor 960D, a selection transistor 970D, a holding capacitor 980D, and an LED chip 200D. A source electrode of the selection transistor 970D is connected to the signal line 971D. The gate electrode of select transistor 970D is connected to gate line 973D. The source electrode of the driving transistor 960D is connected to an anode power supply line 961D. The drain electrode of the driving transistor 960D is connected to the anode of the LED chip 200D. The cathode of the LED chip 200D is connected to a cathode power supply line 963D. The gate electrode of the driving transistor 960D is connected to the drain electrode of the selection transistor 970D. The holding capacitor 980D is connected to the gate electrode and the drain electrode of the driving transistor 960D. The signal line 971D is supplied with a gray-scale signal that determines the emission intensity of the LED chip 200D. The gate line 973D is supplied with a signal for selecting a pixel row to which the above-described gray-scale signal is written.
[ Cross-sectional Structure of display device 20D ]
Fig. 10 is a cross-sectional view of a pixel circuit 110D of a display device 20D according to an embodiment of the present invention. As shown in fig. 10, the display device 20D includes a transistor 300D and a wiring portion 400D. The pixel circuit 110D is configured by the transistor 300D and the wiring portion 400D.
Transistor 300D is disposed on a base layer 310D. The transistor 300D includes a semiconductor layer 320D, a gate insulating layer 330D, a gate electrode 340D, an insulating layer 350D, and a conductive layer 402D (source and drain electrodes). The semiconductor layer 320D is disposed on the base layer 310D. The gate electrode 340D is disposed over the semiconductor layer 320D. The gate insulating layer 330D is disposed between the semiconductor layer 320D and the gate electrode 340D. An insulating layer 350D is disposed over the gate insulating layer 330D and the gate electrode 340D. The conductive layer 402D is provided over the insulating layer 350D and connected to the semiconductor layer 320D through an opening provided in the insulating layer 350D.
The wiring portion 400D includes a conductive layer 402D, a conductive layer 403D, a planarization layer 404D, a conductive layer 406D, an insulating layer 408D, a conductive layer 410D, a conductive layer 411D, a planarization layer 412D, a conductive layer 414D, a conductive layer 416D, a conductive layer 114D, and a conductive layer 116D. In the following description, the 1 st region 480D is a region where a wiring (conductive layer 116D) connected to the anode of the LED chip 200D is provided. The 2 nd region 490D is a region where a wiring (the conductive layer 420D) connected to the cathode of the LED chip 200D is provided.
A planarization layer 404D is disposed over the conductive layer 402D. An opening 422D and an opening 424D are formed in the planarization layer 404D. The opening 422D exposes a portion of the conductive layer 402D in the 1 st region 480D. Opening 424D exposes a portion of conductive layer 403D in region 2 490D. The conductive layer 406D is disposed on the planarization layer 404D and connected to the conductive layer 403D through the opening 424D. An insulating layer 408D is disposed over the conductive layer 406D. In the insulating layer 408D, an opening is provided at a position corresponding to the opening 422D. The conductive layer 406D is supplied with, for example, a common power supply voltage PVDD.
Conductive layer 410D and conductive layer 411D are disposed over insulating layer 408D. The conductive layer 410D is connected to the conductive layer 402D through the opening 422D. Conductive layer 411D is insulated from conductive layer 406D by insulating layer 408D. The conductive layer 411D is supplied with, for example, a common power supply voltage PVSS (for example, ground voltage GND).
A planarization layer 412D is provided over each of the conductive layer 410D and the conductive layer 411D. In the planarization layer 412D, an opening 426D for exposing the conductive layer 410D and an opening 428D for exposing the conductive layer 411D are provided. Conductive layer 114D and conductive layer 414D are disposed over planarization layer 412D. The conductive layer 114D is connected to the conductive layer 410D through the opening 426D. The conductive layer 414D is connected to the conductive layer 411D through the opening 428D.
Conductive layer 116D is disposed over conductive layer 114D. Conductive layer 416D is disposed over conductive layer 414D. The conductive layer 116D is used to mount the LED chip 200D to the wiring portion 400D. That is, the conductive layer 116D has a function of bonding the LED chip 200D and the conductive layer 114D and electrically connecting them. The conductive layer 116D may be referred to as a connection member. The Conductive layer 116D can be formed by a micro-dispensing method, an ink-jet method, a pin transfer method, a mask evaporation method, a mask sputtering method, an ACF (Anisotropic Conductive Film)/NCF (Non-Conductive Film) bonding method, or a printing method. The conductive layer 416D can also be formed by the same method as the conductive layer 116D.
A planarization layer 418D is provided over each of the conductive layers 116D and 416D so as to embed the LED chip 200D. In the planarization layer 418D, an opening 430D for exposing the conductive layer 416D is provided. The upper surface of the planarization layer 418D coincides with the upper surface of the LED chip 200D. As long as the upper surface of the LED chip 200D is exposed from the planarization layer 418D, the upper surface of the planarization layer 418D may not coincide with the upper surface of the LED chip 200D. A conductive layer 420D is disposed over the planarization layer 418D. The conductive layer 420D is connected to the LED chip 200D. Conductive layer 420D is connected to conductive layer 416D through opening 430D.
The conductive layer 116D is connected to the anode of the LED chip 200D. The conductive layer 420D is connected to the cathode of the LED chip 200D. When an ON voltage for turning ON (ON) the transistor 300D is supplied to the gate electrode 340D, a voltage supplied to a signal line (not shown) is supplied to the anode of the LED chip 200D via the transistor 300D and the conductive layers 410D, 114D, and 116D. The cathode of the LED chip 200D is connected to the conductive layer 411D via the conductive layers 420D, 416D, and 414D.
[ Material of Components of display device 20D ]
As each of the conductive layers and the gate electrode 340D constituting the transistor 300D and the wiring portion 400D, Al, Ti, Cr, Co, Ni, Mo, Hf, Ta, W, Bi, Ag, Cu, and alloys or compounds thereof are used. The conductive layer and the gate electrode may be formed using the above-described materials in a single layer or stacked layers. As each conductive layer constituting the wiring portion 400D, for example, a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) can be used. In particular, a transparent conductive material can be used as the conductive layer 420D. The conductive layer 114 has a function of reflecting light emitted from the LED chip 200D toward the wiring portion 400D upward. Therefore, a material having higher reflectance than other conductive layers can be used for the conductive layer 114D.
As respective insulating layers constituting the transistor 300D and the wiring portion 400DSilicon oxide (SiO) may be used for the gate insulating layer 330D and the base layer 310Dx) Silicon oxynitride (SiO)xNy) Silicon nitride (SiN)x) Silicon oxynitride (SiN)xOy) Aluminum oxide (AlO)x) Aluminum oxynitride (AlO)xNy) Aluminum oxynitride (AlN)xOy) Or aluminum nitride (AlN)x) And the like. SiO 2xNyAnd AlOxNyAre silicon compounds and aluminum compounds containing nitrogen (N) in a smaller amount than oxygen (O). SiNxOyAnd AlNxOyAre silicon compounds and aluminum compounds containing oxygen in a smaller amount than nitrogen. As the insulating layer, not only an inorganic insulating material but also an organic insulating material may be used. As the organic insulating material, for example, polyimide resin, acrylic resin, epoxy resin, silicone resin, fluorine resin, siloxane resin, or the like can be used. The insulating layer may be formed using an inorganic insulating layer material and an organic insulating layer material, respectively, or may be formed using a stack of these materials.
The planarization layers constituting the wiring portion 400D can alleviate the step of the unevenness caused by the structures located below the respective layers. As a material of the planarization layer, for example, an organic resin such as a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluorine resin, or a siloxane resin can be used. The organic resin may be used alone or in a stacked state as the planarization layer.
The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate as long as they are not contradictory to each other. The display device according to each embodiment includes a configuration in which a person skilled in the art appropriately adds, deletes, or changes a design of a component, or adds, omits, or changes a condition of a process, and the scope of the present invention is included as long as the person skilled in the art has the gist of the present invention.
Even if other operational effects are different from those obtained by the aspects of the above-described embodiments, it is needless to say that those obvious from the description of the present specification or those easily predictable by those skilled in the art are understood to be obtained by the present invention.
Description of the reference symbols
10. 20D: a display device; 22D: a display area; 24D: a peripheral region; 26D: a terminal area; 100: an array substrate; 101: the 1 st surface; 103: the 2 nd surface; 105B: the 3 rd surface; 109: an insulating substrate; 110: a pixel circuit; 114. 116: a conductive layer; 120: concave-convex; 121: a convex portion; 123: a recess; 129: a space; 130A, 140B: a metal film; 200: an LED chip; 201: a red LED chip; 203: a green LED chip; 205: a blue LED chip; 300D: a transistor; 310D: a base layer; 320D: a semiconductor layer; 330D: a gate insulating layer; 340D: a gate electrode; 350D, 408D: an insulating layer; 400D: a wiring section; 402D, 403D, 406D, 410D, 411D, 414D, 416D, 420D: a conductive layer; 404D, 412D, 418D: a planarization layer; 422D, 424D, 426D, 428D, 430D: an opening; 480D: region 1; 490D: a 2 nd region; 520D: a source driver circuit; 521D: a source wiring; 530D: a gate driver circuit; 531D: a gate wiring; 533D: a terminal portion; 541D: connecting wiring; 600D: a flexible printed circuit substrate; 700D: a chip; 960D: a drive transistor; 961D: an anode power supply line; 963D: a cathode power supply line; 970D: a selection transistor; 971D: a signal line; 973D: a gate line; 980D: a holding capacitance.

Claims (5)

1. A display device is characterized in that a display panel is provided,
the liquid crystal display device includes an array substrate having a 1 st surface side provided with a pixel circuit including 1 or more LED chips, and a 2 nd surface side opposite to the 1 st surface side provided with irregularities exposed in a space,
the unevenness is a shape obtained by processing the 2 nd surface side of the array substrate,
the array substrate includes a metal film provided on the 2 nd surface side,
the surface of the metal film is exposed in the space,
the metal film is connected to a part of a wiring provided in the pixel circuit via a 3 rd surface connecting the 1 st surface and the 2 nd surface.
2. The display device of claim 1,
the array substrate includes an insulating substrate,
the insulating substrate is provided on the 1 st surface side,
the unevenness is a shape reflecting the shape of the insulating substrate.
3. The display device according to claim 1 or 2,
the LED chip is provided with a plurality of LED chips,
a plurality of the above-mentioned LED chips are periodically arranged in the 1 st direction,
the irregularities are provided in the 1 st direction at a period different from that of the LED chip.
4. The display device according to claim 1 or 2,
the irregularities are irregularly arranged.
5. The display device of claim 1,
a fixed reference voltage is supplied to the metal film and the wiring.
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JP5459623B2 (en) 2010-10-15 2014-04-02 東芝ライテック株式会社 Lighting device
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