CN215956686U

CN215956686U - Intelligent discharge circuit

Info

Publication number: CN215956686U
Application number: CN202121642851.8U
Authority: CN
Inventors: 陈长兴
Original assignee: Shanghai Shiningic Electronic Technology Co ltd
Current assignee: Shanghai Shiningic Electronic Technology Co ltd
Priority date: 2021-07-19
Filing date: 2021-07-19
Publication date: 2022-03-04
Anticipated expiration: 2031-07-19

Abstract

An intelligent discharge circuit comprises a normally-on timing regulation T1 module, an intelligent discharge time T module, a first Pulse generation circuit Pulse, a current reduction timing regulation TX module, a first OR gate and a first inverter INV; a constant lighting timing adjustment T1 module, an intelligent discharge time T module, a current reduction timing adjustment TX module, a first OR gate and a first inverter INV are arranged in the chip; the output end of the constant-lighting timing adjusting T1 module is connected with the first input end of the first OR gate OR, the input end of the first inverter INV and the input end of the intelligent discharge time T module through the first Pulse generating circuit Pulse; the output end of the intelligent discharge time T module and the output end of the first inverter INV are connected with the input end of the current reduction timing regulation TX module; the output of the down-flow timing adjusting TX-module is connected to a second input of the first OR-gate OR. Therefore, the intelligent dimming module is arranged in the chip of the driving LED illuminating lamp, so that the energy is saved, and the application cost of a client is saved.

Description

Intelligent discharge circuit

Technical Field

The utility model belongs to the technical field of lighting circuits, and relates to an intelligent discharge circuit.

Background

With the gradual increase of the economic level, the application of outdoor lighting fixtures (for example, LED lighting) is becoming more and more extensive, and the outdoor lighting fixtures can be usually combined with surrounding roads, landscapes and buildings to design and install light, so as to achieve the unification of functionality and artistry.

Today, the outdoor lighting industry is developing towards large-scale, branding and intellectualization. The product upgrading speed is accelerated, the technological content of the product is continuously improved, and the requirements on intelligent technology and energy conservation are also increased.

The intelligent dimming can be used for setting the light of the personalized outdoor lighting lamp at will as the name suggests, and can be gradually closed from light to dark when the outdoor lighting lamp is closed, so that the intelligent dimming lamp is very favorable for saving energy, and meanwhile, the service life of the lamp can be effectively prolonged. Especially in outdoor lighting lamps (street lamps, yard lamps) and the like, the brightness needs to be adjusted at regular time along with the extension of night time and the gradual scarcity of people on the road, so that the aim of saving energy is fulfilled.

In the prior art, an intelligent dimming scheme usually performs an injection program through a single chip microcomputer, so as to control the output (on/off and intensity adjustment of light) of the LED lighting fixture. However, although the above method is simple and allows a customer to perform corresponding adaptation according to different requirements, when the method is applied to an LED lighting fixture, it also means that a single chip needs to be added to drive a chip of the LED lighting fixture, which increases the manufacturing cost, the area of the PCB circuit board, and the difficulty of wiring the PCB circuit board.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problems, the utility model provides a brand new intelligent discharge circuit, and an intelligent dimming module is arranged in a chip for driving an LED lighting lamp, so that energy is saved, and meanwhile, the application cost of a customer is saved.

In order to achieve the purpose, the technical scheme of the utility model is as follows:

an intelligent discharge circuit comprises a normally-on timing regulation T1 module, an intelligent discharge time T module, a first Pulse generation circuit Pulse, a current reduction timing regulation TX module, a first OR gate OR and a first inverter INV; the normally-on timing adjusting T1 module, the intelligent discharging time T module, the current-reducing timing adjusting TX module, the first OR gate and the first inverter INV are arranged in a chip; the output end of the normally-on timing adjusting T1 module is connected with the first input end of the first OR gate OR, the input end of the first inverter INV and the input end of the intelligent discharging time T module through the first Pulse generating circuit Pulse; the output end of the intelligent discharge time T module and the output end of the first inverter INV are connected with the input end of the current reduction timing adjustment TX module; the output end of the down-flow timing adjustment TX module is connected with the second input end of the first OR gate OR; the normally-on timing adjusting T1 module outputs a full-on timing adjusting time T1 and starts timing, and the first Pulse generating circuit Pulse generates an intelligent discharge time T through the intelligent discharge time T module; meanwhile, the first inverter INV inverts an output of the normally-on timing adjustment T1 module, the current-reduction timing adjustment TX module is turned on and reset until the smart discharge time T is over, at which time the current-reduction timing adjustment TX module is locked, the current-reduction timing adjustment TX module outputs a fixed waveform, an output of the normally-on timing adjustment T1 module and the current-reduction timing adjustment TX module are simultaneously input to the first OR gate OR, and the first OR gate OR outputs a smart discharge curve.

Further, the normally-on timing adjustment T1 module includes an external or internal variable resistor RT1, a first oscillator OSC1, and a first frequency-dividing circuit; the variable resistor RT1 is connected between the input terminal and the ground terminal of the first oscillator OSC1, and the frequency of the first oscillator OSC1 is controlled and adjusted by adjusting the resistance value of the variable resistor RT1, so that the full-bright timing adjustment time T1 varying with the resistance value of the variable resistor RT1 is obtained after passing through the first frequency dividing circuit.

Further, the normally-on timing adjustment T1 module includes an external or internal variable capacitor, a first oscillator OSC1, and a first frequency-dividing circuit; the variable capacitor is connected between the input end and the ground end of the first oscillator OSC1, and the capacitance value of the variable capacitor is adjusted to control and adjust the frequency of the first oscillator OSC1, so that the full-bright timing adjustment time T1 varying with the change of the capacitance value of the variable capacitor is obtained after passing through the first frequency division circuit.

Further, the intelligent discharge time T module includes a second oscillator OSC, a second Pulse generation circuit Pulse, and a second frequency-dividing circuit; the second oscillator OSC generates a clock signal CLK, and the clock signal CLK generates a fixed time T through a second frequency dividing circuit; and the intelligent discharge time T is reset by the second Pulse circuit Pulse after being started by the full-bright timing adjustment time T1, so that the full-bright timing adjustment time T1 is ensured to be synchronous with the intelligent discharge time T, and the full-bright timing adjustment time T1 is within the range of the intelligent discharge time T.

Furthermore, the current reduction timing adjustment TX module comprises a third oscillator OSCX, a third frequency dividing circuit, a fourth frequency dividing circuit, a timing current reduction circuit, a latch circuit, and an external or internal variable resistor RTX; adjusting the resistance value of the variable resistor RTX to adjust the frequency of the third oscillator OSCX, and generating time T0 through the third frequency dividing circuit, so as to obtain time T0 changing with the resistance value of the variable resistor RTX; the clock signal CLK generates a fixed period time TC through the fourth frequency dividing circuit, the timing current reducing circuit is controlled through a change time T0 to generate a waveform changing along with the duty ratio, the timing current reducing circuit outputs the period TC, the total current reducing time from full lighting to extinguishing is TC T0, and the latch circuit controlled through the fixed time T determines the final current reducing amplitude.

Further, the down-flow timing adjustment TX module includes a third oscillator OSCX, a third frequency dividing circuit, a fourth frequency dividing circuit, a timing down-flow circuit, a latch circuit, and an external or internal variable capacitor; adjusting the capacitance value of the variable capacitor to adjust the frequency of the third oscillator OSCX, and generating time T0 through the third frequency dividing circuit, thereby obtaining time T0 varying with the capacitance value of the variable capacitor; the clock signal CLK generates a fixed period time TC through the fourth frequency dividing circuit, the timing current reducing circuit is controlled through a change time T0 to generate a waveform changing along with the duty ratio, the timing current reducing circuit outputs the period TC, the total current reducing time from full lighting to extinguishing is TC T0, and the latch circuit controlled through the fixed time T determines the final current reducing amplitude.

Further, the current reduction amplitude is:

the downflow amplitude is 1- (T-T1)/(TC T0) 100%.

According to the technical scheme, the normally-on time T1 of the intelligent discharge circuit can be adjusted through the external resistor RT1, the final current reduction amplitude of the current reduction time TX can be adjusted through the external resistor RTX, and the internal fixed oscillator can control the time of the whole intelligent discharge circuit. In addition, for the customer flexibility and cost consideration, the resistor RT1 and the resistor RTX can also be built in the chip, and the intelligent discharge time T module can also select an external resistor to adjust the intelligent discharge time T.

Therefore, compared with products on the market, the power consumption of the utility model is reduced, and the cost and the application are both improved.

Drawings

FIG. 1 is a schematic diagram of an intelligent discharging circuit according to an embodiment of the present invention

FIG. 2 is a diagram of a normally-on timing adjustment T1 module according to an embodiment of the utility model

FIG. 3 is a diagram of an intelligent discharge time T module according to an embodiment of the utility model

FIG. 4 is a block diagram of a down-flow timing adjust TX block in an embodiment of the present invention

FIG. 5 is a waveform diagram of an intelligent discharging circuit according to an embodiment of the present invention

Detailed Description

The following description of the present invention will be made in detail with reference to the accompanying drawings 1 to 5.

Referring to fig. 1, fig. 1 is a schematic diagram of an intelligent discharge circuit according to an embodiment of the utility model. As shown in fig. 1, the intelligent discharge circuit includes a normally-on timing adjustment T1 module, an intelligent discharge time T module, a first Pulse generation circuit Pulse, a down-flow timing adjustment TX module, a first OR gate OR, and a first inverter INV; the normally-on timing adjusting T1 module, the intelligent discharging time T module, the current-reducing timing adjusting TX module, the first OR gate and the first inverter INV are arranged in a chip.

The output end of the normally-on timing adjusting T1 module is connected with the first input end of the first OR gate OR, the input end of the first inverter INV and the input end of the intelligent discharging time T module through the first Pulse generating circuit Pulse; the output end of the intelligent discharge time T module and the output end of the first inverter INV are connected with the input end of the current reduction timing adjustment TX module; the output terminal of the down-flow timing adjusting TX module is connected to the second input terminal of the first OR gate OR.

The normally-on timing adjusting T1 module outputs a full-on timing adjusting time T1 and starts timing, and the first Pulse generating circuit Pulse generates an intelligent discharge time T through the intelligent discharge time T module; meanwhile, the first inverter INV inverts the output of the normally-on timing adjustment T1 module, the current reduction timing adjustment TX module is turned on and reset until the intelligent discharge time T is over, the current reduction timing adjustment TX module is locked at this time, and the current reduction timing adjustment TX module outputs a fixed waveform, so that the purpose of fixing current is achieved. The output of the normally-on timing adjustment T1 module and the concurrent input of the down-flow timing adjustment TX module are the first OR gate, which outputs an intelligent discharge curve.

In some embodiments of the utility model, for convenience of adjustment, the client can adjust the fixed full-bright time and the fixed down-flow time by externally connecting an adjustable resistor or an adjustable capacitor according to the actual requirements of the client through two external ports, so as to realize the intelligent dimming application of the outdoor lighting lamp.

Referring to fig. 2, fig. 2 is a schematic diagram of a constant illumination timing adjusting T1 module according to an embodiment of the utility model. As shown, the normally-on timing adjustment T1 module includes an external or internal variable resistor RT1, a first oscillator OSC1, and a first frequency-dividing circuit; the variable resistor RT1 is connected between the input terminal and the ground terminal of the first oscillator OSC1, and the frequency of the first oscillator OSC1 is controlled and adjusted by adjusting the resistance value of the variable resistor RT1, so that the full-bright timing adjustment time T1 varying with the resistance value of the variable resistor RT1 is obtained after passing through the first frequency dividing circuit.

That is, the client can adjust the frequency of the first oscillator OSC1 by adjusting the resistance of the adjustable resistor RT1 and then obtain the full-bright timing adjustment time T1 varying with the resistance of the adjustable resistor through the frequency divider circuit T1 by adding the external adjustable resistor RT1 to the first oscillator OSC 1.

Of course, in other embodiments of the present invention, external or internal variable capacitors may be used instead of the variable resistor RT 1. Specifically, the normally-on timing adjustment T1 module may include an external or internal variable capacitor, a first oscillator OSC1, and a first frequency-dividing circuit; the variable capacitor is connected between the input end and the ground end of the first oscillator OSC1, and the capacitance value of the variable capacitor is adjusted to control and adjust the frequency of the first oscillator OSC1, so that the full-bright timing adjustment time T1 varying with the change of the capacitance value of the variable capacitor is obtained after passing through the first frequency division circuit.

Referring to fig. 3, fig. 3 is a schematic diagram of an intelligent discharge time T module according to an embodiment of the utility model. As shown, the smart discharge time T module may include a second oscillator OSC, a second Pulse generation circuit Pulse, and a second frequency dividing circuit; the second oscillator OSC generates a clock signal CLK, and the clock signal CLK generates an intelligent discharge time T through a second frequency dividing circuit; and the intelligent discharge time T is reset by the second Pulse circuit Pulse after being started by the full-bright timing adjustment time T1, so that the full-bright timing adjustment time T1 is ensured to be synchronous with the intelligent discharge time T, and the full-bright timing adjustment time T1 is within the range of the intelligent discharge time T.

Specifically, the circuit of the intelligent discharge time T of the present invention generates the clock signal CLK by selecting the fixed second oscillator OSC, and generates the intelligent discharge time T through the second frequency dividing circuit; and the intelligent discharge time T is reset by the Pulse circuit Pulse after being started by the full-bright timing adjusting time T1, so that the full-bright timing adjusting time T1 and the intelligent discharge time T can be synchronized, and the requirement of the full-bright timing adjusting time T1 in the range of the intelligent discharge time T is further met.

Referring to fig. 4, fig. 4 is a diagram illustrating a down-flow timing adjustment TX module according to an embodiment of the utility model. The current-reducing timing adjusting TX module comprises a third oscillator OSCX, a third frequency dividing circuit, a fourth frequency dividing circuit, a timing current-reducing circuit, a latch circuit and an external or internal variable resistor RTX; adjusting the resistance value of the variable resistor RTX to adjust the frequency of the third oscillator OSCX, and generating time T0 through the third frequency dividing circuit, so as to obtain time T0 changing with the resistance value of the variable resistor RTX; the clock signal CLK generates a fixed period time TC through the fourth frequency dividing circuit, the timing current reducing circuit is controlled through a change time T0 to generate a waveform changing along with the duty ratio, the timing current reducing circuit outputs the period TC, the total current reducing time from full lighting to extinguishing is TC T0, and the latch circuit controlled through the fixed time T determines the final current reducing amplitude.

Of course, in other embodiments of the present invention, an external or internal variable capacitor may be used instead of the variable resistor RTX. Specifically, the down-flow timing adjustment TX module may include a third oscillator OSCX, a third frequency dividing circuit, a fourth frequency dividing circuit, a timing down-flow circuit, a latch circuit, and an external or internal variable capacitor; adjusting the capacitance value of the variable capacitor to adjust the frequency of the third oscillator OSCX, and generating time T0 through the third frequency dividing circuit, thereby obtaining time T0 varying with the capacitance value of the variable capacitor; the clock signal CLK generates a fixed period time TC through the fourth frequency dividing circuit, the timing current reducing circuit is controlled through a change time T0 to generate a waveform changing along with the duty ratio, the timing current reducing circuit outputs the period TC, the total current reducing time from full lighting to extinguishing is TC T0, and the latch circuit controlled through the fixed time T determines the final current reducing amplitude.

In an embodiment of the present invention, the current reduction amplitude may be expressed as:

the flow reduction amplitude is 1- (T-T1)/(TC T0) 100%

Assuming that the full-on timing adjustment time T1 is 3 hours, the intelligent discharge time T is 8 hours, and the total current reduction time from full-on to off is 20 hours, the final current reduction amplitude is:

1-(8-3)/20*100％＝75％，

namely, the intelligent discharge circuit can realize normal lighting for 3 hours, and the brightness is changed to 75% of the original brightness after 5 hours of current reduction, and then the brightness is kept unchanged.

To summarize, in the embodiment of the present invention, the normally-on time T1 can be adjusted by the external resistor RT1, the final current-reducing amplitude of the current-reducing time TX can be adjusted by the external resistor RTX, and the internal fixed oscillator can control the time of the entire intelligent discharging circuit. Furthermore, for the customer flexibility and cost, the variable resistor RT1 and the variable resistor RTX may be built into the chip to adjust the smart discharge time T.

Referring to fig. 5, fig. 5 is a waveform diagram of an intelligent discharge circuit according to an embodiment of the utility model. As shown in fig. 5, the waveform of the intelligent discharge circuit in the embodiment of the present invention decreases to the amplitude of the intelligent discharge time T after the time TX elapses from the amplitude of the full-lighting timing adjustment time T1.

In conclusion, the utility model adjusts the whole intelligent discharge curve through the external adjusting resistor, thereby being more convenient and flexible to use, greatly saving energy and reducing application cost.

The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims

1. An intelligent discharge circuit, comprising: a normal lighting timing adjusting T1 module, an intelligent discharging time T module, a first Pulse generating circuit Pulse, a current reducing timing adjusting TX module, a first OR gate and a first inverter INV; the normally-on timing adjusting T1 module, the intelligent discharging time T module, the current-reducing timing adjusting TX module, the first OR gate and the first inverter INV are arranged in a chip;

the output end of the normally-on timing adjusting T1 module is connected with the first input end of the first OR gate OR, the input end of the first inverter INV and the input end of the intelligent discharging time T module through the first Pulse generating circuit Pulse; the output end of the intelligent discharge time T module and the output end of the first inverter INV are connected with the input end of the current reduction timing adjustment TX module; the output end of the down-flow timing adjustment TX module is connected with the second input end of the first OR gate OR; wherein the content of the first and second substances,

the normally-on timing adjusting T1 module outputs full-on timing adjusting time T1 and starts timing, and the first Pulse generating circuit Pulse generates intelligent discharging time T through the intelligent discharging time T module; meanwhile, the first inverter INV inverts an output of the normally-on timing adjustment T1 module, the current-reduction timing adjustment TX module is turned on and reset until the smart discharge time T is over, at which time the current-reduction timing adjustment TX module is locked, the current-reduction timing adjustment TX module outputs a fixed waveform, an output of the normally-on timing adjustment T1 module and the current-reduction timing adjustment TX module are simultaneously input to the first OR gate OR, and the first OR gate OR outputs a smart discharge curve.

2. The smart discharge circuit of claim 1 wherein the normally-on timing adjustment T1 module includes an external or internal variable resistor RT1, a first oscillator OSC1, and a first frequency-dividing circuit; the variable resistor RT1 is connected between the input terminal and the ground terminal of the first oscillator OSC1, and the frequency of the first oscillator OSC1 is controlled and adjusted by adjusting the resistance value of the variable resistor RT1, so that the full-bright timing adjustment time T1 varying with the resistance value of the variable resistor RT1 is obtained after passing through the first frequency dividing circuit.

3. The smart discharge circuit of claim 1 wherein the normally on timing adjustment T1 module includes an external or internal variable capacitor, a first oscillator OSC1, and a first frequency-dividing circuit; the variable capacitor is connected between the input end and the ground end of the first oscillator OSC1, and the capacitance value of the variable capacitor is adjusted to control and adjust the frequency of the first oscillator OSC1, so that the full-bright timing adjustment time T1 varying with the change of the capacitance value of the variable capacitor is obtained after passing through the first frequency division circuit.

4. The intelligent discharge circuit of claim 1, wherein the intelligent discharge time T module comprises a second oscillator OSC, a second Pulse generation circuit Pulse, and a second frequency dividing circuit; the second oscillator OSC generates a clock signal CLK, and the clock signal CLK generates a fixed time T through a second frequency dividing circuit; and the intelligent discharge time T is reset by the second Pulse circuit Pulse after being started by the full-bright timing adjustment time T1, so that the full-bright timing adjustment time T1 is ensured to be synchronous with the intelligent discharge time T, and the full-bright timing adjustment time T1 is within the range of the intelligent discharge time T.

5. The smart discharging circuit of claim 1, wherein the down-flow timing adjustment TX module comprises a third oscillator OSCX, a third frequency dividing circuit, a fourth frequency dividing circuit, a timing down-flow circuit, a latch circuit, and an external or internal variable resistor RTX;

adjusting the resistance value of the variable resistor RTX to adjust the frequency of the third oscillator OSCX, and generating time T0 through the third frequency dividing circuit, so as to obtain time T0 changing with the resistance value of the variable resistor RTX; the clock signal CLK generates a fixed period time TC through the fourth frequency dividing circuit, the timing current reducing circuit is controlled through a change time T0 to generate a waveform changing along with the duty ratio, the timing current reducing circuit outputs the period TC, the total current reducing time from full lighting to extinguishing is TC T0, and the latch circuit controlled through the fixed time T determines the current reducing amplitude.

6. The smart discharging circuit according to claim 1, wherein the down-flow timing adjustment TX module comprises a third oscillator OSCX, a third frequency dividing circuit, a fourth frequency dividing circuit, a timing down-flow circuit, a latch circuit and an external or internal variable capacitor;

adjusting the capacitance value of the variable capacitor to adjust the frequency of the third oscillator OSCX, and generating time T0 through the third frequency dividing circuit, thereby obtaining time T0 varying with the capacitance value of the variable capacitor; the clock signal CLK generates a fixed period time TC through the fourth frequency dividing circuit, the timing current reducing circuit is controlled through a change time T0 to generate a waveform changing along with the duty ratio, the timing current reducing circuit outputs the period TC, the total current reducing time from full lighting to extinguishing is TC T0, and the latch circuit controlled through the fixed time T determines the current reducing amplitude.

7. The intelligent discharge circuit of any one of claims 5 or 6, wherein the current reduction magnitude is:

the downflow amplitude is 1- (T-T1)/(TC T0) 100%.