CN215953727U - Digital signal measuring system and testing device - Google Patents
Digital signal measuring system and testing device Download PDFInfo
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- CN215953727U CN215953727U CN202121265239.3U CN202121265239U CN215953727U CN 215953727 U CN215953727 U CN 215953727U CN 202121265239 U CN202121265239 U CN 202121265239U CN 215953727 U CN215953727 U CN 215953727U
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Abstract
The utility model relates to the field of signal measurement, and discloses a digital signal measurement system and a digital signal test device, wherein a delay chain is used for improving the measurement precision of the rising edge time and the falling edge time of an input signal; detecting a signal edge through the output of the delay chain and recording an edge timestamp; calculating data information of the input signal in real time according to the time stamps of the rising edge and the falling edge; according to a measurement data reading command of a man-machine interaction interface input signal, obtaining cached current measurement data information; and the user directly reads the latest measurement data through the human-computer interaction interface. The measurement of the digital signal with the frequency of 1 hz-100 Mhz is supported by the measurement method of the digital signal, and the resolution reaches 50 ps. The measuring speed is high, and the time, the frequency, the high-low level time and the duty ratio of the current signal period can be calculated in real time as long as a complete signal period is captured.
Description
Technical Field
The utility model relates to the field of signal measurement, in particular to a digital signal measuring system and a digital signal testing device.
Background
Instruments, meters, chip automation test equipment and the like need to perform characteristic measurement such as period, frequency, duty ratio and the like on digital signals. The need for a wide frequency measurement range and measurement accuracy, especially high frequency measurements, determine the performance limits of the device. The measuring speed determines the testing efficiency of the equipment; the prior art is passive measurement, measurement is started only after a measurement command is initiated, then measurement data can be obtained after measurement is finished through a measurement waiting process, and the measurement efficiency is low.
For example, the patent name, a frequency measurement method, apparatus and frequency meter; patent application No.: CN 201110431534.6; the application date is: 2011-12-21; the patent states that a frequency measurement method, a frequency measurement device and a frequency meter patent disclose that a signal to be measured is converted into a standard digital signal through a signal conditioning circuit and then is input into a digital logic device; detecting the edge of the signal to be detected in the digital logic device through an edge detection circuit; and if the edge of the signal to be measured is detected to appear, the frequency measurement control state machine carries out equal-precision frequency measurement or period measurement according to the frequency measurement instruction signal to obtain the frequency of the signal to be measured.
In the prior art, the measurement of the digital signal is started only after a measurement command is initiated, the measurement time is long, and the measurement efficiency is low.
SUMMERY OF THE UTILITY MODEL
The utility model provides a digital signal measuring system and a digital signal testing device aiming at the defects that in the prior art, the measurement is started only after a measurement command is initiated for the measurement of a digital signal, the measurement time is long, and the measurement efficiency is low.
In order to solve the technical problem, the utility model is solved by the following technical scheme:
a digital signal measuring system comprises a hardware conditioning module and an FPGA digital logic module, wherein a signal source to be measured is converted into a digital signal through the hardware conditioning module and then is input into the FPGA digital logic module; the FPGA digital logic module comprises a delay chain, an edge detection module, a real-time calculation module, a data cache module and a human-computer interaction interface;
the delay chain is used for improving the precision of the time measurement of the rising edge and the falling edge of the input signal;
the edge detection module detects a signal edge through the output of the delay chain and records an edge timestamp;
the real-time calculation module calculates the data information of the input signal in real time according to the time stamps of the rising edge and the falling edge;
the data caching module is used for acquiring cached current measurement data information according to a measurement data reading command of a man-machine interaction interface input signal;
and the user directly reads the latest measurement data through the human-computer interaction interface.
The rising edge time stamp and the falling edge time stamp of the input signal can be accurately measured through the delay chain and the edge detection; the method comprises the steps of measuring in real time, detecting signal edges in real time, automatically detecting the signal edges at the bottom layer and then calculating and updating in real time whether a measurement command is initiated at the upper layer or not, and directly reading automatically refreshed data at the bottom layer when the upper layer needs to measure, so that the measurement time is shortened, and the measurement efficiency is improved.
Preferably, the real-time calculation module comprises a frequency module, a period module, a high-low level width module and a duty ratio module;
the frequency module is used for acquiring the frequency of an input signal;
the period module is used for acquiring the period of the input signal;
the high-low level width module is used for acquiring the high level width and the low level width of the input signal;
and the duty ratio module is used for acquiring the duty ratio of the input signal.
Preferably, the delay chain comprises N tapped delay circuits.
Preferably, the delay circuit is composed of logic devices inside the FPGA.
A digital signal testing device comprises a digital signal measuring system.
Due to the adoption of the technical scheme, the utility model has the remarkable technical effects that:
the rising edge time stamp and the falling edge time stamp of the input signal can be accurately measured through the delay chain and the edge detection; the method comprises the steps of measuring in real time, detecting signal edges in real time, automatically detecting the signal edges at the bottom layer and then calculating and updating in real time whether a measurement command is initiated at the upper layer or not, and directly reading automatically refreshed data at the bottom layer when the upper layer needs to measure, so that the measurement time is shortened, and the measurement efficiency is improved.
The delay chain is composed of N taps, and the delay time of each tap is within 50ps, so the calculated value resolution of the method can be within 50ps, and the method has higher precision. The FPGA digital logic module adopts an FPGA module, the working clock of the FPGA is 250Mhz, and the digital signal measuring system designed by the FPGA digital logic module can measure the digital signal of 100Mhz at most. There is theoretically no minimum frequency limit, but for practical considerations the minimum frequency is limited to 1 hz.
The digital signal measuring method supports the measurement of digital signals with all frequencies within the range of 1hz to 100Mhz, and has the advantages of wider frequency measuring range, higher measuring precision and resolution ratio of 50 ps. The measurement speed is high, and the data such as the time, the frequency, the high level time, the low level time, the duty ratio and the like of the current signal period can be calculated in real time as long as a complete signal period is captured.
Drawings
FIG. 1 is a system diagram of the present invention.
Fig. 2 is a circuit diagram of the delay chain of the present invention.
Fig. 3 is a cycle time waveform diagram of the present invention.
Fig. 4 is a waveform diagram of the present invention.
Fig. 5 is a system diagram of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Example 1
A digital signal measuring system comprises a hardware conditioning module and an FPGA digital logic module, wherein a signal source to be measured is converted into a digital signal through the hardware conditioning module and then is input into the FPGA digital logic module; the FPGA digital logic module comprises a delay chain, an edge detection module, a real-time calculation module, a data cache module and a human-computer interaction interface;
the delay chain is used for improving the precision of the time measurement of the rising edge and the falling edge of the input signal;
the edge detection module detects a signal edge through the output of the delay chain and records an edge timestamp;
the real-time calculation module calculates the data information of the input signal in real time according to the time stamps of the rising edge and the falling edge;
the data caching module is used for acquiring cached current measurement data information according to a measurement data reading command of a man-machine interaction interface input signal;
and the user directly reads the latest measurement data through the human-computer interaction interface. The signals are detected in real time for calculation, and when the man-machine interface initiates a measurement instruction, the measurement result can be directly read, so that the measurement time is shortened, and the measurement efficiency is improved.
The real-time calculation module comprises a frequency module, a period module, a high-low level width module and a duty ratio module;
the frequency module is used for acquiring the frequency of an input signal;
the period module is used for acquiring the period of the input signal;
the high-low level width module is used for acquiring the high level width and the low level width of the input signal;
and the duty ratio module is used for acquiring the duty ratio of the input signal.
The delay chain includes N tap delay circuits. Here N is set to 255.
The delay circuit is composed of logic devices in the FPGA.
The delay chain is composed of N taps, and the delay time of each tap is within 50ps, so the calculated value resolution of the method can be within 50ps, and the method has higher precision. The FPGA digital logic module adopts an FPGA module, the working clock of the FPGA is 250Mhz, and the digital signal measuring system designed by the FPGA digital logic module can measure the digital signal of 100Mhz at most. There is theoretically no minimum frequency limit, but for practical considerations the minimum frequency is limited to 1 hz.
Example 2
On the basis of the embodiment 1, in order to realize the digital signal measuring method adopted by the measuring system, the method comprises the steps that a signal source to be measured is converted into a standard digital signal through a signal conditioning circuit and then is input into a digital logic device; which also comprises that the device comprises a plurality of the devices,
measuring a time stamp, namely measuring a rising edge time stamp and a falling edge time stamp of an input signal through a delay chain and an edge detection module;
real-time calculation, namely calculating data information of the input signal in real time according to the time stamps of the rising edge and the falling edge;
and caching the measurement data into the latest measurement data according to the result output by real-time calculation for reading by upper-layer software.
And the man-machine interaction interface initiates a measurement result reading command, reads the latest data information, and determines whether the data is valid according to the caching time of the data.
If the buffering time is 2 times longer than the measured cycle time, the read measured data is invalid data, and the invalid data occurs for 2 reasons: 1. the input measured signal is abnormal (signal loss) and the measurement data is invalid; 2. when the frequency of the input signal changes (the frequency is reduced), the former-stage module needs to wait in the process of calculating new data measurement (the waiting time is a new cycle time).
The data information includes a signal period time, a signal frequency, a high level time, a low level time, and a duty cycle.
According to the cache data of the previous stage of edge detection module, the cycle time of the input signal can be calculated through 2 identical edge timestamps, rising edges or falling edges, and then the signal frequency can be calculated through the cycle time. According to the time from the rising edge to the falling edge, the high level can be calculated; according to the time from the falling edge to the rising edge, the low level width can be calculated; by high and low level width and duty cycle.
The data information of the input signal, the cycle time T, the signal frequency f,high level width ThighWidth of low level TlowThe duty cycle is calculated in the manner,
cycle time T ═ abs (trailing rising edge timestamp-leading rising edge time);
the signal frequency f is 1 s/period time T;
high level width Thigh＝tFalling edge time stamping–tRising edge time stamp；
Low level width Tlow＝tRising edge time stamp–tFalling edge time stamping；
Duty cycle (T ═ T)high/T)*100％。
Example 3
Based on the above embodiment, as can be seen from fig. 2, the delay chain circuit, the delay chain is implemented by using carry chain unit carry4 inside the FPGA, each carry4 includes 4 adders muxcy, and each muxcy is a tap; the time delay chain accurately measures the time stamp when the rising edge and the falling edge of the input signal reach the local, the measurement resolution and precision are improved, the resolution of the time stamp is determined by the delay time of each tap, and the time stamp can reach within 50 ps.
The measurement data is cached, the calculation result of the previous level is cached for user access acquisition, and the time period, the signal frequency, the high level, the low level and the duty ratio are obtained according to the new result data calculated by the previous level module; the method comprises the steps of updating new data into a buffer area, namely a register, resetting a timer to restart timing while updating the data, wherein the purpose of the timer is to indicate how long ago a calculation result in the current buffer area is obtained, and the purpose is to avoid that an external input signal is interrupted at the current moment, a previous-stage calculation module cannot output the latest calculation data any more, but the calculation result before signal interruption is still reserved in the buffer area, and the data is expired invalid data, so that a user can judge whether the read calculation result is valid or not by reading the time of the timer when reading the calculation result.
Example 4
On the basis of the above embodiment, the working clock of the FPGA in this embodiment is 250Mhz, and the rising edge of each clock samples the output state of the delay chain tap through the D flip-flop, where the output state of the delay chain tap includes a high level "1" and a low level "0"; if the sample value is not all 0's or all 1's, there is an edge change in the input signal.
The edge detection module detects the rising edge and the falling edge of the input signal and the number of taps of the signal passing through the delay chain according to the change state of the tap sampling of the delay chain, calculates the accurate time of the edge of the input signal relative to a local clock, and generates a rising edge timestamp and a falling edge timestamp.
The local timer for generating the time stamp is composed of a counter for generating coarse-grained time and a delay chain sampling value conversion data for generating fine-grained time.
Coarse-grained time counting is realized by a 250M working clock counter of the FPGA, the counter keeps counting after being electrified, and the counter is added with 4ns (one clock period time) when each clock rising edge arrives.
The fine granularity time counting is calculated through a delay chain, the delay of one tap of the delay chain is 19ps, and the total delay time is calculated according to the number of the taps passed by the signal edge.
The combination of the coarse grain count Tcnt and the fine grain count Tdelay can obtain a local accurate time stamp Tstmp when the signal edge arrives, where Tstmp is Tcnt-Tdelay.
For example, the count value of the coarse-grained counter Tcnt is 10000ns, the number of taps passed by the signal edge obtained by sampling in the tap state of the delay chain is 50, and if the average delay of each tap is about 19ps, the fine-grained counter Tdelay is the total delay of the taps, and Tdelay is 19ps × 50 or 950ps — 0.95 ns; the timestamp Tstmp-Tcnt-Tdelay-10000-0.950-9999.05 ns.
Example 5
On the basis of the above embodiments, the digital signal testing device is composed of a digital signal measuring system.
Claims (6)
1. A digital signal measuring system comprises a hardware conditioning module and an FPGA digital logic module, wherein a signal source to be measured is changed into a digital signal through the hardware conditioning module and is input to the FPGA digital logic module; the FPGA digital logic module is characterized by comprising a delay chain, an edge detection module, a real-time calculation module, a data cache module and a human-computer interaction interface;
the delay chain is used for improving the precision of the time measurement of the rising edge and the falling edge of the input signal;
the edge detection module is used for detecting the signal edge, recording an edge timestamp and outputting the signal edge through a delay chain;
the real-time computing module is used for computing the data information of the input signal according to the time stamps of the rising edge and the falling edge;
the data caching module is used for acquiring cached current measurement data information and reading a command according to measurement data of a man-machine interaction interface input signal;
and the human-computer interaction interface is used for acquiring the measurement data and directly reading the measurement data through the human-computer interaction interface.
2. The system for measuring the digital signals according to claim 1, wherein the real-time calculating module comprises a frequency module, a period module, a high-low level width module and a duty ratio module;
the frequency module is used for acquiring the frequency of an input signal;
the period module is used for acquiring the period of the input signal;
the high-low level width module is used for acquiring the high level width and the low level width of the input signal;
and the duty ratio module is used for acquiring the duty ratio of the input signal.
3. A digital signal measurement system according to claim 1, wherein the delay chain comprises N tapped delay circuits.
4. The system of claim 1, wherein the delay circuit is formed by logic devices inside the FPGA.
5. A system for measuring a digital signal as claimed in claim 1, wherein the data information of the input signal comprises signal cycle time, signal frequency, high level time, low level time and duty cycle.
6. A digital signal testing apparatus comprising the digital signal measuring system according to claims 1 to 5.
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