CN215934746U - High-voltage synchronous rectifier bridge - Google Patents
High-voltage synchronous rectifier bridge Download PDFInfo
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- CN215934746U CN215934746U CN202122037275.0U CN202122037275U CN215934746U CN 215934746 U CN215934746 U CN 215934746U CN 202122037275 U CN202122037275 U CN 202122037275U CN 215934746 U CN215934746 U CN 215934746U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The utility model provides a high-voltage synchronous rectifier bridge which comprises a three-phase bridge rectifier circuit, wherein the three-phase bridge rectifier circuit comprises an upper bridge arm and a lower bridge arm, the upper bridge arm and the lower bridge arm respectively comprise a control chip and MOS (metal oxide semiconductor) tubes, the control chip in the upper bridge arm and the control chip in the lower bridge arm are identical in circuit, the MOS tubes in the upper bridge arm and the lower bridge arm are respectively provided with a plurality of the MOS tubes, the control chips in the upper bridge arm and the lower bridge arm respectively correspond to the MOS tubes in the upper bridge arm and the lower bridge arm one by one and are electrically connected for controlling the working state of the MOS tubes of the upper bridge arm and the lower bridge arm, and therefore the high-voltage synchronous rectifier bridge has the advantages of reducing use cost, improving efficiency, reducing heat productivity, and being safe and reliable.
Description
Technical Field
The utility model belongs to the technical field of rectifier circuits, and particularly relates to a high-voltage synchronous rectifier bridge.
Background
At present, almost all two-phase and three-phase rectifier bridges on the market are formed by combining diodes, the voltage drop of the diodes of most rectifier bridges is about 700mV, even if Schottky diodes with low VT are used, the voltage drop is about 400mV, as shown in figure 1, the diodes have large voltage drop and high heat generation, and the heat generation is particularly serious when the output needs high-power supply.
SUMMERY OF THE UTILITY MODEL
The utility model provides a high-voltage synchronous rectifier bridge, which solves the problem of serious heating during high-power supply in the prior art.
The technical scheme of the utility model is realized as follows: a high-voltage synchronous rectifier bridge comprises a three-phase bridge rectifier circuit, wherein the three-phase bridge rectifier circuit comprises an upper bridge arm and a lower bridge arm, the upper bridge arm and the lower bridge arm respectively comprise a control chip and MOS (metal oxide semiconductor) tubes, the control chip in the upper bridge arm and the control chip in the lower bridge arm are identical in circuit, the MOS tubes in the upper bridge arm and the lower bridge arm are respectively provided with a plurality of control chips, and the control chips in the upper bridge arm and the lower bridge arm respectively correspond to the MOS tubes in the upper bridge arm and the lower bridge arm one by one and are electrically connected with the MOS tubes in the upper bridge arm and the lower bridge arm for controlling the working state of the MOS tubes connected with the upper bridge arm.
As a preferred embodiment, the MOS transistor in the upper arm includes a MOSFET device M1, a MOSFET device M2, and a MOSFET device M3 electrically connected in sequence, the lower arm includes a MOSFET device M4, a MOSFET device M5, and a MOSFET device M6 electrically connected in sequence, the MOSFET device M1 is electrically connected to the MOSFET device M4, the MOSFET device M2 is electrically connected to the MOSFET device M5, and the MOSFET device M3 is electrically connected to the MOSFET device M6 through a resistor R.
In a preferred embodiment, the source of the MOSFET device M1 is electrically connected to the electrically connected drain of the MOSFET device M4, the source of the MOSFET device M2 is electrically connected to the electrically connected drain of the MOSFET device M5, and the source of the MOSFET device M3 is electrically connected to the electrically connected drain of the MOSFET device M46.
As a preferred embodiment, the control chip includes a sampling circuit, a signal processing circuit and a logic linear driving circuit, which are electrically connected in sequence.
As a preferred embodiment, the sampling circuit includes a VCC terminal and an SR terminal, the VCC terminal is electrically connected to a gate of a PMOS transistor and a source R5 at the same time, a gate of a high-voltage MOS transistor N1 is electrically connected to a resistor R5, a drain of the PMOS transistor, a gate of a high-voltage MOS transistor N2, a resistor R1, a drain of the high-voltage MOS transistor N1 and a capacitor C1, a source of the high-voltage MOS transistor N1 is electrically connected to an anode of a zener diode Z1, an SR terminal is electrically connected to a resistor R1, a resistor R2 and a resistor R3, a resistor R2 is electrically connected to a drain of the high-voltage MOS transistor N2, a source of the high-voltage MOS transistor N2 is electrically connected to an anode of a zener diode Z2, a resistor R3 is electrically connected to an anode of a resistor R4 and a cathode of the zener diode Z3, a resistor C1 is electrically connected to a cathode of a diode Z1, a cathode of a diode Z2, a resistor R2 and a source of the high-voltage MOS transistor N2 are electrically connected to an LDI terminal as sampling voltage values of the sampling terminal.
As a preferred embodiment, the logic linear driving circuit comprises a MOS tube P, a MOS tube P and a MOS tube P which are connected in parallel, a MOS tube N is connected in parallel between the MOS tube P and the MOS tube P, the drains of the MOS tube P and the MOS tube P are respectively and electrically connected with the MOS tube N and the MOS tube N, the drain of the MOS tube P is electrically connected with the MOS tube N, the drain of the MOS tube N is electrically connected with the MOS tube P, the source of the MOS tube P is respectively and electrically connected with the MOS tube P, the drains of the MOS tube P and the MOS tube P are respectively and electrically connected with the MOS tube N and the MOS tube N, the source of the MOS tube N is sequentially connected in parallel with the MOS tube N and the MOS tube P, the drains of the MOS tube N and the MOS tube N are respectively and the MOS tube P, the drain of the MOS tube P is electrically connected with the DRV terminal, the source of the MOS tube N is respectively and the DRV terminal are electrically connected in series, the drain electrode of the MOS transistor P7 is electrically connected with the DRV terminal.
As a preferred implementation mode, the signal processing circuit comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, a signal processing module, an undervoltage protection circuit and a VCC end, wherein the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3 are electrically connected with the source-drain voltage difference of the MOSFET device, the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3 are respectively and electrically connected with a first reference voltage of-260 mV, a second reference voltage of-40 mV and a third reference voltage of-12 mV, the signal processing module is electrically connected with the undervoltage protection circuit, the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3, and the undervoltage protection circuit is electrically connected with a VCC power supply.
After the technical scheme is adopted, the utility model has the beneficial effects that:
the upper and lower bridge arms of the three-phase bridge rectifier circuit are completely identical in control part circuit, the MOSFET devices of the upper and lower bridge arms in the three-phase bridge rectifier circuit are in one-to-one corresponding connection and matching with the upper and lower pipe control circuits, so that the working state of the MOSFET devices of the upper bridge arm connected with the control circuit can be controlled, the upper and lower bridge arms of the full MOS pipe rectifier bridge can be subjected to self-adaptive control, the service life of the devices is prolonged, the use cost is reduced, the efficiency is improved, the heat productivity is reduced, and the full MOS pipe rectifier bridge is safe and reliable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a circuit diagram of the background art of the present invention;
FIG. 2 is a circuit diagram of the present invention;
FIG. 3 is a functional block diagram of the present invention;
FIG. 4 is a circuit diagram of the sampling circuit of FIG. 3;
FIG. 5 is a circuit diagram of the logic linear driving circuit of FIG. 3;
FIG. 6 is a schematic diagram of the synchronous rectification of the present invention;
fig. 7 is a schematic diagram of a signal processing circuit.
In the figure, M1-M6-MOSFET devices; r to R5-resistors; N1-N9-MOS tube; P1-P12-MOS tube; U1-U3-ortho acid amplifier.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2 to 7, a high-voltage synchronous rectifier bridge includes a three-phase bridge rectifier circuit, where the three-phase bridge rectifier circuit includes an upper bridge arm and a lower bridge arm, the upper bridge arm and the lower bridge arm respectively include a control chip and MOS transistors, the control chip in the upper bridge arm and the control chip in the lower bridge arm have the same circuit, the MOS transistors in the upper bridge arm and the lower bridge arm are respectively provided with a plurality of MOS transistors, and the control chips in the upper bridge arm and the lower bridge arm respectively correspond to the MOS transistors in the upper bridge arm and the lower bridge arm one-to-one and are electrically connected to control the operating states of the MOS transistors connected to the upper bridge arm.
A synchronous rectifier bridge is composed of a three-phase bridge rectifier circuit consisting of a control chip and MOS tubes. The control chip comprises a sampling circuit, a signal processing circuit, a time delay protection circuit, a reference circuit, an under-voltage locking circuit and a logic linear driving circuit, wherein the control parts of the three-phase upper and lower bridge arms are completely identical in circuit, and the MOSFET devices of the upper and lower bridge arms in the three-phase bridge rectification circuit are in one-to-one corresponding connection and matching with the upper and lower control circuits so as to control the working state of the MOSFET devices connected with the upper bridge arms through the control circuits; the utility model can carry out self-adaptive control on the upper and lower bridge arms of the full MOS tube rectifier bridge, prolongs the service life of the device, reduces the use cost, improves the efficiency, reduces the heat productivity, and is safe and reliable.
The MOS tube in the upper bridge arm comprises a MOSFET device M1, a MOSFET device M2 and a MOSFET device M3 which are electrically connected in sequence, the lower bridge arm comprises a MOSFET device M4, a MOSFET device M5 and a MOSFET device M6 which are electrically connected in sequence, the MOSFET device M1 is electrically connected with the MOSFET device M4, the MOSFET device M2 is electrically connected with the MOSFET device M5, and the MOSFET device M3 is electrically connected with the MOSFET device M6 through a resistor R. The source of the MOSFET device M1 is electrically connected to the electrically connected drain of the MOSFET device M4, the source of the MOSFET device M2 is electrically connected to the electrically connected drain of the MOSFET device M5, and the source of the MOSFET device M3 is electrically connected to the electrically connected drain of the MOSFET device M46.
The control chip comprises a sampling circuit, a signal processing circuit and a logic linear driving circuit which are electrically connected in sequence.
The sampling circuit comprises a VCC end and an SR end, the VCC end is simultaneously electrically connected with a grid electrode of a PMOS tube, a source electrode R5, a grid electrode of a high-voltage MOS tube N1 is electrically connected with a resistor R5, a drain electrode of the PMOS tube, a grid electrode of a high-voltage MOS tube N2, a resistor R1, a drain electrode of a high-voltage MOS tube N1 and a capacitor C1, a source electrode of a high-voltage MOS tube N1 is electrically connected with an anode of a voltage-stabilizing diode Z1, the SR end is electrically connected with a resistor R1, a resistor R2 and a resistor R3, the resistor R2 is electrically connected with a drain electrode of the high-voltage MOS tube N2, a source electrode of the high-voltage MOS tube N2 is electrically connected with an anode of the voltage-stabilizing diode Z2, a resistor R3 is electrically connected with anodes of the resistor R4 and the voltage-stabilizing diode Z3, a C1 is electrically connected with a cathode of a diode Z1, a cathode of the diode Z2, a cathode of the diode Z3, a resistor R4 and a ground, and sources of the high-voltage MOS tubes N1 and N2 are respectively and electrically connected with an LDI end as a sampling voltage value of the LDI end. SR to GND are phase voltages, N1, N2 are high-voltage MOS, GATE is connected with a 5V power supply VCC, S terminals LDI and SRS of N1 and N2 are sampled voltage values, and SR is sampled to be between-0.5V and 100V to be between-0.5V and 4.5V. Thereby giving the comparator in fig. 7 a reference voltage.
The logic linear driving circuit comprises a MOS tube P1, a MOS tube P2, a MOS tube P3, a MOS tube P4, a MOS tube P5, a MOS tube P6 and a MOS tube P7 which are connected in parallel, a MOS tube N5 is connected in parallel between the MOS tube P6 and the MOS tube P7, the drains of the MOS tube P1 and the MOS tube P2 are respectively and electrically connected to a MOS tube N1 and a MOS tube N2, the drain of the MOS tube P2 is electrically connected to a MOS tube N2, the drain of the MOS tube N2 is electrically connected to a MOS tube P2, the source of the MOS tube P2 is respectively and parallel connected to a MOS tube P2 and a MOS tube P2, the drains of the MOS tube P2 and the MOS tube P2 are respectively and serially connected to a MOS tube N2 and a MOS tube N2, the source of the MOS tube N2 is sequentially and parallel connected to a MOS tube N2 and a MOS tube N2, the drains of the MOS tube N2 and the MOS tube N2 are respectively and serially connected to a MOS tube P2, the drain of the MOS tube P2 is electrically connected to a DRV end, and the drain of the MOS tube P2 are respectively and the drain of the MOS tube P2 and the MOS tube P2 are electrically connected to a DRV end.
When the circuit detects that the voltage of the drain terminal of the power MOSFET is about 0.26V lower than the voltage of the source terminal of the power MOSFET, the power MOSFET is immediately turned on, at the moment, the signal processing module in FIG. 7 gives a signal of forcibly turning on 400nS, PD is pulled down, the MOS tube P1 is turned on, DRV is pulled up, after 400nS, PD is pulled up, the MOS tube P1 turns off the chip and enters a linear working state, and the operational amplifier composed of N3, N4, P4, P5, P6 and P8 controls the pull-up or pull-down of DRV. LDI is the SR signal collected in fig. 4, the DRV end is controlled by the bias of the N3 and N4 tubes, so that the voltage from the drain end to the source end of the power MOSFET is clamped at about-40 mV, when the SR voltage rises and the LDI also rises, the voltage difference from the source end to the drain end of the MOSFET is gradually reduced, when the voltage from the drain end to the source end of the power MOSFET rises to about-12 mV, the G end of the operational amplifier output end P8 is pulled down, the P8 is conducted, and the DRV end is pulled down, so that the external MOS is turned off.
The signal processing circuit comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, a signal processing module, an undervoltage protection circuit and a VCC end, wherein the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3 are electrically connected with the source-drain voltage difference of the MOSFET device, the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3 are respectively and electrically connected with a first reference voltage of-260 mV, a second reference voltage of-40 mV and a third reference voltage of-12 mV, the signal processing module is electrically connected with the undervoltage protection circuit, the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3, and the undervoltage protection circuit is electrically connected with a VCC power supply.
The application consists of a plurality of synchronous rectifier diodes, each of which replaces a diode in the original rectifier bridge. The upper bridge arm adopts a bootstrap power supply mode. When the rectifier bridge starts to work, current firstly passes through a body diode of the power MOSFET, and when the circuit detects that the voltage of the drain terminal of the power MOSFET is lower than the voltage of the source terminal of the power MOSFET by about 0.26V, the power MOSFET is immediately turned on, so that the conduction loss of the system is reduced. When Ton exceeds about 400ns, the logic pull-up of the power MOSFET drive will turn off, and then the linear driver intervenes. When the current through the power MOSFET drops such that the Drain voltage is about 40mV lower than the source voltage, the linear driver will increase the impedance of the MOSFET by lowering the drive voltage vdrive of the MOSFET, thereby maintaining the Drain voltage at about-40 mV. As the current approaches 0, the regulation of the linear driver fails to maintain the Drain voltage at-40 mV and the Drain voltage continues to rise. When the voltage reaches about-12 mV, the chip will immediately turn off the power MOSFET completely through logic. (see fig. 6)
The sampling circuit can collect the source-drain voltage difference VSR of the MOSFET device, when the collected voltage difference VSR is larger than a first reference voltage in the signal processing voltage, the signal processing circuit carries out logic driving on the MOSFET device through the logic linear driving circuit, and the logic driving state can be kept in the logic driving time; after the logic driving time, linearly driving the MOSFET device through a logic linear driving circuit;
and after the linear driving state is entered, the control circuit adjusts the driving voltage loaded to the connected MOSFET device, the source-drain voltage difference VSR of the MOSFET device is matched with the second reference voltage until the current flowing through the MOSFET device is close to 0, and when the source-drain voltage difference VSR of the MOSFET device is matched with the third reference voltage, the logic linear driving circuit immediately turns off the MOSFET device.
The circuit also comprises an under-voltage protection circuit, and when the power supply voltage provided by the upper tube power supply circuit is lower than the protection voltage VUVLO2, the upper tube control circuit can be in a sleep state through the under-voltage protection circuit; when the power supply voltage provided by the upper tube power supply circuit is greater than the protection voltage VUVLO2 and lower than the protection voltage VUVLO1, the upper bridge arm MOSFET device connected with the upper tube control circuit keeps in an off state until the power supply voltage provided by the upper tube power supply circuit is greater than the protection voltage VUVLO1, and the working state of the upper bridge arm MOSFET device is controlled by the upper tube control circuit.
The circuit also comprises a delay protection circuit, wherein the delay protection circuit can provide turn-on blanking time and turn-off blanking time, and when the upper tube control circuit drives the MOSFET device of the upper bridge arm to be turned on, the MOSFET device of the upper bridge arm can be in an on state after the turn-on blanking time; when the upper tube control circuit turns off the connected upper bridge arm MOSFET device, the upper bridge arm MOSFET device can enter a turn-off state after the turn-off blanking time.
The first reference voltage is-260 mV +/-20%, the second reference voltage is-40 mV +/-20%, the third reference voltage is-12 mV +/-20%, and the logic driving time is 400ns +/-20%. VUVLO1 was 2.8V. + -. 20%, VUVLO2 was 2.4V. + -. 20%.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention. In the description of the present invention, unless otherwise specified and limited, it is to be noted that the terms "mounted," "connected," and "connected" are to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, a communication between two elements, a direct connection, or an indirect connection via an intermediate medium, and specific meanings of the terms may be understood by those skilled in the art according to specific situations.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The high-voltage synchronous rectifier bridge is characterized by comprising a three-phase bridge rectifier circuit, wherein the three-phase bridge rectifier circuit comprises an upper bridge arm and a lower bridge arm, the upper bridge arm and the lower bridge arm respectively comprise a control chip and MOS (metal oxide semiconductor) tubes, the control chip in the upper bridge arm and the control chip in the lower bridge arm are identical in circuit, the MOS tubes in the upper bridge arm and the lower bridge arm are respectively provided with a plurality of MOS tubes, and the control chips in the upper bridge arm and the lower bridge arm respectively correspond to the MOS tubes in the upper bridge arm and the lower bridge arm one by one and are electrically connected with the MOS tubes in the upper bridge arm and the lower bridge arm for controlling the working state of the MOS tubes of the connected bridge arms.
2. The high-voltage synchronous rectifier bridge of claim 1, wherein the MOS transistor in the upper bridge arm comprises a MOSFET device M1, a MOSFET device M2 and a MOSFET device M3 which are electrically connected in sequence, the lower bridge arm comprises a MOSFET device M4, a MOSFET device M5 and a MOSFET device M6 which are electrically connected in sequence, the MOSFET device M1 is electrically connected with the MOSFET device M4, the MOSFET device M2 is electrically connected with the MOSFET device M5, and the MOSFET device M3 is electrically connected with the MOSFET device M6 through a resistor R.
3. The bridge of claim 2, wherein the source of the MOSFET device M1 is electrically connected to the electrically connected drain of the MOSFET device M4, the source of the MOSFET device M2 is electrically connected to the electrically connected drain of the MOSFET device M5, and the source of the MOSFET device M3 is electrically connected to the electrically connected drain of the MOSFET device M46.
4. The bridge of claim 1, wherein the control chip comprises a sampling circuit, a signal processing circuit and a logic linear driving circuit electrically connected in sequence.
5. The high voltage synchronous rectifier bridge according to claim 4, wherein the logic linear driving circuit comprises a parallel MOS transistor P, a parallel MOS transistor N between the parallel MOS transistor P and the parallel MOS transistor P, a parallel MOS transistor N and a parallel MOS transistor N respectively connected to the drains of the parallel MOS transistor P, a parallel MOS transistor N and a parallel MOS transistor P respectively connected to the sources of the parallel MOS transistor P and the parallel MOS transistor P, a parallel MOS transistor N and a parallel MOS transistor N respectively connected to the drains of the parallel MOS transistor N and the parallel MOS transistor N respectively connected to the drains of the parallel MOS transistor P and the parallel MOS transistor P, the drain electrode of MOS pipe P1 has DRV end, the source electrode of MOS pipe N5 and the source electrode of MOS pipe P8 are connected with DRV end electric respectively, the drain electrode of MOS pipe P7 and DRV end electric connection.
6. The high-voltage synchronous rectifier bridge according to claim 5, wherein the sampling circuit comprises a VCC end and an SR end, the VCC end is electrically connected to a gate of a PMOS (P-channel metal oxide semiconductor) transistor and a source R5 at the same time, the gate of the MOS transistor N1 is electrically connected to a resistor R5, a drain of the PMOS transistor, a gate of a high-voltage MOS transistor N2, a resistor R1, a drain of a MOS transistor N1 and a capacitor C1, the source of the MOS transistor N1 is electrically connected to an anode of a zener diode Z1, the SR end is electrically connected to a resistor R1, a resistor R2 and a resistor R3, the resistor R2 is electrically connected to a drain of a high-voltage MOS transistor N2, the source of the high-voltage MOS transistor N2 is electrically connected to an anode of a zener diode Z2, the resistor R3 is electrically connected to a resistor R4 and an anode of a zener diode Z3, the resistor C1 is electrically connected to a cathode of a diode Z1, a cathode of a diode Z2, a cathode of a resistor R2 and a source of the MOS transistor N2 are electrically connected to ground, and a source of the MOS transistor N2 are respectively connected to the LDI, The SRS terminal is used as a sampled voltage value.
7. The high-voltage synchronous rectifier bridge of claim 6, wherein the signal processing circuit comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, a signal processing module, an under-voltage protection circuit and a VCC end, the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3 are all electrically connected with a source-drain voltage difference of the MOSFET device, the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3 are respectively and electrically connected with a first reference voltage of 260mV, a second reference voltage of 40mV and a third reference voltage of 12mV, the signal processing module is electrically connected with the under-voltage protection circuit, the operational amplifier U1, the operational amplifier U2 and the operational amplifier U3, and the under-voltage protection circuit is electrically connected with a VCC power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202122037275.0U CN215934746U (en) | 2021-08-27 | 2021-08-27 | High-voltage synchronous rectifier bridge |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202122037275.0U CN215934746U (en) | 2021-08-27 | 2021-08-27 | High-voltage synchronous rectifier bridge |
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| CN215934746U true CN215934746U (en) | 2022-03-01 |
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