CN215904439U - Vehicle-mounted display system and vehicle - Google Patents

Abstract

The utility model discloses a vehicle-mounted display system and a vehicle, which comprise a camera information source, an FPGA component and a display screen; the camera information source comprises a vehicle-mounted camera and an analog video decoding chip; the vehicle-mounted camera is in signal connection with the FPGA component through the analog video decoding chip; the FPGA component is in signal connection with the display screen. According to the utility model, the image signal transmitted by the camera information source is processed by the independent FPGA component and then is directly transmitted to the display screen without passing through a Linux system of a vehicle central control, so that the Linux system is not required to be started, the image signal of the camera after the vehicle is started and electrified is rapidly displayed, a driver can rapidly judge the running of the vehicle or the environment condition around the vehicle without waiting after ignition, and the driver is helped to rapidly make the judgment on the running of the vehicle.

Description

Vehicle-mounted display system and vehicle

Technical Field

The utility model relates to the field of vehicle systems, in particular to a vehicle-mounted display system and a vehicle.

Background

With the development of technology and markets, vehicles are often equipped with external cameras that transmit image signals of specific orientations of the vehicle to a display screen located on a center console of the vehicle to assist the driver in making correct vehicle driving decisions. For example, a camera is additionally arranged at the lower part in front of the vehicle to make up a visual field blind area blocked by a nose and the like.

The existing external camera signal is controlled by the Linux system, so that a picture transmitted by the camera can be displayed on the display screen after the Linux system is powered on and initialized, the required time of the process is long, and the driver needs to wait for a long time in the process from starting the vehicle to calling the camera to acquire surrounding information (for example, in the process of looking up whether an obstacle exists in the reversing direction when a truck is started), so that inconvenience is brought to the driver.

Therefore, how to quickly provide an image signal of an external camera after a vehicle is started to help a driver to quickly make a decision is a problem to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a vehicle-mounted display system and a vehicle, and aims to solve the problems that in the prior art, the waiting time is long and the driving of a driver is hindered between the time when the vehicle is started and the time when an external camera image is displayed.

In order to solve the technical problem, the utility model provides a vehicle-mounted display system which comprises a camera information source, an FPGA component and a display screen;

the camera information source comprises a vehicle-mounted camera and an analog video decoding chip;

the vehicle-mounted camera is in signal connection with the FPGA component through the analog video decoding chip;

the FPGA component is in signal connection with the display screen.

Optionally, the vehicle-mounted display system further comprises a Linux information source and an Android information source;

the FPGA component also comprises a source switcher;

the camera information source, the Linux information source and the Android information source are in signal connection with the display screen through the information source switcher.

Optionally, in the vehicle-mounted display system, a multi-gear knob is further included;

the multi-gear knob is in signal connection with the information source switcher.

Optionally, in the vehicle-mounted display system, the analog video decoding chip is a TW9990 chip.

Optionally, in the vehicle-mounted display system, the TW9990 chip is in signal connection with the FPGA component via an ITU656 protocol.

Optionally, in the vehicle-mounted display system, the FPGA component further includes an RGB signal converter;

the camera information source is in signal connection with the display screen through the RGB signal converter.

Optionally, in the vehicle-mounted display system, the FPGA component further includes a deinterlacing processor;

the camera information source is connected with the display screen through the RGB signal converter and the de-interlacing processor in sequence.

Optionally, in the vehicle-mounted display system, the FPGA component further includes a ping-pong buffer;

the camera information source is connected with the display screen through the RGB signal converter, the de-interlacing processor and the ping-pong buffer in sequence.

Optionally, in the vehicle-mounted display system, the storage unit of the ping-pong buffer is a DDR3 storage unit.

A vehicle comprising an in-vehicle display system as claimed in any one of the preceding claims.

The vehicle-mounted display system comprises a camera information source, an FPGA component and a display screen; the camera information source comprises a vehicle-mounted camera and an analog video decoding chip; the vehicle-mounted camera is in signal connection with the FPGA component through the analog video decoding chip; the FPGA component is in signal connection with the display screen. According to the utility model, the image signal transmitted by the camera information source is processed by the independent FPGA component and then is directly transmitted to the display screen without passing through a Linux system of a vehicle central control, so that the Linux system is not required to be started, the image signal of the camera after the vehicle is started and electrified is rapidly displayed, a driver can rapidly judge the running of the vehicle or the environment condition around the vehicle without waiting after ignition, and the driver is helped to rapidly make the judgment on the running of the vehicle. The utility model also provides a vehicle with the beneficial effects.

Drawings

In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an embodiment of a vehicle-mounted display system provided in the present invention;

FIG. 2 is a schematic structural diagram of another embodiment of an in-vehicle display system provided by the present invention;

FIG. 3 is a schematic structural diagram of an in-vehicle display system according to another embodiment of the present invention;

fig. 4 is a schematic diagram of a pixel point corresponding to YcbCr data in an embodiment of the vehicle-mounted display system provided in the present invention;

FIG. 5 is a schematic diagram of a DDR3 single spatial cache image mechanism in an embodiment of the in-vehicle display system provided in the present invention;

fig. 6 is a diagram illustrating a ping-pong buffer mechanism.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the utility model will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the utility model, and not restrictive of the full scope of the utility model. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The core of the utility model is to provide a vehicle-mounted display system, the structure schematic diagram of one specific embodiment of which is shown in fig. 1, and is called as the first specific embodiment, and the first specific embodiment comprises a camera information source, an FPGA component 20 and a display screen 30;

the camera information source comprises a vehicle-mounted camera 11 and an analog video decoding chip 12;

the vehicle-mounted camera 11 is in signal connection with the FPGA component 20 through the analog video decoding chip 12;

the FPGA component 20 is in signal connection with the display screen 30.

In a preferred embodiment, the analog video decoding chip 12 is a TW9990 chip. The main part of a common decoding circuit is composed of an adv7180 chip, however, the adv7180 chip is not suitable for the vehicle-mounted field, and the TW9990 chip has low power consumption and low cost, and is suitable for being used as the analog video decoding chip 12 of the utility model.

Furthermore, the TW9990 chip is connected to the FPGA component 20 through an ITU656 protocol.

As a specific embodiment, the FPGA component 20 further includes an RGB signal converter;

the camera information source is in signal connection with the display screen 30 through the RGB signal converter.

Usually, the video format collected by the vehicle-mounted camera 11 is the data of the YcbCr color space, and in the utility model, the YcbCr video signal is further converted into the RGB video signal by the RGB signal converter. In the YcbCr color space, Y denotes a luminance signal, Cb, Cr denotes a chrominance signal, and the luminance signal and the chrominance signal are independent of each other. Because human eyes are most sensitive to luminance Y information, each pixel of the YcbCr data format sent by ITU656 contains Y information, and two adjacent pixels share one group of CbCr signals, so that the pixel color correspondence diagram of ITU656 format is shown in fig. 4, and the conversion relationship between RGB and YcbCr is as follows:

in the FPGA logical operation, floating point numbers cannot be directly used for operation, so that the left and right of an equation can be amplified by 256 times for operation, and the operation is reduced by 256 times after the operation is finished.

Further, the FPGA component 20 further includes a de-interlacing processor;

the camera information source is in signal connection with the display screen 30 sequentially through the RGB signal converter and the deinterlace processor.

Two basic concepts are first elucidated: interlaced scanning and progressive scanning.

Interlaced scanning means that when the display screen 30 displays an image, the odd lines are scanned first, and then the even lines are scanned after the odd lines are completely scanned, so that each image needs to be scanned twice, and the image display frame flickers greatly. Interlaced scanning is the division of each frame into two fields, each field containing all the odd or even scan lines of a frame, usually scanning the odd lines first to obtain a first field and then scanning the even lines to obtain a second field, as is the case with ITU656 video formats.

Each frame image is formed by the electron beam scanning sequentially line by line, which is called progressive scanning.

The biggest problem of interlaced scanning is that line-to-line flicker, parallel phenomena or vertical edge saw effect easily occur, and the visual effect viewed by human eyes is influenced. It is also difficult to solve the problem that the frequency of the interlaced scanning is too slow, the odd and even fields add up to 25 frames per second, and the data of the odd and even fields are collected at different times. Therefore, there is a sense of jaggy in visual effect when the object moves. Then, there is one solution: and (5) de-interlacing. De-interlacing is to use a single odd field to restore the complete image of both odd and even fields, and a single even field to restore the complete image of both odd and even fields, so that a 50Hz image is seen every second, and the human eye can hardly feel jaggy in visual sensitivity.

A total of three algorithms can implement de-interlacing, one of which is simply to reconstruct an image using the arithmetic mean of the most recent two data, as shown in equation 1; two and three of which are shown in equations 2 and 3, respectively, are referred to as parallel FIR filtering methods.

Equation 1:

Cb[i]＝((Cb[i-1]+Cb[i+1]))/2；

equation 2:

Cb[i]＝(160(Cb[i-1]+Cb[i+1])-48(Cb[i-3]+Cb[i+3])+24(Cb[i-5]+Cb[i+5])-12(Cb[i-7]+Cb[i+7])+6(Cb[i-9]+Cb[i+9])-42(Cb[i-11]+Cb[i+11]))/256；

equation 3:

Cb[i]＝(1300(Cb[i-1]+Cb[i+1])-420(Cb[i-3]+Cb[i+3])+236(Cb[i-5]+Cb[i+5])-152(Cb[i-7]+Cb[i+7])+104(Cb[i-9]+Cb[i+9])-70(Cb[i-11]+Cb[i+11])+48(Cb[i-13]+Cb[i+13])-32(Cb[i-15]+Cb[i+15])+20(Cb[i-17]+Cb[i+17])-12(Cb[i-19]+Cb[i+19])+6(Cb[i-21]+Cb[i+21])-4(Cb[i-23]+Cb[i+23]))/2048。

further, the FPGA component 20 further includes a ping-pong buffer;

the camera information source is in signal connection with the display screen 30 sequentially through the RGB signal converter, the de-interlacing processor, and the ping-pong buffer.

Still further, the storage unit of the ping-pong buffer is a DDR3 storage unit.

When buffering the deinterlaced video data, there is no line-field synchronization signal, and in order to ensure that the video data is correctly displayed on the LCD display 30, a storage space capable of buffering one frame of image data is created in the DDR 3. And writing the first pixel point of the image corresponding to the first data obtained by the de-interlacing processing into the first address of the storage space. The data obtained after the de-interlacing process are counted, and then are respectively written into corresponding address spaces. After counting one frame of data, returning to the first address of the storage space to continue storing the next frame of image. When displaying images, the FPGA reads data from the first address of the DDR3 storage space, counts the reading processes, and displays the read image data to the corresponding pixel point positions of the LCD display screen 30 respectively.

The above operation ensures that the data is not scrambled without the line field sync signal, but results in the currently read image being interleaved with the last stored image, as shown in fig. 5.

It can be seen from time t2 of fig. 5 that the two frames of images in the DDR3 memory space are interleaved. In order to solve the problem, the utility model adopts the ping-pong buffer to buffer ping-pong video, and opens up two-frame storage spaces A and B in DDR 3. The image data is always written in the two storage spaces by switching constantly, the area B is read when the area a is written, and the area a is read when the area B is written, so that read-write collision can be avoided, and video tearing is prevented, and a schematic diagram is shown in fig. 6.

The vehicle-mounted display system comprises a camera information source, an FPGA component 20 and a display screen 30; the camera information source comprises a vehicle-mounted camera 11 and an analog video decoding chip 12; the vehicle-mounted camera 11 is in signal connection with the FPGA component 20 through the analog video decoding chip 12; the FPGA component 20 is in signal connection with the display screen 30. In the utility model, the image signal transmitted by the camera information source is processed by the independent FPGA component 20 and then is directly transmitted to the display screen 30 without passing through a Linux system of a vehicle central control, so that the Linux system is not required to be started, the image signal of the camera after the vehicle is started and electrified is rapidly displayed, a driver can rapidly judge the running of the vehicle without waiting after ignition or the environment condition around the vehicle, and the driver is helped to rapidly make the judgment on the running of the vehicle.

On the basis of the first specific embodiment, the FPGA component 20 is further improved to obtain a second specific embodiment, a schematic structural diagram of which is shown in fig. 2 and includes a camera information source, the FPGA component 20 and a display screen 30;

the camera information source comprises a vehicle-mounted camera 11 and an analog video decoding chip 12;

the vehicle-mounted camera 11 is in signal connection with the FPGA component 20 through the analog video decoding chip 12;

the FPGA component 20 is in signal connection with the display screen 30;

the system also comprises a Linux information source 40 and an Android information source 50;

the FPGA component 20 further includes a source switch 21;

the camera signal source, the Linux signal source 40 and the Android signal source 50 are in signal connection with the display screen 30 through the signal source switcher 21.

In the present embodiment, the information source of the Linux system in the vehicle is combined with the information source of the Android system, specifically, in the central control of the modern vehicle, the Linux system and the Android system may exist at the same time, and each of the Linux system and the Android system has its own display signal and operation command, so that the information source switcher 21 is added to enable a driver to comprehensively obtain information or input an instruction on the display screen 30 of the central control of the vehicle, and the information source switcher 21 enables the information source of the display screen 30 to be freely switched among the camera information source, the Linux information source 40, and the Android information source 50, thereby implementing efficient information display.

On the basis of the second specific embodiment, in further consideration of the convenience in operation of the FPGA component 20, the control method of the FPGA component 20 is defined, and a third specific embodiment is obtained, where a schematic structural diagram of the third specific embodiment is shown in fig. 3 and includes a camera information source, the FPGA component 20, and a display screen 30;

the camera information source comprises a vehicle-mounted camera 11 and an analog video decoding chip 12;

the vehicle-mounted camera 11 is in signal connection with the FPGA component 20 through the analog video decoding chip 12;

the FPGA component 20 is in signal connection with the display screen 30;

the system also comprises a Linux information source 40 and an Android information source 50;

the FPGA component 20 further includes a source switch 21;

the camera signal source, the Linux signal source 40 and the Android signal source 50 are in signal connection with the display screen 30 through the signal source switcher 21;

also includes a multi-gear knob 22;

the multi-gear knob 22 is in signal connection with the source switcher 21.

This embodiment is still further on embodiment two's basis, prescribes a limit to FPGA subassembly 20's information source passes through gear position decision of gear knob 22, specifically, the different gears of knob have corresponded different information sources, and the driver only need slightly change the knob, can change display content on the display screen 30, it is more convenient to operate, does not adopt the click but rotatory, has avoided the driver to move away from the front window in the in-process sight that advances, goes the trouble of positioning button, only needs the afterglow to be cared for, perhaps directly fumbles and confirms gear knob 22 position can be operated, has promoted driving safety nature greatly.

The utility model also provides a vehicle which comprises the vehicle-mounted display system. The vehicle-mounted display system comprises a camera information source, an FPGA component 20 and a display screen 30; the camera information source comprises a vehicle-mounted camera 11 and an analog video decoding chip 12; the vehicle-mounted camera 11 is in signal connection with the FPGA component 20 through the analog video decoding chip 12; the FPGA component 20 is in signal connection with the display screen 30. In the utility model, the image signal transmitted by the camera information source is processed by the independent FPGA component 20 and then is directly transmitted to the display screen 30 without passing through a Linux system of a vehicle central control, so that the Linux system is not required to be started, the image signal of the camera after the vehicle is started and electrified is rapidly displayed, a driver can rapidly judge the running of the vehicle without waiting after ignition or the environment condition around the vehicle, and the driver is helped to rapidly make the judgment on the running of the vehicle.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The vehicle-mounted display system and the vehicle provided by the utility model are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims (10)

1. A vehicle-mounted display system is characterized by comprising a camera information source, an FPGA component and a display screen;

the camera information source comprises a vehicle-mounted camera and an analog video decoding chip;

the vehicle-mounted camera is in signal connection with the FPGA component through the analog video decoding chip;

the FPGA component is in signal connection with the display screen.

2. The vehicle-mounted display system of claim 1, further comprising a Linux source and an Android source;

the FPGA component also comprises a source switcher;

the camera information source, the Linux information source and the Android information source are in signal connection with the display screen through the information source switcher.

3. The vehicle display system of claim 2, further comprising a multi-position knob;

the multi-gear knob is in signal connection with the information source switcher.

4. The in-vehicle display system of claim 1, wherein the analog video decoding chip is a TW9990 chip.

5. The in-vehicle display system of claim 4, wherein the TW9990 chip is in signal connection with the FPGA component via an ITU656 protocol.

6. The in-vehicle display system of any of claims 1 to 5, wherein the FPGA component further comprises an RGB signal converter;

the camera information source is in signal connection with the display screen through the RGB signal converter.

7. The in-vehicle display system of claim 6, wherein the FPGA component further comprises a de-interlacing processor;

the camera information source is connected with the display screen through the RGB signal converter and the de-interlacing processor in sequence.

8. The in-vehicle display system of claim 7, wherein the FPGA component further comprises a ping-pong buffer;

the camera information source is connected with the display screen through the RGB signal converter, the de-interlacing processor and the ping-pong buffer in sequence.

9. The in-vehicle display system of claim 8, wherein the ping-pong buffer memory unit is a DDR3 memory unit.

10. A vehicle characterized in that it comprises an on-board display system as claimed in any one of claims 1 to 9.

Images