CN215895192U - Display substrate and display device - Google Patents

Abstract

The utility model provides a display substrate and a display device, relates to the technical field of display, and aims to solve the problem that a transition hole between a fan-out wire and a signal wire is easily damaged by transient large current entering the fan-out wire from a driving chip, so that a display panel has poor vertical and dark lines. The display substrate includes: a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out area; the display substrate further includes: the display device comprises a plurality of first signal lines, a plurality of fan-out lines and a plurality of first electrostatic protection circuits, wherein the first signal lines extend from a display area to a peripheral area; the fan-out line is positioned in the fan-out area; the fanout lines are coupled with the corresponding first signal lines; the fan-out lines comprise a plurality of target fan-out lines, and the target fan-out lines and the first signal lines coupled with the target fan-out lines are arranged in different layers; the first electrostatic protection circuit is located in the fan-out area and coupled with the corresponding fan-out line for releasing static electricity on the fan-out line. The display substrate provided by the utility model is used for forming a display device.

Description

Display substrate and display device

Technical Field

The utility model relates to the technical field of display, in particular to a display substrate and a display device.

Background

With the continuous development of display technologies, display products are developing towards narrow frames. In order to meet the development requirement of narrow frame, the width of a fan-out area in the display panel is narrowed, and fan-out lines distributed in the fan-out area are distributed in a mode that a gate metal layer and a source drain metal layer are alternately distributed. Under the condition that the data line is made of the source-drain metal layer, when the fanout line made of the gate metal layer is coupled with the corresponding data line, a switching hole and a conductive bridging portion are needed, namely, the conductive bridging portion is respectively coupled with the corresponding fanout line and the corresponding data line through the switching hole.

Although the structure is beneficial to the development of the narrow frame of the display panel, after the large current enters the fan-out wire from the driving chip of the display panel, the large current firstly passes through the switching hole of the fan-out area, so that the transient large current is easy to damage the switching hole, and the display panel has poor vertical and dark lines.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a display substrate and a display device, which are used for solving the problem that transient large current entering a fan-out wire from a driving chip easily damages a switching hole between the fan-out wire and a signal wire, so that a display panel has poor vertical and dark lines.

In order to achieve the above purpose, the utility model provides the following technical scheme:

a first aspect of the present invention provides a display substrate comprising: a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out region; the display substrate further includes:

a plurality of first signal lines extending from the display region to the peripheral region;

the fan-out lines are positioned in the fan-out area; the fan-out lines are coupled with the corresponding first signal lines; the multiple fan-out lines comprise multiple target fan-out lines, and the target fan-out lines and the first signal lines coupled with the target fan-out lines are arranged in different layers;

the first electrostatic protection circuits are located in the fan-out area and coupled with the corresponding fan-out lines and used for releasing static electricity on the fan-out lines.

Optionally, the display substrate further includes:

a plurality of conductive connection portions coupled to the corresponding target fanout line and the corresponding first signal line, respectively; the orthographic projection of the first electrostatic protection circuit on the substrate of the display substrate is positioned on one side, away from the display area, of the orthographic projection of the conductive connecting part on the substrate.

Optionally, the display substrate further includes a common signal line; the first electrostatic protection circuit includes:

a first transistor, a gate of which is coupled to the common signal line, a first pole of which is coupled to the corresponding fanout line, and a second pole of which is coupled to the common signal line;

and the grid electrode of the second transistor is coupled with the corresponding fanout line, the first pole of the second transistor is coupled with the corresponding fanout line, and the second pole of the second transistor is coupled with the common signal line.

Optionally, the display substrate further includes:

a bonding region, the fan-out region being located between the display region and the bonding region;

the second electrostatic protection circuits are coupled with the corresponding fan-out lines, and the second electrostatic protection circuits are located between the first electrostatic protection circuits and the binding regions and used for releasing static electricity on the fan-out lines.

Optionally, the second electrostatic protection circuit includes: the at least one third transistor is arranged along the extending direction of the fan-out line corresponding to the second electrostatic protection circuit, and the grid electrode, the first pole and the second pole of the third transistor are coupled with the corresponding fan-out line.

Optionally, the second electrostatic protection circuit includes: a plurality of third transistors whose channel width-to-length ratios become gradually smaller in a direction in which the fan-out region points to the bonding region.

Optionally, the display substrate further includes: a plurality of sub-pixels located in the display area, the sub-pixels including a driving transistor; the channel width-to-length ratios of the plurality of third transistors are smaller than the channel width-to-length ratio of the driving transistor.

Optionally, the display substrate includes a gate metal layer and a source drain metal layer, the target fanout line and the gate metal layer are arranged in the same layer and the same material as each other, a non-target fanout line of the plurality of fanout lines and the source drain metal layer are arranged in the same layer and the same material as each other, and the non-target fanout line and the corresponding first signal line form an integrated structure.

Optionally, the display substrate further includes:

a plurality of third ESD protection circuits, the third ESD protection circuits being located between the display area and the fan-out area, the third ESD protection circuits being coupled to the corresponding first signal lines for discharging static electricity on the first signal lines.

Optionally, the display substrate further includes:

the array circuit comprises a plurality of virtual transistor groups, a plurality of first control circuits and a plurality of second control circuits, wherein each virtual transistor group comprises at least one virtual transistor which is arranged along the extending direction of a first signal line corresponding to the virtual transistor group, and a first pole of each virtual transistor is coupled with the first signal line; the grid electrode of the virtual transistor and the second pole of the virtual transistor are both suspended;

and the virtual transistor group is multiplexed as the third electrostatic protection circuit.

Optionally, the dummy transistor group includes a plurality of dummy transistors, and a channel width-to-length ratio of the plurality of dummy transistors gradually decreases along a direction in which the display region points to the fan-out region.

Optionally, the display substrate further includes:

the sub-pixels are positioned in the display area and comprise driving transistors, and the channel width-length ratio of the driving transistors is larger than that of one part of the virtual transistors and smaller than that of the other part of the virtual transistors.

Based on the technical solution of the display substrate, a second aspect of the utility model provides a display device, which includes the display substrate.

Optionally, the display device further includes an opposite substrate and a liquid crystal layer, the opposite substrate is disposed opposite to the display substrate, and the liquid crystal layer is located between the display substrate and the opposite substrate.

In the technical scheme provided by the utility model, the first electrostatic protection circuit is arranged in the fan-out area and is coupled with the corresponding fan-out line, so that the static electricity with large current enters the fan-out line from the driving chip, firstly passes through the first electrostatic protection circuit, then passes through the position where the fan-out line is coupled with the first signal line, and then enters the first signal line. Therefore, in the technical scheme provided by the utility model, when the static electricity with large current passes through the first static protection circuit, the first static protection circuit can release the static electricity with large current, so that the phenomenon that the coupling point of the fan-out line and the first signal line is damaged by the transient large current is avoided, and the phenomenon that the display device has poor vertical and dark lines when the display substrate is applied to the display device is avoided. And the first electrostatic protection circuit releases high-current static electricity, and avoids that the high current directly damages a plurality of rows of driving transistors close to the peripheral area in the display area, thereby avoiding that part of sub-pixels form poor bright and dark points due to short circuit of the source and drain electrodes of the driving transistors.

Drawings

The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and not to limit the utility model. In the drawings:

FIG. 1 is a schematic diagram of a first ESD protection circuit of a display substrate according to an embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view taken along line A1A2 in FIG. 1;

FIG. 3 is a schematic diagram of a novel ESD protection circuit for a display substrate according to an embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view taken along line B1B2 in FIG. 3;

FIG. 5 is a schematic cross-sectional view taken along line C1C2 in FIG. 3;

FIG. 6 is a schematic diagram of a third ESD protection circuit for a display substrate according to an embodiment of the present invention;

fig. 7 is a schematic cross-sectional view taken along direction D1D2 in fig. 6.

Detailed Description

In order to further explain the display substrate and the display device provided by the embodiment of the utility model, the following detailed description is made with reference to the drawings of the specification.

At present, Organic light-Emitting diode (OLED) display devices and Thin-film transistor Liquid Crystal display devices (TFT-LCD) are developed towards narrow frames to improve display effect and screen ratio.

Since the cost of the COG (chip on glass) method is lower than that of the COF packaging method, the COG (chip on glass) method is widely used for display panels. In a display panel using the COG method, a driver chip (Source IC) is directly bonded to an array substrate in the display panel. The data signal provided by the driving chip can be transmitted to the data line through the fan-out line, and in the transmission process of the data signal, after entering the data line from the fan-out line, the data signal sequentially passes through an ESD (Electro-Static discharge) electrostatic ring and a Dummy area and finally enters the display area.

Meanwhile, the frame where the binding area of the display panel is located is narrowed, so that the wiring of the fanout line is denser. In order to arrange more fanout lines in a limited layout space, a mode of alternately arranging the fanout lines by using a gate metal layer and a source drain metal layer is considered. Under the condition that the data line is made of the source-drain metal layer, when the fanout line made of the gate metal layer is coupled with the corresponding data line, a switching hole and a conductive bridging portion are needed, namely, the conductive bridging portion is respectively coupled with the corresponding fanout line and the corresponding data line through the switching hole.

In addition, since the driving chip bonding area needs to be connected with the driving chip, the conductive bridging portion needs to be lapped, and the driving chip bonding area is located in the pad area of the display panel, in the production process of the display panel, such as a module section, the polarizer attaching and driving chip bonding process may encounter the ESD condition caused by equipment or human factors, and the generated static electricity enters the fan-out line through the conductive bridging portion on the surface of the bonding area and leads to the display area. In addition, before the array substrate and the color film substrate are assembled, for example, a TFT-LCD rubbing process also generates a large amount of static electricity, and the conductive bridging portion of the bonding region is the outermost film layer and is not protected by the film layer for isolating the static electricity, so that the static electricity can be introduced into the display region in the related supporting process of the display panel, thereby damaging and burning the transfer hole, and causing a vertical dark line on the display panel or damaging several driving thin film transistors in front of the display region to cause poor bright and dark spots. In addition, during the assembly and the finishing process of the client, a large ESD current may enter the display panel from the driving chip to cause damage.

The ESD electrostatic ring is arranged in the display panel, the influence of ESD can be eliminated, however, in order to prevent the phenomenon that the signal loss or crosstalk is caused by the fact that a large leakage current (a signal line is often connected with a Com wiring through an ESD unit) occurs when a Thin Film Transistor (TFT) in the ESD electrostatic ring normally works, the channel length L of the TFT is often large, and the impedance of the TFT is large due to the design of the large channel length, so that the capacity of resisting transient ESD large current is weak, the switching hole of the display panel and the TFT in a display area are the weak point that the large ESD current is firstly broken down, and the difficulty level of breaking down of the three parts is as follows: TFT of the display area ≈ via holes of the fan-out < ESD electrostatic ring.

Therefore, after the large current enters the fan-out line from the driving chip, the large current firstly passes through the switching hole of the fan-out area, and no protection is provided for the switching hole before the large current, so that the switching hole is easily damaged by the large current in the transient state, and the display panel has poor vertical dark lines. In addition, partial large current enters the display area through the switching hole, effective protection measures do not exist except an ESD electrostatic ring (the effect is not obvious enough), and under the condition that a fan-out line of the switching hole and a data line are not required to form an integrated structure, the large current can directly damage a plurality of rows of driving transistors close to the peripheral area in the display area, so that the source and drain electrodes are in short circuit, and partial sub-pixels are poor in bright and dark points.

Referring to fig. 1 and fig. 2, an embodiment of the utility model provides a display substrate, including: a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out area 21; the display substrate further includes:

a plurality of first signal lines 30, the first signal lines 30 extending from the display region 10 to the peripheral region;

the fan-out lines 31 are positioned in the fan-out area 21; the fanout line 31 is coupled to the corresponding first signal line 30; the plurality of fanout lines 31 include a plurality of target fanout lines 310, and the target fanout lines 310 are arranged in different layers from the first signal lines 30 coupled thereto;

the first electrostatic protection circuits 40 are located in the fan-out region 21, and the first electrostatic protection circuits 40 are coupled to the corresponding fanout lines 31 and used for releasing static electricity on the fanout lines 31.

Illustratively, the display area includes a rectangular display area, the peripheral area surrounds the display area, and the peripheral area includes an upper frame area, a lower frame area, a left frame area, and a right frame area. The lower frame area comprises a fan-out area 21 and a binding area, the fan-out area 21 is provided with a fan-out line 31, and the binding area is provided with a driving chip.

Illustratively, the first signal line 30 includes a data line or other signal line. The first signal line 30 includes a portion located in the display region and a portion located in the peripheral region.

Illustratively, at least a portion of the fan-out line 31 is located at the fan-out area 21. The fan-out lines 31 correspond to the first signal lines 30 one by one, and the fan-out lines 31 are coupled to the corresponding first signal lines 30 and corresponding pins of the driving chip respectively. The fanout line 31 can transmit a signal provided from the driving chip to the first signal line 30.

Illustratively, the plurality of fanout lines 31 include a plurality of target fanout lines 310 and a plurality of non-target fanout lines 311, the target fanout lines 310 are disposed on different layers from the first signal lines 30, and the non-target fanout lines 311 are disposed on the same layer and the same material as the first signal lines 30.

Illustratively, the plurality of first electrostatic protection circuits 40 correspond to the plurality of fanout lines 31 one by one, and the first electrostatic protection circuits 40 are coupled to the corresponding fanout lines 31 and configured to discharge static electricity on the corresponding fanout lines 31.

As can be seen from the specific structure of the display substrate, in the display substrate provided in the embodiment of the present invention, the first electrostatic protection circuit 40 is disposed in the fan-out region 21, and the first electrostatic protection circuit 40 is coupled to the corresponding fan-out line 31, so that the large-current static electricity enters the fan-out line 31 from the driving chip, first passes through the first electrostatic protection circuit 40, then passes through the position where the fan-out line 31 is coupled to the first signal line 30, and then enters the first signal line 30. Therefore, in the display substrate provided in the embodiment of the present invention, when the static electricity with a large current passes through the first static electricity protection circuit 40, the first static electricity protection circuit 40 can release the static electricity with a large current, so as to prevent the coupling point between the fan-out line 31 and the first signal line 30 from being damaged by the transient large current, thereby preventing the display device from having a poor vertical and dark line when the display substrate is applied to the display device. In addition, the first electrostatic protection circuit 40 releases large-current static electricity, and also prevents a large current from directly striking several rows of driving transistors close to the peripheral area in the display area 10, thereby preventing a part of sub-pixels from forming poor bright and dark spots due to short circuit of the source and drain electrodes of the driving transistors.

Referring to fig. 1 and 2, in some embodiments, the display substrate further includes:

a plurality of conductive connection parts 50, the conductive connection parts 50 being coupled with the corresponding target fanout line 310 and the corresponding first signal line 30, respectively; the orthographic projection of the first electrostatic protection circuit 40 on the substrate 70 of the display substrate is positioned on one side, away from the display area 10, of the orthographic projection of the conductive connecting part 50 on the substrate 70.

Illustratively, the display substrate further includes a plurality of sub-pixels distributed in an array, where the sub-pixels include a pixel electrode and a common electrode stacked on each other, and the common electrode is located between the substrate 70 and the pixel electrode. Illustratively, the common electrode is made of a first indium tin oxide layer, and the pixel electrode is made of a second indium tin oxide layer. Illustratively, the pixel electrode is provided with a plurality of slits.

Illustratively, the conductive connection 50 is made using a second indium tin oxide layer.

Illustratively, the conductive connection portions 50 correspond to the target fanning-out lines 310 included in the fanning-out lines 31 one by one, and correspond to the first signal lines 30 corresponding to the target fanning-out lines 310 one by one. An orthogonal projection of the conductive connection portion 50 on the substrate 70 at least partially overlaps an orthogonal projection of the corresponding target fanout line 310 on the substrate 70, and the conductive connection portion 50 and the corresponding target fanout line 310 are coupled at the overlap through at least one first transfer hole 541. An orthogonal projection of the conductive connection portion 50 on the substrate 70 at least partially overlaps an orthogonal projection of the corresponding first signal line 30 on the substrate 70, and the conductive connection portion 50 and the corresponding first signal line 30 are coupled at the overlap through at least one second transfer hole 542.

The orthographic projection of the first electrostatic protection circuit 40 on the substrate 70 is located on one side of the orthographic projection of the conductive connecting part 50 on the substrate 70, which is far away from the display area 10, so that when the static electricity with large current passes through the first electrostatic protection circuit 40, the first electrostatic protection circuit 40 can release the static electricity with large current, and the first transfer hole 541 and the second transfer hole 542 are prevented from being damaged by the transient large current, thereby preventing the display device from having poor vertical and dark lines when the display substrate is applied to the display device.

As shown in fig. 1 and 2, in some embodiments, the display substrate further includes a common signal line 51; the first electrostatic protection circuit 40 includes:

a first transistor T1, a gate T1-g of the first transistor T1 being coupled to the common signal line 51, a first pole T1-1 of the first transistor T1 being coupled to the corresponding fanout line 31, a second pole T1-2 of the first transistor T1 being coupled to the common signal line 51;

a second transistor T2, wherein a gate T2-g of the second transistor T2 is coupled to the corresponding fanout line 31, a first pole T2-1 of the second transistor T2 is coupled to the corresponding fanout line 31, and a second pole T2-2 of the second transistor T2 is coupled to the common signal line 51.

Note that an active layer T1-3 of the first transistor and an active layer T2-3 of the second transistor are also illustrated in fig. 1 and 2.

Illustratively, the common signal line 51 is loaded with the same common signal as the common electrode.

Illustratively, an orthographic projection of the channel of the first transistor T1 on the substrate 70 is located between the display area 10 and an orthographic projection of the channel of the second transistor T2 on the substrate 70.

For example, when a large amount of static electricity passes through the first electrostatic discharge protection circuit 40, the second transistor T2 is turned on first, and the static electricity is discharged to the common signal line 51. If the current of the static electricity is large enough, after being discharged through the first transistor T1, a part of the static electricity is still transmitted to the first transistor T1, and the part of the static electricity can be discharged to the common signal line 51 through the first transistor T1.

For example, in the first electrostatic protection circuit 40 corresponding to the target fanout line 310, the first pole T1-1 of the first transistor T1 may be coupled to the corresponding target fanout line 310 through a first strapping pattern 551, and the second electrode of the first transistor T1 may be coupled to the common signal line 51 through a second strapping pattern 552; the first pole T2-1 of the second transistor T2 is coupled to the corresponding target fanout line 310 through a third strapping pattern 553, and the second pole T2-2 of the second transistor T2 is coupled to the common signal line 51 through the second strapping pattern 552. The gate T2-g of the second transistor T2 is formed as an integral structure with the corresponding target fanout line 310.

For example, in the first electrostatic protection circuit 40 corresponding to the non-target fanout line 311, the first electrode T1-1 of the first transistor T1 may be formed as an integral structure with the corresponding non-target fanout line 311, and the second electrode of the first transistor T1 may be coupled to the common signal line 51 through a fourth strapping pattern 554; the first pole T2-1 of the second transistor T2 is formed as an integral structure with the corresponding non-target fanout line 311, and the second pole T2-2 of the second transistor T2 is coupled to the common signal line 51 through the fourth crossover pattern 554. The gate T2-g of the second transistor T2 is coupled to the first pole T2-1 of the second transistor T2 through a fifth strap pattern 555.

Illustratively, the common signal line 51 includes a first common pattern and a second common pattern alternately arranged, and adjacent first common patterns and second common patterns are coupled. The first common pattern and the target fanout line 310 are arranged in the same layer and the same material, and an orthographic projection of the first common pattern on the substrate 70 is not overlapped with an orthographic projection of the target fanout line 310 on the substrate 70. The second common pattern is made of the second ito layer, an orthographic projection of the second common pattern on the substrate 70 is partially overlapped with an orthographic projection of the target fanout line 310 on the substrate 70, and the second common pattern can cross over the target fanout line 310, so that the first common patterns on two sides of the target fanout line 310 are electrically connected.

Will first electrostatic protection circuit 40 sets up to above-mentioned structure, has realized first electrostatic protection circuit 40 still has simple structure when guaranteeing good electrostatic protection effect, is favorable to reducing first electrostatic protection circuit 40's the overall arrangement degree of difficulty.

As shown in fig. 3 to 5, in some embodiments, the display substrate further includes:

a bonding region, the fan-out region 21 being located between the display region 10 and the bonding region;

a plurality of second esd protection circuits 41, the second esd protection circuits 41 are coupled to the corresponding fanout lines 31, and the second esd protection circuits 41 are located between the first esd protection circuits 40 and the binding regions, and are configured to release static electricity on the fanout lines 31.

Illustratively, the orthographic projection of the second electrostatic protection circuit 41 on the substrate 70 is located between the orthographic projection of the first electrostatic protection circuit 40 on the substrate 70 and the orthographic projection of the bonding region on the substrate 70.

The second ESD protection circuit 41 is disposed between the first ESD protection circuit 40 and the binding region, so that the second ESD protection circuit 41 and the first ESD protection circuit 40 can be combined to form a novel ESD electrostatic ring unit, and the novel ESD electrostatic ring unit has an effect of releasing static electricity accumulated in the screen and can resist a large transient current.

As shown in fig. 3 to 5, in some embodiments, the second electrostatic protection circuit 41 includes: at least one third transistor T3, the at least one third transistor T3 is arranged along the extending direction of the corresponding fan-out line 31 of the second electrostatic protection circuit 41, and the gate T3-g, the first pole T3-1 and the second pole T3-2 of the third transistor T3 are all coupled to the corresponding fan-out line 31.

Note that fig. 3 to 5 also illustrate an active layer T3-3 of the third transistor T3.

Illustratively, in the third transistor T3 coupled to the non-target fan-out line 311, the gate T3-g of the third transistor T3 is coupled to the second pole T3-2 of the third transistor T3 through a sixth strapping pattern 556, and the first pole T3-1 of the third transistor T3 is formed as an integral structure with the non-target fan-out line 311.

Illustratively, in the third transistor T3 coupled to the target fan-out line 310, the gate T3-g of the third transistor T3 is coupled to the second pole T3-2 of the third transistor T3 through a seventh strapping pattern 557, and the first pole T3-1 of the third transistor T3 is coupled to the target fan-out line 310 through an eighth strapping pattern 558.

When the static electricity is discharged through the third transistor T3, the third transistor T3 is electrostatically broken down.

The second esd protection circuit 41 is configured to include at least one third transistor T3, so that the second esd protection circuit 41 has a simple structure while ensuring a good esd protection effect, and the second esd protection circuit 41 does not occupy too much space of the fan-out area 21, which is beneficial to reducing the layout difficulty of the second esd protection circuit 41.

As shown in fig. 3 to 5, in some embodiments, the second electrostatic protection circuit 41 includes: a plurality of third transistors T3, a channel width-to-length ratio of the plurality of third transistors T3 becoming gradually smaller in a direction in which the fan-out region 21 points to the binding region.

Illustratively, at least two of the third transistors T3 among the plurality of third transistors T3 have different channel width to length ratios.

The second electrostatic protection circuit 41 is configured to include the plurality of third transistors T3, so that the plurality of third transistors T3 can serve as a sacrificial point where a large-current electrostatic signal flowing from the binding region breaks down first, thereby protecting other functional structures of the third transistor T3 toward the display region 10 side.

The channel width-length ratios of the third transistors T3 are gradually decreased, so that the difficulty of electrostatic breakdown of the third transistors T3 is distributed in a stepwise manner, and the electrostatic protection circuit can better correspond to large currents of different electrostatic levels, and has a wider electrostatic range that can be handled by the second electrostatic protection circuit 41.

As shown in fig. 6 and 7, in some embodiments, the display substrate further includes: a plurality of sub-pixels located in the display region 10, the sub-pixels including a driving transistor DTFT; the plurality of third transistors T3 have a channel width to length ratio smaller than that of the driving transistor DTFT.

Illustratively, the sub-pixel further includes a pixel electrode, an output electrode of the driving transistor DTFT is coupled to the pixel electrode, a gate electrode of the driving transistor DTFT is coupled to the corresponding scan line, an input electrode of the driving transistor DTFT is coupled to the corresponding data line, and the driving transistor DTFT is turned on under the control of a scan signal provided by the corresponding scan line to transmit a data signal provided by the corresponding data line to the pixel electrode.

The channel width-to-length ratios of the third transistors T3 are set to be smaller than the channel width-to-length ratio of the driving transistor DTFT, so that the difficulty of breaking down the third transistors T3 is smaller than the difficulty of breaking down the driving transistor DTFT, and the current always selects a path with lower impedance to move, so that the third transistor T3 induces a large current to break down itself first, and consumes most of the energy during the discharging process of static electricity, so that the energy left after the large current is discharged through the third transistor T3 is not enough to damage the switch hole 54 and the driving transistor DTFT.

In some embodiments, the display substrate includes a gate metal layer and a source drain metal layer, the target fanout line 310 and the gate metal layer are disposed on the same layer and the same material, a non-target fanout line 311 of the fanout lines 31 and the source drain metal layer are disposed on the same layer and the same material, and the non-target fanout line 311 and the corresponding first signal line 30 form an integrated structure.

The target fanout line 310 and the gate metal layer are arranged on the same layer and the same material, so that the target fanout line 310 and the gate metal layer can be formed in the same composition process, the manufacturing process flow of the display substrate is simplified, and the manufacturing cost of the display substrate is reduced.

The non-target fanout line 311 in the fanout lines 31 and the source drain metal layer are arranged in the same layer and the same material, so that the non-target fanout line 311 in the fanout lines 31 and the source drain metal layer can be formed in the same composition process, the manufacturing process flow of the display substrate is facilitated to be simplified, and the manufacturing cost of the display substrate is reduced.

The non-target fanout line 311 and the corresponding first signal line 30 are formed into an integrated structure, which is beneficial to improving the reliability of the electrical connection between the non-target fanout line 311 and the first signal line 30.

As shown in fig. 6 and 7, in some embodiments, the display substrate further includes:

a plurality of third esd protection circuits 42, wherein the third esd protection circuits 42 are located between the display area 10 and the fan-out area 21, and the third esd protection circuits 42 are coupled to the corresponding first signal lines 30 for discharging static electricity on the first signal lines 30.

Illustratively, the plurality of third esd protection circuits 42 corresponds to the plurality of first signal lines 30 one by one, and the third esd protection circuits 42 are coupled to the corresponding first signal lines 30.

The third electrostatic protection circuit 42 is coupled to the corresponding first signal line 30, so that the third electrostatic protection circuit 42 can release the high-current static electricity before the high-current static electricity enters the display area 10, the phenomenon that the high-current static electricity directly damages several rows of driving transistors close to the peripheral area in the display area 10 to cause source-drain short circuit is avoided, and the phenomenon that sub-pixels in the display substrate form poor bright and dark spots is avoided.

As shown in fig. 6 and 7, in some embodiments, the display substrate further includes:

a plurality of dummy transistor groups including at least one dummy transistor DUTFT arranged along an extending direction of a first signal line 30 corresponding to the dummy transistor group, a first electrode DUTFT-1 of the dummy transistor DUTFT being coupled to the first signal line 30; a grid electrode DUTFT-g of the virtual transistor DUTFT and a second pole DUTFT-2 of the virtual transistor DUTFT are both suspended; the set of virtual transistors is multiplexed into the third electrostatic protection circuit 42.

Note that an active layer DUTFT-3 of the dummy transistor DUTFT is illustrated in fig. 6 and 7. In fig. 7, the common electrode layer 52 is illustrated and is made of indium tin oxide.

Illustratively, the DUMMY transistor groups are disposed in a DUMMY area 23 of the display substrate, and the DUMMY area 23 is located between the fan-out area 21 and the display area 10.

Illustratively, the dummy transistor group includes a plurality of dummy transistors DUTFT arranged along an extending direction of the first signal line 30 corresponding to the dummy transistor group. Illustratively, the dummy transistor group includes four dummy transistors DUTFT.

Illustratively, the dummy transistor DUTFT includes a complete gate, source and drain, and is capable of absorbing ESD charges to form a source-drain breakdown. Illustratively, the dummy transistor DUTFT is identical in structure to the driving transistor. Illustratively, the dummy transistor dutf is identical in structure to the third transistor T3. Illustratively, the structure of the dummy transistor group is the same as the structure of the first electrostatic protection circuit 40.

After static electricity enters the DUMMY region 23 from the fan-out region 21, the energy is greatly attenuated after being absorbed by the DUMMY transistors DUTFT, thereby protecting the driving transistors in the display region 10.

In some embodiments, the dummy transistor group includes a plurality of dummy transistors DUTFT, and a channel width-to-length ratio of the plurality of dummy transistors DUTFT gradually becomes smaller in a direction in which the display region 10 is directed to the fan-out region 21.

Illustratively, the channel width-to-length ratio of the dummy transistor DUTFT includes 17 μm/2.3 μm.

Illustratively, the area of the active layer of the dummy transistors DUTFT comprises 17.35 × 15.55 μm²。

Through setting up the channel width length ratio of a plurality of virtual transistor DUTFT diminishes gradually for a plurality of virtual transistor DUTFT antistatic breakdown difficult degree becomes cascaded distribution, the heavy current of different static grades of correspondence that can be better.

In some embodiments, the display substrate further comprises:

and a plurality of sub-pixels located in the display region 10, the sub-pixels including driving transistors having a channel width-to-length ratio greater than that of a portion of the dummy transistors DUTFT and less than that of another portion of the dummy transistors DUTFT.

Since the breakdown voltage of the TFT is proportional to the length L of the channel and has no correlation with the width W of the channel, when the DUMMY transistor DUTFT in the DUMMY region 23 is designed with a gradually changing channel length, the channel lengths of the plurality of DUMMY transistors DUTFT may be set in stages with the channel length of the driving transistor as a center point within the range of the exposure process capability. Illustratively, the channel length range of the dummy transistors DUTFT may be distributed in a range of 1 μm to 4 μm. Considering that the dummy transistors dutf exist as a point of inducing ESD discharge, a step distribution design in which channel lengths of the plurality of dummy transistors dutf are sequentially 1 μm, 1 μm, 3 μm, and 4 μm may be set to correspond to different levels of static electricity, respectively. Illustratively, the channel length of the drive transistor comprises 2.3 μm. Illustratively, the channel length of the transistors in the first electrostatic protection circuit 40 comprises 12 μm.

In the display substrate provided by the above embodiment, on the basis of the alternate wiring design of the narrow-frame fan-out region 21, the transistors with different breakdown weak degrees are added to the switching hole 54 of the fan-out region 21 and the front end of the driving transistor of the display region 10 to serve as the breakdown sacrificial point, and the first electrostatic protection circuit 40 is arranged in the fan-out region 21, so that the static large-current prevention capability of the fan-out region 21 and the display region 10 is effectively enhanced, the occurrence rate of vertical lines and bright and dark points is reduced, the product quality is improved, and the margin of the process is increased.

It should be noted that all the dummy transistors DUTFT and the novel electrostatic ring are designed with the same film layer preparation process flow and the same as the existing product preparation process, so the utility model does not need to additionally add a mask process, and the design is changed on the basis of the existing process to enhance the ability of the fan-out area 21 and the display area 10 to prevent static heavy current, and the production cost is not additionally increased.

It is worth noting that the preparation process flow sequentially comprises: manufacturing a gate metal layer, a gate insulating layer GI, an active layer, a source drain metal layer, a passivation layer PVX and an indium tin oxide layer. The gate metal layer is used to make the gate of the transistor and a portion of the common signal line 51. The active layer is capable of forming a channel of a transistor. The source and drain metal layers are used for forming a source electrode and a drain electrode of the transistor. The passivation layer PVX is used to protect the underlying film layers that it covers. The indium tin oxide layer is used to make the conductive connection 50 and another portion of the common signal line 51.

The embodiment of the utility model also provides a display device which comprises the display substrate provided by the embodiment.

In the display substrate provided in the above embodiment, the first electrostatic protection circuit 40 is disposed in the fan-out region 21, and the first electrostatic protection circuit 40 is coupled to the corresponding fan-out line 31, so that the large-current static electricity enters the fan-out line 31 from the driving chip, first passes through the first electrostatic protection circuit 40, then passes through the position where the fan-out line 31 is coupled to the first signal line 30, and then enters the first signal line 30. Therefore, in the display substrate provided in the above embodiment, when the static electricity with a large current passes through the first static electricity protection circuit 40, the first static electricity protection circuit 40 can release the static electricity with a large current, so as to avoid that the coupling point of the fan-out line 31 and the first signal line 30 is damaged by the transient large current, thereby avoiding that the display device has a poor vertical and dark line when the display substrate is applied to the display device. In addition, the first electrostatic protection circuit 40 releases large-current static electricity, and also prevents a large current from directly striking several rows of driving transistors close to the peripheral area in the display area 10, thereby preventing a part of sub-pixels from forming poor bright and dark spots due to short circuit of the source and drain electrodes of the driving transistors.

The display device provided by the embodiment of the utility model has the beneficial effects when the display device comprises the display substrate, and the description is omitted.

The display device may be: the display device comprises a television, a display, a digital photo frame, a mobile phone, a tablet personal computer and any other product or component with a display function, wherein the display device further comprises a flexible circuit board, a printed circuit board, a back plate and the like.

In some embodiments, the display device further includes an opposite substrate 60 and a liquid crystal layer, the opposite substrate 60 is disposed opposite to the display substrate, and the liquid crystal layer is disposed between the display substrate and the opposite substrate 60.

Illustratively, the opposite substrate 60 includes a color filter substrate. The counter substrate 60 is provided with a black matrix BM.

It should be noted that "same layer" in the embodiments of the present invention may refer to a film layer on the same structural layer. Or, for example, the film layer on the same layer may be a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then patterning the film layer by using the same mask plate through a one-time patterning process. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

In the embodiments of the methods of the present invention, the sequence numbers of the steps are not used to limit the sequence of the steps, and for those skilled in the art, the sequence of the steps is not changed without creative efforts.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (14)

1. A display substrate, comprising: a display area and a peripheral area surrounding the display area, the peripheral area including a fan-out region; the display substrate further includes:

a plurality of first signal lines extending from the display region to the peripheral region;

the fan-out lines are positioned in the fan-out area; the fan-out lines are coupled with the corresponding first signal lines; the multiple fan-out lines comprise multiple target fan-out lines, and the target fan-out lines and the first signal lines coupled with the target fan-out lines are arranged in different layers;

the first electrostatic protection circuits are located in the fan-out area and coupled with the corresponding fan-out lines and used for releasing static electricity on the fan-out lines.

2. The display substrate of claim 1, further comprising:

a plurality of conductive connection portions coupled to the corresponding target fanout line and the corresponding first signal line, respectively; the orthographic projection of the first electrostatic protection circuit on the substrate of the display substrate is positioned on one side, away from the display area, of the orthographic projection of the conductive connecting part on the substrate.

3. The display substrate according to claim 1, wherein the display substrate further comprises a common signal line; the first electrostatic protection circuit includes:

a first transistor, a gate of which is coupled to the common signal line, a first pole of which is coupled to the corresponding fanout line, and a second pole of which is coupled to the common signal line;

and the grid electrode of the second transistor is coupled with the corresponding fanout line, the first pole of the second transistor is coupled with the corresponding fanout line, and the second pole of the second transistor is coupled with the common signal line.

4. The display substrate of claim 1, further comprising:

a bonding region, the fan-out region being located between the display region and the bonding region;

the second electrostatic protection circuits are coupled with the corresponding fan-out lines, and the second electrostatic protection circuits are located between the first electrostatic protection circuits and the binding regions and used for releasing static electricity on the fan-out lines.

5. The display substrate of claim 4, wherein the second electrostatic protection circuit comprises: the at least one third transistor is arranged along the extending direction of the fan-out line corresponding to the second electrostatic protection circuit, and the grid electrode, the first pole and the second pole of the third transistor are coupled with the corresponding fan-out line.

6. The display substrate of claim 5, wherein the second electrostatic protection circuit comprises: a plurality of third transistors whose channel width-to-length ratios become gradually smaller in a direction in which the fan-out region points to the bonding region.

7. The display substrate of claim 6, further comprising: a plurality of sub-pixels located in the display area, the sub-pixels including a driving transistor; the channel width-to-length ratios of the plurality of third transistors are smaller than the channel width-to-length ratio of the driving transistor.

8. The display substrate of claim 1, wherein the display substrate comprises a gate metal layer and a source drain metal layer, the target fanout line and the gate metal layer are arranged on the same layer and the same material, a non-target fanout line of the plurality of fanout lines and the source drain metal layer are arranged on the same layer and the same material, and the non-target fanout line and a corresponding first signal line form an integrated structure.

9. The display substrate of claim 1, further comprising:

a plurality of third ESD protection circuits, the third ESD protection circuits being located between the display area and the fan-out area, the third ESD protection circuits being coupled to the corresponding first signal lines for discharging static electricity on the first signal lines.

10. The display substrate of claim 9, further comprising:

the array circuit comprises a plurality of virtual transistor groups, a plurality of first control circuits and a plurality of second control circuits, wherein each virtual transistor group comprises at least one virtual transistor which is arranged along the extending direction of a first signal line corresponding to the virtual transistor group, and a first pole of each virtual transistor is coupled with the first signal line; the grid electrode of the virtual transistor and the second pole of the virtual transistor are both suspended;

and the virtual transistor group is multiplexed as the third electrostatic protection circuit.

11. The display substrate of claim 10, wherein the set of dummy transistors comprises a plurality of dummy transistors having a gradually decreasing channel width-to-length ratio along a direction in which the display area points to the fan-out region.

12. The display substrate of claim 11, further comprising:

the sub-pixels are positioned in the display area and comprise driving transistors, and the channel width-length ratio of the driving transistors is larger than that of one part of the virtual transistors and smaller than that of the other part of the virtual transistors.

13. A display device comprising the display substrate according to any one of claims 1 to 12.

14. The display device according to claim 13, further comprising an opposing substrate disposed opposite to the display substrate, and a liquid crystal layer between the display substrate and the opposing substrate.

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