CN215871406U - RS485 relay circuit - Google Patents
RS485 relay circuit Download PDFInfo
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- CN215871406U CN215871406U CN202121783374.7U CN202121783374U CN215871406U CN 215871406 U CN215871406 U CN 215871406U CN 202121783374 U CN202121783374 U CN 202121783374U CN 215871406 U CN215871406 U CN 215871406U
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Abstract
The utility model provides an RS485 relay circuit, wherein a first pin of an RS485 bus transceiver circuit is connected with a first pin of a first received signal filtering delay circuit, a second pin of the RS485 bus transceiver circuit is connected with a first pin of a signal sending control circuit, a third pin of the RS485 bus transceiver circuit is connected with a second pin of the signal sending control circuit, and a fourth pin of the RS485 bus transceiver circuit is connected with a first pin of a second received signal filtering delay circuit; the second pin of the first received signal filtering delay circuit is connected with the third pin of the sending signal control circuit, and the second pin of the second received signal filtering delay circuit is connected with the fourth pin of the sending signal control circuit. The utility model adopts the logic gate circuit to generate the low-delay control signal, thereby ensuring the safe transmission of the RS485 bus data.
Description
Technical Field
The utility model relates to the technical field of communication, in particular to an RS485 relay circuit, and particularly relates to an RS485 relay circuit with low cost, low time delay and high reliability.
Background
A repeater is a device for connecting network lines, and is often used for bidirectional forwarding of physical signals between two network nodes, so as to extend the transmission distance of the network by retransmitting or forwarding data signals. The RS485 repeater is a data relay communication product of an RS485 bus, can relay and prolong the communication distance of an RS485 bus network, enhances the number of RS485 bus network devices, and has application in the fields of industrial control automation, industrial distributed distribution systems, road traffic control automation and the like.
With the continuous improvement of the requirement of field control precision and the expansion of data network equipment sites, the data flow, the system range and the scale are continuously expanded, the stability, the integrity and the safety of field network data are ensured to become more important, and the method is directly related to the field production and control conditions.
Patent document No. CN205092859U discloses an RS485 relay circuit including: the device comprises a PLD for receiving and processing data and sending control signals, a data transmission circuit for data input and output, an optical coupling isolation unit for preventing common-mode voltage interference, an RS485 interface communication chip set for RS485 protocol communication between data transceivers, and a dial switch set for switching data transmission modes and adjusting data communication rates. The optical coupling isolation unit is connected with the PLD, the RS485 interface communication chip set is connected between the optical coupling isolation unit and the data transmission circuit and connected with the PLD, and the dial switch set is connected with the RS485 interface communication set and the PLD. However, the patent document still has the defects of incomplete data signals and high time delay.
SUMMERY OF THE UTILITY MODEL
Aiming at the defects in the prior art, the utility model aims to provide an RS485 relay circuit.
The RS485 relay circuit provided by the utility model comprises an RS485 bus transceiver circuit, a first received signal filtering delay circuit, a second received signal filtering delay circuit and a transmitted signal control circuit;
a first pin of the RS485 bus transceiver circuit is connected with a first pin of the first received signal filtering delay circuit, a second pin of the RS485 bus transceiver circuit is connected with a first pin of the transmitted signal control circuit, a third pin of the RS485 bus transceiver circuit is connected with a second pin of the transmitted signal control circuit, and a fourth pin of the RS485 bus transceiver circuit is connected with a first pin of the second received signal filtering delay circuit;
and a second pin of the first received signal filtering delay circuit is connected with a third pin of the sending signal control circuit, and a second pin of the second received signal filtering delay circuit is connected with a fourth pin of the sending signal control circuit.
Preferably, the RS485 bus transceiver circuit comprises an RS485 transceiver U3 and an RS485 transceiver U6, and the RS485 transceiver U3 and the RS485 transceiver U6 are used for receiving and transmitting data of two buses.
Preferably, the first received signal filtering delay circuit comprises a schmitt input nor gate U1D, a schmitt input nor gate U2D, a schmitt input nor gate U2E, a schmitt input nor gate U2F, a filtering delay resistor R1 and a capacitor C1;
a first input end of the Schmidt input NOR gate U1D is connected with a second pin of the first received signal filtering delay circuit, and a second input end of the Schmidt input NOR gate U1D is grounded;
the output end of the schmitt input nor gate U1D is connected to one end of the filter delay resistor R1, and the other end of the filter delay resistor R1 is connected to one end of the capacitor C1 and the input end of the schmitt input nor gate U2F, respectively;
the other end of the capacitor C1 is grounded;
the output end of the Schmitt input NOT gate U2F is connected with the input end of the Schmitt input NOT gate U2E, and the output end of the Schmitt input NOT gate U2E is connected with the input end of the Schmitt input NOT gate U2D;
the output end of the Schmitt input NOT gate U2D is connected with the first pin of the first received signal filtering delay circuit.
Preferably, the schmidt input nor gate U1D is model SN74HC 7002N.
Preferably, the schmidt input not gate U2D is SN74HC14D, the schmidt input not gate U2E is SN74HC14D, and the schmidt input not gate U2F is SN74HC 14D.
Preferably, the second received signal filtering and delaying circuit comprises a schmitt input nor gate U1A, a schmitt input nor gate U2A, a schmitt input nor gate U2B, a schmitt input nor gate U2C, a filtering and delaying circuit R12 and a capacitor C8;
a first input end of the Schmidt input NOR gate U1A is connected with a second pin of the second received signal filtering delay circuit, and a second input end of the Schmidt input NOR gate U1A is grounded;
the output end of the schmitt input nor gate U1A is connected to one end of the filter delay resistor R12, and the other end of the filter delay resistor R12 is connected to one end of the capacitor C8 and the input end of the schmitt input nor gate U2A, respectively;
the other end of the capacitor C8 is grounded;
the output end of the Schmitt input NOT gate U2A is connected with the input end of the Schmitt input NOT gate U2B, and the output end of the Schmitt input NOT gate U2B is connected with the input end of the Schmitt input NOT gate U2C;
the output end of the Schmitt input NOT gate U2C is connected with the first pin of the second received signal filtering delay circuit.
Preferably, the schmidt input nor gate U1A is model SN74HC 7002N.
Preferably, the schmidt input not gate U2A is SN74HC14D, the schmidt input not gate U2B is SN74HC14D, and the schmidt input not gate U2C is SN74HC 14D.
Preferably, the transmission signal control circuit includes a monostable flip-flop U4A, a monostable flip-flop U4B, an and gate U5A, an and gate U5B, a schmidt input nor gate U1B, a schmidt input nor gate U1C, a delay circuit R6, a capacitor C4, a delay resistor R7, a capacitor C6, a delay resistor R2, a capacitor C3, a delay resistor R9, and a capacitor C7;
a first pin of the monostable flip-flop U4A is connected to a first input terminal of the schmitt input nor gate U1B, one end of the delay resistor R7, one end of the capacitor C6, and a fourth pin of the transmission signal control circuit, respectively;
a second pin of the monostable flip-flop U4A is respectively connected with a first input end of the AND gate U5A;
a third pin of the monostable flip-flop U4A is respectively connected with one end of the delay resistor R9 and one end of the capacitor C7;
the other end of the delay resistor R7 is connected with an external voltage, and the other end of the capacitor C6 is grounded;
the other end of the delay resistor R9 is connected with an external voltage, and the other end of the capacitor C7 is grounded;
a first pin of the monostable flip-flop U4B is respectively connected with a first input end of the Schmidt input NOR gate U1C, one end of the delay resistor R6, one end of the capacitor C4 and a third pin of the transmission signal control circuit;
a second pin of the monostable flip-flop U4B is respectively connected with a first input end of the AND gate U5B;
a third pin of the monostable flip-flop U4A is respectively connected with one end of the delay resistor R2 and one end of the capacitor C3;
the other end of the delay resistor R6 is connected with an external voltage, and the other end of the capacitor C4 is grounded;
the other end of the delay resistor R2 is connected with an external voltage, and the other end of the capacitor C3 is grounded;
a second input end of the schmitt input nor gate U1B is respectively connected with an output end of the schmitt input nor gate U1C and a second input end of the and gate U5B; the output end of the schmitt input nor gate U1B is respectively connected with the second input end of the schmitt input nor gate U1C and the second input end of the and gate U5A;
the output end of the AND gate U5A is connected with the second pin of the sending signal control circuit, and the output end of the AND gate U5B is connected with the first pin of the sending signal control circuit.
Preferably, the model of the monostable flip-flop U4A is DM74LS123M, and the model of the monostable flip-flop U4B is DM74LS 123M;
the model of the AND gate U5A is SN74HC08D, and the model of the AND gate U5B is SN74HC 08D;
the Schmidt input NOR gate U1B is SN74HC7002N, and the Schmidt input NOR gate U1C is SN74HC 7002N.
Compared with the prior art, the utility model has the following beneficial effects:
1. according to the utility model, two received signal filtering delay circuits are adopted to delay received signals, and the time sequence control is carried out on the transmission control signals DE-1 and DE-2 of the RS485 transceiver by the delay resistor R6, the capacitor C4, the delay resistor R7 and the capacitor C6, so that the integrity and low time delay of data signals are ensured;
2. by adopting the monostable trigger, the problem that the whole network of the RS485 branch bus fails for a long time due to the bus failure assembly is solved, and the stability is improved;
3. the utility model is realized by adopting a logic gate circuit without adopting an MCU control mode, thereby reducing the cost.
Drawings
Other features, objects and advantages of the utility model will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of the structure of an RS485 relay circuit of the present invention;
fig. 2 is a schematic diagram of an RS485 relay circuit of the present invention.
The figures show that:
second receiving signal filtering delay circuit 2B of RS485 bus transceiver circuit 1
First received signal filtering delay circuit 2A sends signal control circuit 4
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the utility model, but are not intended to limit the utility model in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the utility model. All falling within the scope of the present invention.
As shown in fig. 1 and fig. 2, an RS485 relay circuit provided by the present invention includes an RS485 bus transceiver circuit, a first received signal filtering delay circuit, the first pin of the RS485 bus transceiver circuit is connected with the first pin of the first received signal filtering delay circuit, the second pin of the RS485 bus transceiver circuit is connected with the first pin of the transmitted signal control circuit, the third pin of the RS485 bus transceiver circuit is connected with the second pin of the transmitted signal control circuit, the fourth pin of the RS485 bus transceiver circuit is connected with the first pin of the second received signal filtering delay circuit, the second pin of the first received signal filtering delay circuit is connected with the third pin of the transmitted signal control circuit, and the second pin of the second received signal filtering delay circuit is connected with the fourth pin of the transmitted signal control circuit. The RS485 bus transceiver circuit comprises an RS485 transceiver U3 and an RS485 transceiver U6, and the RS485 transceiver U3 and the RS485 transceiver U6 are used for receiving and transmitting data of two buses.
The sending signal control circuit comprises a monostable trigger U4A, a monostable trigger U4B, an AND gate U5A, an AND gate U5B, a Schmidt input NOR gate U1B, a Schmidt input NOR gate U1C, a delay circuit R6, a capacitor C4, a delay resistor R7, a capacitor C6, a delay resistor R2, a capacitor C3, a delay resistor R9 and a capacitor C7, a first pin of the monostable trigger U4A is respectively connected with a first input terminal of the Schmidt input NOR gate U1B, one end of a delay resistor R7, one end of a capacitor C6 and a fourth pin of the sending signal control circuit, a second pin of the monostable trigger U4A is respectively connected with a first input terminal of the AND gate U5A, a third pin of the monostable trigger U4A is respectively connected with one end of the delay resistor R A and one end of the capacitor C A, the other end of the delay resistor R A is connected with the external voltage of the delay resistor R A, and the other end of the delay resistor R A is connected with the external ground, the delay resistor C A and the external voltage of the delay resistor C A is connected with the external ground, a first pin of a monostable flip-flop U4B is respectively connected to a first input terminal of a Schmidt input NOR gate U1C, one end of a delay resistor R6, one end of a capacitor C4 and a third pin of a transmission signal control circuit, a second pin of the monostable flip-flop U4B is respectively connected to a first input terminal of an AND gate U5B, a third pin of a monostable flip-flop U4A is respectively connected to one end of a delay resistor R2 and one end of a capacitor C3, the other end of the delay resistor R6 is connected to an external voltage, the other end of the capacitor C4 is grounded, the other end of the delay resistor R2 is connected to an external voltage, the other end of the capacitor C3 is grounded, a second input terminal of the Schmidt input NOR gate U1B is respectively connected to an output terminal of the Schmidt input NOR gate U1C and a second input terminal of the AND gate U5B, output terminals of the Schmidt input NOR gate U1B are respectively connected to a second input terminal of the Schmidt input NOR gate U1C and a second input terminal of the AND gate U5A, the output end of the AND gate U5A is connected with the second pin of the sending signal control circuit, and the output end of the AND gate U5B is connected with the first pin of the sending signal control circuit. The model of the monostable flip-flop U4A is DM74LS123M, the model of the monostable flip-flop U4B is DM74LS123M, the model of the AND gate U5A is SN74HC08D, the model of the AND gate U5B is SN74HC08D, the model of the Schmidt input NOR gate U1B is SN74HC7002N, and the model of the Schmidt input NOR gate U1C is SN74HC 7002N.
The first received signal filtering delay circuit comprises a Schmidt input NOR gate U1D, a Schmidt input NOR gate U2D, a Schmidt input NOR gate U2E, a Schmidt input NOR gate U2F, a filtering delay resistor R1 and a capacitor C1, the first input end of the Schmidt input NOR gate U1D is connected with the second pin of the first receiving signal filtering delay circuit, the second input end of the Schmidt input NOR gate U1D is grounded, the output end of the Schmidt input NOR gate U1D is connected with one end of a filtering delay resistor R1, the other end of the filtering delay resistor R1 is connected with one end of a capacitor C1 and the input end of the Schmidt input NOR gate U2F respectively, the other end of the capacitor C1 is grounded, the output end of the Schmidt input NOR gate U2F is connected with the input end of the Schmidt input NOR gate U2E, the output end of the Schmidt input NOR gate U2E is connected with the input end of the Schmidt input NOR gate U2D, and the output end of the Schmidt input NOR gate U2D is connected with the first pin of the first receiving signal filtering delay circuit. The schmidt input nor gate U1D has a model number SN74HC7002N, the schmidt input nor gate U2D has a model number SN74HC14D, the schmidt input nor gate U2E has a model number SN74HC14D, and the schmidt input nor gate U2F has a model number SN74HC 14D.
The second received signal filtering delay circuit comprises a Schmidt input NOR gate U1A, a Schmidt input NOR gate U2A, a Schmidt input NOR gate U2B, a Schmidt input NOR gate U2C, a filtering delay circuit R12 and a capacitor C8, the first input end of the Schmidt input NOR gate U1A is connected with the second pin of the second receiving signal filtering delay circuit, the second input end of the Schmidt input NOR gate U1A is grounded, the output end of the Schmidt input NOR gate U1A is connected with one end of a filtering delay resistor R12, the other end of the filtering delay resistor R12 is connected with one end of a capacitor C8 and the input end of the Schmidt input NOR gate U2A respectively, the other end of the capacitor C8 is grounded, the output end of the Schmidt input NOR gate U2A is connected with the input end of the Schmidt input NOR gate U2B, the output end of the Schmidt input NOR gate U2B is connected with the input end of the Schmidt input NOR gate U2C, and the output end of the Schmidt input NOR gate U2C is connected with the first pin of the second receiving signal filtering delay circuit. The schmidt input nor gate U1A has a model number SN74HC7002N, the schmidt input nor gate U2A has a model number SN74HC14D, the schmidt input nor gate U2B has a model number SN74HC14D, and the schmidt input nor gate U2C has a model number SN74HC 14D.
Example (b):
an RS485 repeater, comprising: the RS485 bus transceiver circuit 1, the receiving signal filtering delay circuits 2A and 2B, and the sending signal control circuit 3. Wherein, the RS485 transceivers U3 and U6 are respectively connected with 2 external RS485 communication buses (BUS-1 and BUS-2).
The RS485 bus transceiver circuit 1 includes: and the 2 RS485 transceivers are responsible for receiving and transmitting data of the 2 buses.
The receiving signal RXD-1 of the RS485 transceiver U3 is connected with the pin 1 of U1A in the signal receiving filter delay circuit 2B, and the RXD-1 is also connected with the pin 1 of U4A in the sending signal control circuit 3. The transmitting signal TXD-1 of the RS485 transceiver U3 is connected to pin 8 of U2D in the signal receiving filter delay circuit 2A. The transmission control signal DE-1 of the RS485 transceiver U3 is connected to pin 6 of U5B in the transmission signal control circuit 3.
The receiving signal RXD-2 of the RS485 transceiver U6 is connected with the pin 12 of U1D in the signal receiving filter delay circuit 2A, and the RXD-2 is also connected with the pin 9 of U4B in the sending signal control circuit 3. The transmitting signal TXD-2 of the RS485 transceiver U6 is connected with the pin 6 of the U2C in the signal receiving filter delay circuit 2B. The transmission control signal DE-2 of the RS485 transceiver U6 is connected to pin 3 of U5A in the transmission control circuit 3.
The received signal filtering delay circuit 2A includes: 1 schmitt input nor gate U1D (SN74HC7002N), 3 schmitt input nor gates U2D, U2E, U2F (SN74HC14D), and filter delay circuits R1 and C1, resulting in a delay of 1 us. Since pin 13 of U1D is 0 (hereinafter, low level is abbreviated as 0, and high level is abbreviated as 1), the state of U1D is determined by the state of pin 12, and it becomes a not gate. When RXD-2 (pin 12 of U1D) is 0, the output pin 11 of U1D is 1, C1 is charged through R1, when the voltage of C1 exceeds the threshold voltage (1.9V) of U2F, the output of U2F is 0, and the output after passing through U2E and U2D is 0. When pin 12 of U1D is 1 and pin 11 of U1D is 0, C1 is discharged through R1, and when the voltage of C1 is lower than the threshold voltage (1.2V) of U2F, the output of U2F is 1 and the output after passing through U2E and U2D is 1.
The received signal filtering delay circuit 2B includes: 1 schmitt input nor gate U1A (SN74HC7002N), 3 schmitt input nor gates U2A, U2B, U2C (SN74HC14D), and filter delay circuits R12 and C8, resulting in a delay of 1 us. The control principle is the same as that of the received signal filtering delay circuit 2A.
The transmission signal control circuit 3 includes: 2 retriably-triggerable monostable flip-flops U4A, U4B (DM74LS123M), 2 AND gates U5A, U5B (SN74HC08D), 2 RS flip-flops composed of Schmitt input NOR gates U1B and U1C (SN74HC7002N), delay circuits R6 and C4 (generating a delay of 40 us), delay circuits R7 and C6 (generating a delay of 40 us), delay circuits R2 and C3 (generating a delay of 2.5 s), and delay circuits R9 and C7 (generating a delay of 2.5 s).
The working principle is as follows:
under the condition of initial power-on, when 2 RS485 buses have no data, RXD-1 and RXD-2 are both 1, at this time, the low-level input pins A (pin 1 of U4A and pin 9 of U4B) of the monostable flip-flops U4A and U4B are also 1, and since the input pins B (pin 2 of U4A and pin 10 of U4B) of the monostable flip-flops U4A and U4B and the reset pin CLR (pin 3 of U4A and pin 11 of U4B) are both switched into high level, the monostable flip-flop output Q (pin 13 of U4A and pin 5 of U4B) is 0. Capacitors C4 and C6 are at high level after being charged for 40us for a short time through resistors, so that the inputs (pin 4 of U1B and pin 10 of U1C) of the RS flip-flop composed of U1B and U1C are both 1, and the outputs (pin 6 of U1B and pin 8 of U1C) are both 0. Since the input pins of and gates U5A and U5B (pins 1 and 2 of U5A, pins 4 and 5 of U5B) are both 0, the outputs (pin 3 of U5A, pin 6 of U5B) are both 0. The transmission control signals DE-1 and DE-2 of the RS485 transceiver are both 0, and the transceiver is in a reception prohibition transmission state. When the RS485 transceiver receives data, take U3 as an example. When RXD-1 changes to low level for negative jump, the repeatable monostable flip-flop U4A is triggered by the data received by the BUS BUS-1 of U3, and a high level pulse of 2.5s is output. Meanwhile, the capacitor C6 is rapidly discharged to a low level through the diode D2, the output (pin 6 of U1B) of the RS flip-flop consisting of U1B and U1C is 1, 1 is output through the AND gate U5A, DE-2 is 1, and U6 starts to send data. Due to the delay effect of the received signal filtering delay circuit 2B, the transmitting signal TXD-2 is changed into low level after 1us, and the integrity of the leading edge of the low level of the data is ensured. When the RXD-1 changes from positive jump to high level, the repeated monostable trigger is not triggered, high level pulse is continuously output until the last negative jump 2.5 of the RXD-1, the output is 0, and the long-time failure of the whole network caused by the failure of an RS485 branch bus is prevented. Meanwhile, the capacitor C6 is charged by R7 for 40us to be high-level, the output (pin 6 of U1B) of the RS trigger consisting of U1B and U1C is 0, 0 is output through the AND gate U5A, DE-2 is 0, and U6 stops sending data, so that the integrity of the back edge of the low-level data is ensured.
The utility model adopts the logic gate circuit to generate the low-delay control signal, thereby ensuring the safe transmission of the RS485 bus data.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the utility model. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. An RS485 relay circuit is characterized by comprising an RS485 bus transceiver circuit, a first received signal filtering delay circuit, a second received signal filtering delay circuit and a transmitted signal control circuit;
a first pin of the RS485 bus transceiver circuit is connected with a first pin of the first received signal filtering delay circuit, a second pin of the RS485 bus transceiver circuit is connected with a first pin of the transmitted signal control circuit, a third pin of the RS485 bus transceiver circuit is connected with a second pin of the transmitted signal control circuit, and a fourth pin of the RS485 bus transceiver circuit is connected with a first pin of the second received signal filtering delay circuit;
and a second pin of the first received signal filtering delay circuit is connected with a third pin of the sending signal control circuit, and a second pin of the second received signal filtering delay circuit is connected with a fourth pin of the sending signal control circuit.
2. The RS485 relay circuit of claim 1, wherein the RS485 bus transceiver circuit comprises an RS485 transceiver U3 and an RS485 transceiver U6, the RS485 transceiver U3 and the RS485 transceiver U6 are used for data reception and transmission of two buses.
3. The RS485 relay circuit according to claim 1, wherein the first receive signal filter delay circuit comprises a Schmitt input NOR gate U1D, a Schmitt input NOR gate U2D, a Schmitt input NOR gate U2E, a Schmitt input NOR gate U2F, a filter delay resistor R1 and a capacitor C1;
a first input end of the Schmidt input NOR gate U1D is connected with a second pin of the first received signal filtering delay circuit, and a second input end of the Schmidt input NOR gate U1D is grounded;
the output end of the schmitt input nor gate U1D is connected to one end of the filter delay resistor R1, and the other end of the filter delay resistor R1 is connected to one end of the capacitor C1 and the input end of the schmitt input nor gate U2F, respectively;
the other end of the capacitor C1 is grounded;
the output end of the Schmitt input NOT gate U2F is connected with the input end of the Schmitt input NOT gate U2E, and the output end of the Schmitt input NOT gate U2E is connected with the input end of the Schmitt input NOT gate U2D;
the output end of the Schmitt input NOT gate U2D is connected with the first pin of the first received signal filtering delay circuit.
4. The RS485 relay circuit of claim 3, wherein the Schmidt input NOR gate U1D is model SN74HC 7002N.
5. The RS485 relay circuit of claim 3, wherein the Schmidt input NOT gate U2D is model SN74HC14D, the Schmidt input NOT gate U2E is model SN74HC14D, and the Schmidt input NOT gate U2F is model SN74HC 14D.
6. The RS485 relay circuit according to claim 1, wherein the second receive signal filter delay circuit comprises a Schmitt input NOR gate U1A, a Schmitt input NOR gate U2A, a Schmitt input NOR gate U2B, a Schmitt input NOR gate U2C, a filter delay circuit R12 and a capacitor C8;
a first input end of the Schmidt input NOR gate U1A is connected with a second pin of the second received signal filtering delay circuit, and a second input end of the Schmidt input NOR gate U1A is grounded;
the output end of the schmitt input nor gate U1A is connected to one end of the filter delay resistor R12, and the other end of the filter delay resistor R12 is connected to one end of the capacitor C8 and the input end of the schmitt input nor gate U2A, respectively;
the other end of the capacitor C8 is grounded;
the output end of the Schmitt input NOT gate U2A is connected with the input end of the Schmitt input NOT gate U2B, and the output end of the Schmitt input NOT gate U2B is connected with the input end of the Schmitt input NOT gate U2C;
the output end of the Schmitt input NOT gate U2C is connected with the first pin of the second received signal filtering delay circuit.
7. The RS485 relay circuit of claim 6, wherein the Schmidt input NOR gate U1A is model SN74HC 7002N.
8. The RS485 relay circuit of claim 6, wherein the Schmidt input NOT gate U2A is model SN74HC14D, the Schmidt input NOT gate U2B is model SN74HC14D, and the Schmidt input NOT gate U2C is model SN74HC 14D.
9. The RS485 relay circuit according to claim 1, wherein the transmission signal control circuit comprises a monostable flip-flop U4A, a monostable flip-flop U4B, an AND gate U5A, an AND gate U5B, a Schmidt input NOR gate U1B, a Schmidt input NOR gate U1C, a delay circuit R6, a capacitor C4, a delay resistor R7, a capacitor C6, a delay resistor R2, a capacitor C3, a delay resistor R9 and a capacitor C7;
a first pin of the monostable flip-flop U4A is connected to a first input terminal of the schmitt input nor gate U1B, one end of the delay resistor R7, one end of the capacitor C6, and a fourth pin of the transmission signal control circuit, respectively;
a second pin of the monostable flip-flop U4A is respectively connected with a first input end of the AND gate U5A;
a third pin of the monostable flip-flop U4A is respectively connected with one end of the delay resistor R9 and one end of the capacitor C7;
the other end of the delay resistor R7 is connected with an external voltage, and the other end of the capacitor C6 is grounded;
the other end of the delay resistor R9 is connected with an external voltage, and the other end of the capacitor C7 is grounded;
a first pin of the monostable flip-flop U4B is respectively connected with a first input end of the Schmidt input NOR gate U1C, one end of the delay resistor R6, one end of the capacitor C4 and a third pin of the transmission signal control circuit;
a second pin of the monostable flip-flop U4B is respectively connected with a first input end of the AND gate U5B;
a third pin of the monostable flip-flop U4A is respectively connected with one end of the delay resistor R2 and one end of the capacitor C3;
the other end of the delay resistor R6 is connected with an external voltage, and the other end of the capacitor C4 is grounded;
the other end of the delay resistor R2 is connected with an external voltage, and the other end of the capacitor C3 is grounded;
a second input end of the schmitt input nor gate U1B is respectively connected with an output end of the schmitt input nor gate U1C and a second input end of the and gate U5B; the output end of the schmitt input nor gate U1B is respectively connected with the second input end of the schmitt input nor gate U1C and the second input end of the and gate U5A;
the output end of the AND gate U5A is connected with the second pin of the sending signal control circuit, and the output end of the AND gate U5B is connected with the first pin of the sending signal control circuit.
10. The RS485 relay circuit of claim 9, wherein the model number of the monostable flip-flop U4A is DM74LS123M, the model number of the monostable flip-flop U4B is DM74LS 123M;
the model of the AND gate U5A is SN74HC08D, and the model of the AND gate U5B is SN74HC 08D;
the Schmidt input NOR gate U1B is SN74HC7002N, and the Schmidt input NOR gate U1C is SN74HC 7002N.
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| CN117579440A (en) * | 2024-01-17 | 2024-02-20 | 杭州罗莱迪思科技股份有限公司 | RS485 relay circuit with arbitration mechanism |
| CN117579440B (en) * | 2024-01-17 | 2024-04-09 | 杭州罗莱迪思科技股份有限公司 | RS485 relay circuit with arbitration mechanism |
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