CN215834533U - Anti-latch-up IGBT device - Google Patents

Abstract

The utility model provides an anti-latch-up IGBT device, wherein at least one corresponding base region injection shielding structure is additionally arranged on the front surface of a substrate, and in the process of forming a base region in the substrate through an ion injection process, the base region injection shielding structure is additionally arranged to shield partial base region regions, so that the bottom of the base region shielded by each base region injection shielding structure is shallower than the bottoms of other base region regions, thereby changing the appearance of the bottom of the base region, and when the IGBT device is switched off, a cavity can preferentially pass through other base region regions with shallower bottoms, optimizing a channel for extracting the cavity, reducing the current passing through a PN junction, achieving the aim of improving the latch-up effect and improving the reliability of a product.

Description

Anti-latch-up IGBT device

Technical Field

The utility model relates to the technical field of semiconductor device manufacturing, in particular to an anti-latch-up IGBT device.

Background

An Insulated Gate Bipolar Transistor (IGBT) device combines voltage control of a Metal-Oxide-Semiconductor Field Effect Transistor (MOS) and a characteristic of a Bipolar Junction Transistor (BJT) conductance modulation current, has characteristics of high input impedance, small switching loss, fast speed, small voltage driving power, and the like, and is widely applied to various fields of power transmission and transformation, high-speed train traction, industrial driving, clean energy, and the like. IGBTs have limited use in certain areas because the parasitic PNPN structure is highly susceptible to latch-up failure.

The main disadvantage of the existing anti-latch-up concept is that the base resistance is considered to be reduced, but holes are still extracted through the original channel, hole current still passes through a PN junction, latch-up effect still occurs along with the increase of the current, and the capability of improving latch-up of the original structure is very limited.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide an anti-latch-up IGBT device which can improve anti-latch-up capability.

To achieve the above object, the present invention provides an anti-latch-up IGBT device including: the semiconductor device comprises a substrate of a first conduction type, a base region of a second conduction type formed in the front surface of the substrate, a grid electrode groove formed in the front surface of the substrate and located on two sides of the base region, and a grid electrode filled in the grid electrode groove. The latch-up resistant IGBT device further comprises at least one base injection shielding structure used for shielding part of the base region area in the process of forming the base region in the substrate through an ion injection process, the base injection shielding structure is formed above the front face of the substrate, doping impurities of the base region area on the periphery of each base injection shielding structure are diffused into the base region area shielded by the base injection shielding structure in the annealing activation process and are connected with each other to form the base region, and the bottom of the base region area shielded by each base injection shielding structure is shallower than the bottoms of other base region areas.

Optionally, each base region implantation blocking structure and the gate electrode are different parts of the same film layer.

Optionally, a gate oxide layer is disposed on the inner surface of the gate trench and between the base region injection shielding structure and the substrate surface.

Optionally, at least one of the base region implantation blocking structures is a bridge-like structure extending from a sidewall of the gate trench on one side of the base region to a sidewall of the gate trench on the other side of the base region along a direction perpendicular to the gate trench.

Optionally, at least one of the base injection shielding structures is a strip-shaped structure that is disposed at a side wall of the gate trench on one side of the base and extends along the gate trench, and the plurality of base injection shielding structures at the side wall of the gate trench on one side of the base are distributed in a sectional manner.

Optionally, the base injection shielding structures at the gate trenches on both sides of the base are arranged in a staggered manner.

Optionally, the latch-up resistant IGBT device further includes emitter regions formed in both sides of the top of the base region, the emitter regions on each side of the base region are distributed in a segmented manner, and each segment of the emitter region and the corresponding base region injection shielding structure in the strip structure are respectively disposed on both sides of the base region.

Optionally, the latch-up resistant IGBT device further includes a plurality of emitter contact plugs disposed above the front surface of the substrate, and each base injection shielding structure is disposed on one side of a corresponding emitter contact plug in a one-to-one correspondence manner.

Optionally, at least one of the base implantation masking structures has at least one slit, and the slit penetrates through the base implantation masking structure to expose the front surface of the substrate.

Optionally, the substrate includes a base of a first conductivity type and a drift region of the first conductivity type formed on a front surface of the base, a bottom of the gate trench is located in the drift region, and the base region is formed in the drift region; the anti-latch-up IGBT device further includes: the charge storage layer of the first conduction type is formed in the drift region at the bottom of the base region, the body contact region of the second conduction type is formed at the top of the base region, and the collector region of the second conduction type is formed on the back surface of the substrate.

Compared with the prior art, the technical scheme of the utility model has at least one of the following beneficial effects:

1. the method comprises the steps that at least one corresponding base region injection shielding structure is added on the front face of a substrate, therefore, in the process of forming a base region in the substrate through an ion injection process, part of a base region is shielded through the added base region injection shielding structure, in the process of annealing and activating doped impurities of the base region at the periphery of each base region injection shielding structure, the doped impurities can be diffused into the base region shielded by the base region injection shielding structure and are connected with each other to form the base region, and at the moment, the bottom of the base region shielded by each base region injection shielding structure is shallower than the bottoms of other base region regions. Therefore, the appearance of the bottom of the base region is changed, and when the IGBT device is turned off, the cavity preferentially passes through other base region regions with shallower bottoms, a channel for extracting the cavity is optimized, and the current passing through the PN junction is reduced, so that the aim of improving the latch-up effect is fulfilled, namely, the risk of opening the PN junction is reduced, the latch-up resistance of the IGBT device is improved, the UIS (unshipped Inductive Switching) capability of the product is improved, and the reliability of the product is improved.

2. The base region injection shielding structure and the grid can be constructed through the same film layer, and the base region injection shielding structure and the grid manufacture can be formed together by modifying the layout design of the grid mask plate, so that the method is compatible with the original process, only the grid layout design needs to be modified, and the manufacturing cost cannot be obviously increased.

Drawings

Fig. 1 is a schematic cross-sectional structure diagram of a conventional IGBT device.

Fig. 2 is a schematic perspective view of an IGBT device according to a first embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view taken along line AA in fig. 2.

Fig. 4 is a schematic sectional view taken along the line BB in fig. 2.

Fig. 5 is a schematic cross-sectional structure diagram of an IGBT device according to a second embodiment of the present invention.

Fig. 6 is a schematic cross-sectional structure diagram of an IGBT device according to a third embodiment of the present invention.

Wherein the reference numerals are as follows:

100. 200-a substrate; 101. 201-epitaxial layer (i.e., drift region); 102. 202-base region; 103. 203-a charge storage layer; 104. 204-a gate trench; 105. 205-gate oxide layer, 106, 206 a-gate; 107. 207-an emission area; 108. 208-a body contact region; 109. 209-emitter contact plug; 110. 210-a collector region; 206 b-base region implant masking structure.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the utility model. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "or" connected to "other elements or layers, it can be directly on, connected to, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …", "directly connected to" other elements or layers, there are no intervening elements or layers present. Although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. Spatial relationship terms such as "below … …", "below", "lower", "above … …", "above", "upper", and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" … …, or "beneath" would then be oriented "on" other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As shown in fig. 1, a conventional N-type IGBT device includes a substrate (N + -type) 100, an epitaxial layer (N-type epitaxial layer, or N-drift region) 101 provided on the substrate 100, a base region (P-type, also referred to as body region) 102 provided in an upper portion of the epitaxial layer 101, a charge storage layer (N + -type) 103 provided at a bottom of the base region 102, a body contact region (P + -type) 108 aligned with an emitter contact plug 109 provided at a top of the base region 102, an emitter region (N + -type, also referred to as source region) 107 provided in the base region 102 on both sides of the body contact region 108, gate trenches 104 provided on both sides of the base region 102, a gate oxide layer 105 formed on an inner surface of the gate trenches 104 and filled with a gate 106, a metal emitter provided on a front surface of the substrate 100 and electrically connected to the emitter region 107 and the body contact region 108 through the emitter contact plug 109, a collector region (P + -type) 110 provided on a back surface of the substrate 100, a metal collector (not shown) may be formed on the bottom surface of the collector region 110 in ohmic contact therewith.

In the above IGBT device, the N + emitter region 107, the P-type base region 102, the N-epitaxial layer 101, and the P + collector region 110 form a parasitic regionWhen the collector current is large, the collector current generates voltage drop through the resistance of the base region 102, so that when a PN junction formed by the P-type base region 102 and the N + emitter region 107 is conducted in the forward direction, the current does not directly flow from the P-type base region 102 to the metal emitter through a channel, the gate 106 loses control over the IGBT device, the current rises sharply, and the voltage is reduced. At this time, the sum of the current amplification coefficients of the PNP tube and the NPN tube is alpha_PNP+α_NPNThis phenomenon is latch-up 1.

To improve latch-up of IGBT devices, it is generally considered to reduce α_PNPAnd alpha_NPNCurrently, a more common method is to increase the concentration of the P-type base region 102 under the N + emitter region 107, i.e., to increase the P + body contact region 108, so as to reduce the overall resistance of the P-type base region 102, thereby achieving the purpose of improving the latch-up. Specifically, after a contact hole for forming the emitter contact plug 109 is formed by etching and before metal is filled to form the emitter contact plug 109, a P + impurity is implanted into the P-type base region 102 along the contact hole and junction push is performed, thereby forming a relatively large P + body contact region 108 below the N + emitter region 107.

However, although the latch-up effect is improved by reducing the resistance of the P-type base region 102 in the above method, the device still performs hole extraction through the original channel, the hole current still passes through the PN junction, and the latch-up effect still occurs with the increase of the hole current.

Based on the above, the utility model mainly provides an anti-latch IGBT device, wherein the bottom appearance of a base region formed after the base region is changed by arranging a base region injection shielding structure, the extraction path of a cavity is optimized, the risk of opening a PN junction is reduced, the anti-latch capability of the IGBT is improved, the UIS capability of a product is improved, and the reliability of the product is improved.

The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

Fig. 2 to 4 actually show respective schematic diagrams of the device structure of one cell region of the latch-up resistant IGBT device of the present embodiment. Referring to fig. 2 to 4, the present embodiment provides an anti-latch-up IGBT device, which includes: the semiconductor device includes a substrate 2 of a first conductivity type, a base region 202 of a second conductivity type formed in a front surface of the substrate, a gate trench 205 formed in the front surface of the substrate and located at both sides of the base region 202, a gate 206a filled in the gate trench 204, a plurality of base implant masking structures 206b, and a collector region 210 of the second conductivity type formed on a rear surface of the substrate.

Taking the first conductive type as N type and the second conductive type as P as an example, in this embodiment, the substrate is composed of an N + base 200 and an N-drift region 201 formed on the N + base 200, and the N-drift region 201 may be an N-epitaxial layer formed on the N + base 200 through an epitaxial growth process, or may be an ion implantation layer formed through an ion implantation process or the like. The material of the N + base 200 may be any suitable substrate material, such as silicon, germanium, silicon-on-insulator, silicon germanium, or gallium arsenide, among others. The P-type base region 202 is formed on the upper portion of the N-drift region 201, an N + charge storage layer 203 is further formed on the N-drift region 201 at the bottom of the P-type base region 202, a P + body contact region 208 is formed on the top of the P-type base region 202, and N + emitter regions 207 are formed in the P-type base region 202 on two sides of the P + body contact region 208. The P + collector region 210 is formed on the back surface of the N + substrate 200, and may be formed through an ion implantation process or an epitaxial growth process, etc.

In this embodiment, the P-type base region 202 between the two gate trenches 204 is continuously extended, the two gate trenches 204 and the region formed by the P-type base region 202 therebetween are a cell region, the bottom boundary (also referred to as a lower boundary) of the P-type base region 202 is higher than the bottom boundary of the gate trench 204, and further, the bottom boundary of the gate trench 204 is lower than the bottom boundary of the N + charge storage layer 203 and higher than the bottom boundary of the N-drift region 201.

It should be understood that when the latch-up resistant IGBT device of the present embodiment has a plurality of cell regions, the cell regions may be arranged in parallel and formed on the same N-drift region 201, that is, when a plurality of gate trenches 204 are formed in the N-drift region 201, a P-type base region 202 is formed between no two adjacent gate trenches 204.

The inner surface of each gate trench 204 is covered with a gate oxide layer 205 and filled with a gate 206a, and the material of the gate 206a is, for example, doped polysilicon. Each base implant masking structure 206b is formed over the front surface of the base region 202.

In this embodiment, two gate trenches 204 extend along the Y direction, and the base implantation blocking structures 206b on the region between two adjacent gate trenches 204 are disposed in parallel and at equal intervals and extend along the X direction (i.e., the direction perpendicular to the gate trenches), and extend from the gate trench 204 on one side of the P-type base region 202 adjacent to the sidewall of the P-type base region 202 along the X direction to the gate trench 204 on the other side of the P-type base region 202 adjacent to the sidewall of the P-type base region 202, so as to form a bridge structure straddling over the P-type base region 202.

As an example, each base implant masking structure 206b is a different part of the same film as the gate 206a, that is, each base implant masking structure 206b may be formed in the same film as the gate 206 a. Specifically, after a gate oxide layer 205 is formed on the inner surface of the gate trench 204 and the front surface of the substrate, a gate material is deposited by a deposition process, and the gate material is subjected to photolithography and etching by using a mask having patterns of the gate and the base implantation mask 206b, so that each base implantation mask 206b and the gate 206a are formed simultaneously. At this time, the gate oxide layer 205 is also remained between each base implantation mask structure 206b and the P-type base region 202. The ion implantation for forming the P-type base region 202 is performed after the formation of each base implantation blocking structure 206b and the gate 206a, so that the bottom profile of the formed P-type base region 202 is optimized by each base implantation blocking structure 206b, specifically, the bottom of the region of the P-type base region 202 blocked by each base implantation blocking structure 206b is shallower than the bottom of the region of the other base region 202, thereby forming the bottom profile of the P-type base region 202 of a wavy line type shown in fig. 4, and the bottom profile of the wavy line type is extended in the Y direction.

In addition, the latch-up resistant IGBT device of the present embodiment further includes an insulating dielectric layer (not shown), a plurality of emitter contact plugs 209, a metal emitter (not shown), and a metal collector. The insulating medium layer covers the front surface of the substrate to protect each base region injection shielding structure 206b, the gate 206a in the gate trench 204, the N + emitter region 207, the P-type base region 202 and the like, a plurality of contact holes are formed in the insulating medium layer at intervals, each contact hole exposes a part of the P-type base region 202 and a part of the N + emitter regions 207 on two sides, an emitter contact plug 209 is filled in each contact hole, and each emitter contact plug 209 is in ohmic contact with the P-type base region 202 and the two N + emitter regions 207 at the bottom of the contact hole. A metal emitter is formed over the insulating dielectric layer and each emitter contact plug 209 and is electrically connected to all emitter contact plugs 209 between two gate trenches 204. A metal collector is formed on the bottom surface of the P + collector region 210 and in ohmic contact with the P + collector region 210.

In this embodiment, the base injection shielding structures 206b and the emitter contact plugs 209 are the same in number and are arranged in a one-to-one correspondence manner, that is, each base injection shielding structure 206b is arranged on one side of a corresponding emitter contact plug 209 in a one-to-one correspondence manner, so that the bottom topography of the P-type base region 202 is relatively uniformly improved.

The manufacturing process of the IGBT device according to this embodiment may be completely compatible with the manufacturing process of the existing IGBT device, and each step and process are completely the same, the difference is only that the original gate layout is modified, and a pattern corresponding to each base region implantation blocking structure 206b is added therein, specifically, after gate polysilicon is deposited to fill up the gate trench 204, photolithography and etching may be performed on the deposited gate polysilicon and the formed gate oxide layer 205 by using a mask plate having the gate pattern and the base region implantation blocking structure pattern, so as to form each base region implantation blocking structure 206b and gate 206a simultaneously, and then, P-type ion (or referred to as P-type doping impurity) implantation is performed on the N-drift region 201 to form the P-type base region 202 by using each base region implantation blocking structure 206b and gate 206a as masks, in this P-type ion implantation process, each base injection blocking structure 206b can block part of the base region to prevent P-type ions from being injected into the base injection blocking structure 206b, and other P-type ions are injected into the N-drift region 201 which is not blocked by the base injection blocking structure 206b and the gate 206a, after annealing push (the injected ions can diffuse in the annealing process) is further performed, the P-type ions in the N-drift region 201 at the periphery of each base injection blocking structure 206b diffuse into the N-drift region 201 below each base injection blocking structure 206b, and the P-type ion regions diffused below each base injection blocking structure 206b are connected with each other, so that the P-type base region 202 connected into a whole is formed between two adjacent gate trenches 204. Moreover, since the doping impurities in the base region 202 shielded by each base region injection shielding structure 206b are formed by diffusion, and the doping impurities in the base region 202 at the periphery of each base region injection shielding structure 206b are mainly formed by ion implantation, the bottom of the base region 202 region shielded by each base region injection shielding structure 206b is shallower than the bottom of the other base region 202 regions, thereby forming the bottom profile of the P-type base region 202 of the wavy line type shown in fig. 4.

The other steps and procedures in the manufacturing process of the IGBT device of the present embodiment are conventional technologies, and can be implemented by any suitable existing method, which is not described in detail herein.

Compared with the IGBT device structure shown in fig. 1, in the structure of the IGBT device of this embodiment, the ion implantation result for forming the P-type base region 202 is changed by adding each base implantation shielding structure 206b above the substrate between the gate trenches 204, and further, after the P-type base ion implantation annealing, the bottom profile of the formed P-type base region 202 can be changed, so that the bottom profile of the wavy-line-type P-type base region 202 shown in fig. 4 is formed, the bottom of the P-type base region 202 around each base implantation shielding structure 206b is relatively more concave towards the N + charge storage layer 203, and a channel for hole extraction is optimized, so that when the IGBT device is turned off, holes are preferentially extracted from the shallowest region of the P-type base region 202 around each base implantation shielding structure 206b through each base implantation shielding structure (i.e. the flowing direction of dotted-line holes is upwards extracted from the upper convex point (also can be called a peak) of the wavy line at both sides of the emitter contact plugs as shown in fig. 4, the current of a PN junction formed by the P-type base region and the N + emitter region is greatly reduced, so that the aims of effectively improving the latch-up effect and increasing the latch-up resistance are fulfilled.

Alternatively, the emitter contact plugs 209 on both sides of each base injection shielding structure 206b are distributed in an axial symmetry manner with respect to the base injection shielding structure 206b, so that a hole extraction channel (i.e., a hole extraction path) formed under each base injection shielding structure 206b toward the emitter contact plugs on both sides thereof is in a Y shape and is axially symmetric with respect to the base injection shielding structure 206 b.

In addition, the more uniformly the base implant masking structures 206b are distributed, the more uniformly the change in the bottom profile of the P-type base region 202 is, and the higher the device reliability is.

Example two

Referring to fig. 5, the present embodiment provides an anti-latch-up IGBT device, which has a structure that is different from that of the first embodiment in that at least one base implantation masking structure 206b has at least one slit 206c, and the slit 206c penetrates through the base implantation masking structure 206b where it is located and the gate oxide layer 205 below it to expose the front surface of the substrate. Other structures of the anti-latch-up IGBT device provided in this embodiment are substantially the same as the corresponding structures of the first embodiment, and are not described in detail here.

In this case, due to the existence of the slit 206c, the bottom shape of the P-type base region 202 in the latch-up resistant IGBT device according to this embodiment is not only in a wavy line shape in the Y direction, but also in a wavy line shape in the X direction, so that the hole extraction path is further optimized, and the latch-up resistance of the IGBT device is improved.

In addition, the more uniform the distribution of the base implantation shielding structure 206b and its slits 206c, the more uniform the change of the bottom profile of the P-type base region 202, and the higher the device reliability.

EXAMPLE III

Fig. 6 is a schematic cross-sectional structure diagram of an IGBT device according to a third embodiment of the present invention. In fig. 6, in order to more clearly show the cross-sectional structure of the corresponding doped region in the substrate along the Y direction, only the cross-sectional structure of the corresponding doped region along the Y direction is shown on the right sidewall of the device in fig. 6, and the cross-sectional structure of the gate and the gate dielectric layer along the Y direction is omitted.

Referring to fig. 6, the present embodiment provides an anti-latch-up IGBT device, which has a structure that differs from the first embodiment mainly in that each base injection shielding structure 206b does not extend along the X direction any more, but is disposed at the sidewall of the gate trench 204 on one side of the corresponding P-type base region 202 and extends along the gate trench 204, that is, each base injection shielding structure 206b extends along the Y direction and has a strip-shaped structure, and the plurality of base injection shielding structures 206 at the sidewall of the gate trench 204 of the P-type base region 202 are discontinuous and are distributed in a segmented manner.

In this embodiment, the base implantation shielding structures 206b on the sidewalls of the gate trenches 204 on both sides of the P-type base region 202 are arranged in a staggered manner.

In the latch-up resistant IGBT device of this embodiment, the N + emitter regions 207 on each side are distributed in a segmented manner, and each segment of N + emitter region 207 and a corresponding segment of base injection shielding structure 206b are respectively disposed on two sides of the P-type base region 202.

Other structures of the anti-latch-up IGBT device provided in this embodiment are substantially the same as the corresponding structures of the first embodiment, and are not described in detail here.

In this embodiment, the junction depth of the P-type base region 202 under the bottom of each base injection shielding structure 206b after junction pushing is a bit shallower than the junction depth of the P-type base region 202 at the periphery of each base injection shielding structure 206b, so that a hole preferentially goes under the bottom of each base injection shielding structure 206b when the IGBT device is turned off, and the N + emitter region 207 is turned off under the bottom of each base injection shielding structure 206b, thereby effectively reducing the current passing through the PN junction formed by the N + emitter region 207 and the P-type base region 202, that is, the scheme of this embodiment can also optimize the hole extraction path, greatly reduce the current passing through the PN junction formed by the P-type base region and the N + emitter region, and achieve the purposes of effectively improving the latch-up effect and improving the latch-up resistance of the IGBT device.

It should be further noted that the technical features disclosed in the foregoing embodiments may also be combined with each other to obtain other embodiments of the present invention, for example, on the basis of embodiment three, the structure of the IGBT device according to another embodiment of the present invention is to add at least one slit 206c as described in embodiment two in at least one section of the base implantation shielding structure 206b to further optimize the bottom profile of the P-type base 202. For another example, in the structure of the IGBT device according to still another embodiment of the present invention, the two base implantation blocking structures 206b described in the first embodiment and the third embodiment are combined, so that a mixed base implantation blocking structure 206b is formed, so as to optimize the bottom topography of the P-type base region 202.

It should be understood that the bottom topography of the P-type base region 202 varies depending on the topography of the base implant mask structure 206b, and therefore the topography of the base implant mask structure 206b of the present invention is not limited to the bridge-like structure or the stripe-like structure with rectangular cross-sections along the XY plane and the Z-direction plane, which are listed in the above embodiments, but may be any other suitable topography, for example, the shape of the cross-section of the base implant mask structure 206b along the XY plane or the Z-direction plane is a source line, an ellipse, a pentagon, a hexagon, an octagon, a polygon with a wavy frame, and so on.

In addition, it should be noted that the critical dimensions of each base implantation masking structure 206b and the emitter contact plugs 209 at both sides thereof, the critical dimensions of each base implantation masking structure 206b and the gates at both ends thereof, the line width of the base implantation masking structure 206b, the line width of the emitter contact plug 209, and the like, are not particularly limited in the present invention, and may be reasonably selected according to the device design requirements and the critical dimensions allowed by the process, for example, the distance between the base implantation masking structure 206b and the gates at both ends thereof in fig. 2 is the thickness of the gate oxide layer 205 on the sidewall of the gate trench 204, while the distance between the base implantation masking structure 206b and the gates at both ends thereof in fig. 6 is close to 0, in other embodiments, the distance between the base implantation masking structure 206b and the gates at both ends thereof may also be allowed to be greater than the thickness of the gate oxide layer 205 on the sidewall of the gate trench 204, and so on.

In addition, in each of the above embodiments, the base injection blocking structure 206b is a different part of the same film layer as the gate 206a, and only the gate layout design needs to be modified, so that the mask plate for forming the gate by etching has not only the gate pattern but also the base injection blocking structure 206b pattern, and the process is not increased or decreased compared with the prior art, but the technical scheme of the present invention is not limited thereto.

In summary, in the latch-up resistant IGBT device of the present invention, the shape of the bottom of the base region is changed by adding at least one corresponding base region injection shielding structure on the front surface of the substrate, and when the IGBT device is turned off, the cavity preferentially passes through other base region regions with a shallower bottom, so that a channel for extracting the cavity is optimized, and a current passing through the PN junction is reduced, thereby achieving an object of improving the latch-up effect, that is, reducing a risk of turning on the PN junction, improving the latch-up resistance of the IGBT device, improving UIS (Switching process under an Unclamped Inductive load) capability of the product, and improving reliability of the product. Further, the base injection shielding structure and the grid electrode can be constructed through the same film layer, so that the method is compatible with the original process, only the layout design needs to be modified, and the manufacturing cost is not obviously increased.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.

Claims (10)

1. An anti-latch-up IGBT device, comprising: the substrate comprises a substrate of a first conductive type, a base region of a second conductive type formed in the front face of the substrate, gate trenches formed in the front face of the substrate and located on two sides of the base region, and a gate filled in the gate trenches, and is characterized by further comprising at least one base injection shielding structure used for shielding part of a base region in the process of forming the base region in the substrate through an ion implantation process, wherein the base injection shielding structure is formed above the front face of the substrate, doped impurities of the base region at the periphery of each base injection shielding structure are diffused into the base region shielded by the base injection shielding structure in the annealing activation process and are connected with each other to form the base region, and the bottom of the base region shielded by each base injection shielding structure is shallower relative to the bottoms of other base regions.

2. The latch-up resistant IGBT device of claim 1, wherein each of the base implant masking structures and the gate are different portions of a same film layer.

3. The latch-up resistant IGBT device of claim 2, wherein a gate oxide layer is disposed on an inner surface of the gate trench and between the base implant masking structure and the substrate surface.

4. The latch-up resistant IGBT device of claim 1, wherein at least one of the base implant masking structures is a bridge-like structure extending from a sidewall of a gate trench on one side of the base to a sidewall of the gate trench on the other side of the base in a direction perpendicular to the gate trench.

5. The latch-up resistant IGBT device of claim 1, wherein at least one of the base implant masking structures is a stripe structure disposed at and extending along a sidewall of the gate trench on the base side, and a plurality of the base implant masking structures at the sidewall of the gate trench on the base side are distributed in a segmented manner.

6. The latch-up resistant IGBT device of claim 5, wherein the base implant masking structures at the gate trenches on both sides of the base are staggered.

7. The latch-up resistant IGBT device of claim 6, further comprising emitter regions formed in both sides of the top of the base region, and the emitter regions on each side of the base region are distributed in a segmented manner, and each segment of the emitter region and the corresponding base implant shielding structure in the stripe structure are separated on both sides of the base region.

8. The latch-up resistant IGBT device of claim 1, further comprising a plurality of emitter contact plugs disposed over the front surface of the substrate, each of the base implant masking structures being disposed on a side of a respective one of the emitter contact plugs in a one-to-one correspondence.

9. The latch-up resistant IGBT device of any one of claims 2-8, wherein at least one of the base implant shields has at least one slit therein, the slit extending through the base implant shield to expose the front side of the substrate.

10. The latch-up resistant IGBT device of claim 1, wherein the substrate includes a base of a first conductivity type and a drift region of the first conductivity type formed on a front surface of the base, a bottom of the gate trench being located in the drift region, the base region being formed in the drift region; the anti-latch-up IGBT device further includes: the charge storage layer of the first conduction type is formed in the drift region at the bottom of the base region, the body contact region of the second conduction type is formed at the top of the base region, and the collector region of the second conduction type is formed on the back surface of the substrate.

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