CN215730446U

CN215730446U - Timer circuit applied to digital electronic technology practical training teaching

Info

Publication number: CN215730446U
Application number: CN202122094337.1U
Authority: CN
Inventors: 卢善勇; 何世品; 陶烈健; 卢丽娇
Original assignee: Guangxi Xiying Information Technology Co ltd
Current assignee: Guangxi Xiying Information Technology Co ltd
Priority date: 2021-09-01
Filing date: 2021-09-01
Publication date: 2022-02-01
Anticipated expiration: 2031-09-01

Abstract

The utility model provides a timer circuit applied to digital electronic technology practical training teaching. The timer circuit mainly comprises a 7-bit binary counter, a 555 chip, an 8-channel input NAND gate and a dial switch, wherein the 555 chip forms a square wave oscillator and generates a second period clock, the 7-bit binary counter counts the second period clock, and the dial switch and the NAND gate finish timing setting. Be applied to the real teaching of instructing of digital electronic technology course with this utility model, can mobilize the interest that the student participated in real teaching of instructing, improve the teaching effect of binary counter content.

Description

Timer circuit applied to digital electronic technology practical training teaching

Technical Field

The utility model relates to a timer circuit, which is applied to digital electronic technology training teaching and belongs to the technical field of digital electronics.

Background

The binary counter is a common sequential logic chip in digital electronic technology, and is also one of the teaching key contents of the digital electronic technology course. However, in the traditional practical teaching of the binary counter, logic verification is mostly carried out on a chip of the binary counter, the teaching is abstract and boring, the interest of students cannot be attracted, and the practical teaching effect is not good. In life and production, a timer is needed in many occasions, students are familiar with the function of the timer, and the working principle and the circuit of the timer are curious. Therefore, a 7-bit binary counter chip is adopted, a timer circuit is designed, and the timer circuit is applied to practical training teaching of digital electronic technology courses so as to arouse interest of students in participating in the practical training teaching and improve teaching effect of the content of the binary counter.

SUMMERY OF THE UTILITY MODEL

The utility model provides a timer circuit applied to digital electronic technology training teaching, which is applied to digital electronic technology course training teaching. The timer circuit mainly comprises a 7-bit binary counter, a 555 chip, an 8-channel input NAND gate and a dial switch. The 555 chip forms a square wave oscillator, generates a second reference clock, the 7-bit binary counter counts the second reference clock, and the dial switch and the NAND gate finish timing setting.

The utility model adopts the following specific technical scheme:

a timer circuit applied to digital electronic technology training teaching comprises a 555 chip U1, a counter U2, a NAND gate U3, a dial switch SW1, keys K1 and K2, interfaces J1 and J2, light emitting diodes LED 1-LED 10, capacitors C1 and C2 and resistors R1-R13, an adjustable resistor RV1, test ends TP 1-TP 3, TQ 1-TQ 3 and exclusion RN1, the 8 pin of the 555 chip U1 is connected with +5V, the 1 pin is grounded, the 2 pin and the 6 pin are connected with a test end TP2, the anode of a capacitor C1, and one fixed end and a movable end of an adjustable resistor RV1, the 3 pin is connected with one end of a resistor R10, the other fixed end of the adjustable resistor RV1, one end of a test end TP1 and an end of an interface J1, the 4 pin is connected with one end of the interface J2 and one end of a resistor R11, the other end of the resistor R11 is connected with +5V, the other end of the resistor R10 is connected with the anode of the LED8, and the cathode of the LED8 and the cathode of the capacitor C1 are grounded; a pin 1 of the counter U2 is connected to the other end of the interface J1, one end of the capacitor C2, one end of the key K1 and one end of the resistor R8, a pin 2 is connected to one end of the key K2 and one end of the resistor R9, the other ends of the key K2 and the resistor R8 are connected to +5V, and the other ends of the key K1, the capacitor C2 and the resistor R9 are connected to the ground; a 3 pin of a counter U2 is connected with an 8 pin of a dial switch SW1 and one end of a resistor R7, a 4 pin is connected with a 9 pin of the dial switch SW1 and one end of a resistor R6, a 5 pin is connected with a 10 pin of the dial switch SW1 and one end of a resistor R5, a 6 pin is connected with an 11 pin of the dial switch SW1 and one end of the resistor R4, a 9 pin is connected with a 12 pin of a dial switch SW1, one end of the resistor R3 and a test end TQ3, a 13 pin of the dial switch SW1, one end of a resistor R2 and a test end TQ2, a 14 pin of a 12 pin is connected with the dial switch SW1, one end of a resistor R1 and a test end TQ1, and the other ends of the resistors R1-R7 are respectively connected with anodes of light-emitting diodes LED 1-7, and cathodes of the light emitting diodes LED 1-7 are grounded; a 1 pin of a 1 pin dial switch SW1 and a 9 pin of an exclusion RN1 of the NAND gate U3, a 2 pin of a 2 pin dial switch SW1 and an 8 pin of an exclusion RN1, a 3 pin of a 3 pin dial switch SW1 and a 7 pin of an exclusion RN1, a 4 pin of a 4 pin dial switch SW1 and a 6 pin of an exclusion RN1, a 5 pin of a 5 pin dial switch SW1 and a 5 pin of an exclusion RN1, a 6 pin of a 6 pin dial switch SW1 and a 4 pin of an exclusion RN1, a 7 pin of a 11 pin dial switch SW1 and a 3 pin of an exclusion RN1, a 12 pin +5V, one end of an 8 pin resistor R12, one end of a resistor R13, a test end 3, the other end of an interface J2, the other end of a resistor R12 is connected with the negative electrode of an LED9, the positive electrode of an LED9 and the positive electrode of an exclusion RN 72 TP 9, the LED9 of an LED9 and the other end of the LED9 is connected with the ground; the counter U2 adopts a CD4024 chip, and the NAND gate U3 adopts a TTL7430 chip.

The utility model adopts a 7-bit binary counter chip and designs a timer circuit, which is applied to the practical training teaching of digital electronic technology courses, mobilizes the interest of students in participating in the practical training teaching and improves the teaching effect of the content of the binary counter.

Drawings

Fig. 1 is a circuit diagram of the present invention.

Detailed Description

The utility model is further described below with reference to the accompanying drawings.

As shown in FIG. 1, a timer circuit applied to digital electronic technology training teaching comprises a 555 chip U1, a counter U2, a NAND gate U3, a dial switch SW1, keys K1 and K2, interfaces J1 and J2, light emitting diodes LED 1-LED 10, capacitors C1 and C2, and resistors R1-R13, an adjustable resistor RV1, test ends TP 1-TP 3, TQ 1-TQ 3 and exclusion RN1, the 8 pin of the 555 chip U1 is connected with +5V, the 1 pin is grounded, the 2 pin and the 6 pin are connected with a test end TP2, the anode of a capacitor C1, and one fixed end and a movable end of an adjustable resistor RV1, the 3 pin is connected with one end of a resistor R10, the other fixed end of the adjustable resistor RV1, one end of a test end TP1 and an end of an interface J1, the 4 pin is connected with one end of the interface J2 and one end of a resistor R11, the other end of the resistor R11 is connected with +5V, the other end of the resistor R10 is connected with the anode of the LED8, and the cathode of the LED8 and the cathode of the capacitor C1 are grounded; a pin 1 of the counter U2 is connected to the other end of the interface J1, one end of the capacitor C2, one end of the key K1 and one end of the resistor R8, a pin 2 is connected to one end of the key K2 and one end of the resistor R9, the other ends of the key K2 and the resistor R8 are connected to +5V, and the other ends of the key K1, the capacitor C2 and the resistor R9 are connected to the ground; a 3 pin of a counter U2 is connected with an 8 pin of a dial switch SW1 and one end of a resistor R7, a 4 pin is connected with a 9 pin of the dial switch SW1 and one end of a resistor R6, a 5 pin is connected with a 10 pin of the dial switch SW1 and one end of a resistor R5, a 6 pin is connected with an 11 pin of the dial switch SW1 and one end of the resistor R4, a 9 pin is connected with a 12 pin of a dial switch SW1, one end of the resistor R3 and a test end TQ3, a 13 pin of the dial switch SW1, one end of a resistor R2 and a test end TQ2, a 14 pin of a 12 pin is connected with the dial switch SW1, one end of a resistor R1 and a test end TQ1, and the other ends of the resistors R1-R7 are respectively connected with anodes of light-emitting diodes LED 1-7, and cathodes of the light emitting diodes LED 1-7 are grounded; a 1 pin of a 1 pin dial switch SW1 and a 9 pin of an exclusion RN1 of the NAND gate U3, a 2 pin of a 2 pin dial switch SW1 and an 8 pin of an exclusion RN1, a 3 pin of a 3 pin dial switch SW1 and a 7 pin of an exclusion RN1, a 4 pin of a 4 pin dial switch SW1 and a 6 pin of an exclusion RN1, a 5 pin of a 5 pin dial switch SW1 and a 5 pin of an exclusion RN1, a 6 pin of a 6 pin dial switch SW1 and a 4 pin of an exclusion RN1, a 7 pin of a 11 pin dial switch SW1 and a 3 pin of an exclusion RN1, a 12 pin +5V, one end of an 8 pin resistor R12, one end of a resistor R13, a test end 3, the other end of an interface J2, the other end of a resistor R12 is connected with the negative electrode of an LED9, the positive electrode of an LED9 and the positive electrode of an exclusion RN 72 TP 9, the LED9 of an LED9 and the other end of the LED9 is connected with the ground; the counter U2 adopts a CD4024 chip, and the NAND gate U3 adopts a TTL7430 chip.

The 555 chip U1 and the peripheral resistance-capacitance element form a square wave oscillator, and the adjustable resistor RV1 is adjusted to adjust the oscillation frequency. The counter U2 adopts a CD4024 chip, which is a 7-bit binary asynchronous counter for counting square waves generated by a 555 chip U1. The nand gate U3 is an 8-input nand gate chip, and the toggle switch DSW1 is a 7-way toggle switch, which can connect 7 outputs of the counter U2 to 7 inputs of the nand gate U3, and the other input of the nand gate U3 to + 5V. The interfaces J1 and J2 are provided with short-circuit caps, when the interface J2 is switched on by the short-circuit caps, the reset end (4 pins) of the 555 chip U1 is controlled by the output end (8 pins) of the NAND gate U3, when the NAND gate U3 outputs a high level, the 555 chip U1 starts oscillation, and when the NAND gate U3 outputs a low level, the 555 chip U1 stops oscillation.

Training the content of a square wave oscillator: the short-circuit caps of the interfaces J1 and J2 are pulled out and electrified, so that the flickering of the light-emitting diode LED8 can be observed, the square-wave oscillator starts to vibrate, the resistor RV1 can be adjusted, the flickering speed of the light-emitting diode LED8 can be observed to change, the resistor RV1 can be adjusted, and the oscillation frequency of the square-wave oscillator can be changed; observing a test end TP1 by using an oscilloscope, observing square wave voltage, and adjusting a resistor RV1 to enable the frequency of the square wave to be 1 Hz; and observing the test end TP2 by using an oscilloscope, and observing the voltage waveform of the charging and discharging of the capacitor.

Binary counter logic verification: the shorting cap of interface J2 was pulled out and the shorting cap of interface J1 was inserted. When the power is on, the reset key K2 is pressed, the LEDs 1-7 can be observed to be completely turned off, and the counter U2 is in a reset state; when the reset key K2 is released, the oscilloscope observes the voltage waveforms of TP1, TQ1, TQ2 and TQ3, four paths of square wave output can be observed, the periods are respectively 1 second, 2 seconds, 4 seconds and 8 seconds, and the results show that TQ1, TQ2 and TQ3 are respectively the output of the halving frequency, quartering frequency and octaving frequency of the counting clock.

Training the timer content: firstly, setting a dial switch DSW1 according to timing time, if the timing time is 6 seconds, the binary number of 7 bits corresponding to decimal 6 is 0000110, switching on the corresponding dial bits output by Q3 and Q2 of a counter U2, and switching off other dial bits, namely completing the setting of the dial switch DSW 1; the short-circuit caps of the interfaces J1 and J2 are inserted, power is on, a reset key K1 is pressed once, the light-emitting diode LED10 can be observed to be bright, timing is indicated to start, and the voltage of a measurement terminal TP3 is at a high level; after 6 seconds, the light emitting diode LED10 is turned off, the light emitting diode LED9 is turned on, timing is finished, the voltage of the TP3 at the measuring and testing end is low level, meanwhile, the light emitting diode LED8 can be observed to stop flickering, the square wave oscillator is stopped vibrating, the light emitting diodes LED 1-LED 7 are observed, only the LED2 and the LED3 are turned on, and the fact that the Q7Q6Q5Q4Q3Q2Q1 of the counter U2 is stopped in a state of '0000110' is shown.

Claims

1. A timer circuit applied to digital electronic technology practical training teaching is characterized in that: the circuit comprises a 555 chip U1, a counter U2, an NAND gate U3, a dial switch SW1, keys K1 and K2, interfaces J1 and J2, Light Emitting Diodes (LEDs) 1-LED 10, capacitors C1 and C2, resistors R1-R13, an adjustable resistor RV1, test ends TP 1-TP 3 and TQ 1-TQ 3 and exclusion RN1, wherein the 8 pin of the 555 chip U1 is connected with +5V, the 1 pin is grounded, the 2 pin and the 6 pin are connected with a test end TP2, the positive electrode of the capacitor C1, a fixed end and a moving end of the adjustable resistor RV1, the 3 pin is connected with one end of a resistor R10, the other fixed end of the adjustable resistor RV1, the test end TP1 and one end of an interface J7, the 4 pin is connected with one end of the interface J2 and one end of a resistor R11, the other positive electrode of the resistor R365 + V of the resistor R11 is connected with the negative electrode of the LED 36 12, and the negative electrode of the LED 11 is connected with the LED 11 and the LED 11 of the LED 36 1 2; a pin 1 of the counter U2 is connected to the other end of the interface J1, one end of the capacitor C2, one end of the key K1 and one end of the resistor R8, a pin 2 is connected to one end of the key K2 and one end of the resistor R9, the other ends of the key K2 and the resistor R8 are connected to +5V, and the other ends of the key K1, the capacitor C2 and the resistor R9 are connected to the ground; a 3 pin of a counter U2 is connected with an 8 pin of a dial switch SW1 and one end of a resistor R7, a 4 pin is connected with a 9 pin of the dial switch SW1 and one end of a resistor R6, a 5 pin is connected with a 10 pin of the dial switch SW1 and one end of a resistor R5, a 6 pin is connected with an 11 pin of the dial switch SW1 and one end of the resistor R4, a 9 pin is connected with a 12 pin of a dial switch SW1, one end of the resistor R3 and a test end TQ3, a 13 pin of the dial switch SW1, one end of a resistor R2 and a test end TQ2, a 14 pin of a 12 pin is connected with the dial switch SW1, one end of a resistor R1 and a test end TQ1, and the other ends of the resistors R1-R7 are respectively connected with anodes of light-emitting diodes LED 1-7, and cathodes of the light emitting diodes LED 1-7 are grounded; a 1 pin of a 1 pin dial switch SW1 and a 9 pin of an exclusion RN1 of the NAND gate U3, a 2 pin of a 2 pin dial switch SW1 and an 8 pin of an exclusion RN1, a 3 pin of a 3 pin dial switch SW1 and a 7 pin of an exclusion RN1, a 4 pin of a 4 pin dial switch SW1 and a 6 pin of an exclusion RN1, a 5 pin of a 5 pin dial switch SW1 and a 5 pin of an exclusion RN1, a 6 pin of a 6 pin dial switch SW1 and a 4 pin of an exclusion RN1, a 7 pin of a 11 pin dial switch SW1 and a 3 pin of an exclusion RN1, a 12 pin +5V, one end of an 8 pin resistor R12, one end of a resistor R13, a test end 3, the other end of an interface J2, the other end of a resistor R12 is connected with the negative electrode of an LED9, the positive electrode of an LED9 and the positive electrode of an exclusion RN 72 TP 9, the LED9 of an LED9 and the other end of the LED9 is connected with the ground; the counter U2 adopts a CD4024 chip, and the NAND gate U3 adopts a TTL7430 chip.