CN203350915U

CN203350915U - Gate ball ten-second timer

Info

Publication number: CN203350915U
Application number: CN 201320466696
Authority: CN
Inventors: 胡健; 王松; 王莉; 刘琳; 陶庆玲; 佘富豪; 张尉锋; 高庆敏
Original assignee: Shangqiu Institute of Technology
Current assignee: Shangqiu Institute of Technology
Priority date: 2013-08-01
Filing date: 2013-08-01
Publication date: 2013-12-18
Anticipated expiration: 2023-08-01

Abstract

The utility model belongs to a ten-second timer for timing of a gate ball referee. Ten-second timing is finished by adopting a digital integration circuit, a prompt buzzing sound with a certain loudness is emitted respectively at the starting time point and the ending time point in the timing process, the timing process state is displayed by adopting a color-changing light emitting diode, and when the timing function is finished, a prompt notice of timing information is given to a timed athlete, so the timing operation and judge action of the referee are accepted by the athlete and the public.

Description

Ten seconds timers of croquet

Technical field

The utility model relates to a kind of ten seconds timers of croquet that are applied to judge's timing of croquet motion, timing time is 0-10 second, send the prompting buzz of certain loudness at two time points that start timing and timing time end in 10 seconds, and employing color-changing light-emitting diode is according to the different time points of timing process, change glow color, carry out the state indication.

Background technology

Croquet is the elderly's sports, and a rule wherein is: the limiting time of every sportsman's shot process is 10 seconds.The operation of motion mat chairman, require 10 seconds timers to send prompt tone at two time points that start timing and timing in 10 seconds end, and the volume of prompt tone will have certain intensity, allow the team member that the referee is timed hear at one's side.At present, timing in the 10 seconds operation of croquet motion, do not have special-purpose timing tool.Maximum common machinery or electronic stopclocks that remain used in the timing operation, because stopwatch only provides timing, do not start the prompt tone that timing and timing finish, do not possess disclosed information notification prompting, and the operation of timing is referee's personal behavior with completing, lack sportsman's approval and public letter, easily produce dispute and disagreement.The croquet timer of some producer's development and production, design adopts monostable integration timing circuit, this timer is difficult to fully up to expectations at aspects such as accuracy of timekeeping, timing Repeat accuracy, homogeneity of product, do not have and produce the function that starts timing and timing end prompt tone simultaneously.The utility model accuracy of timekeeping is higher, timing is reproducible, homogeneity of product is very high, increased simultaneously start prompting buzz that timing and timing finish and at this two time points the function with different glow color indications, can meet prescribe a time limit in the 10 seconds clocking requirement of sports rule of croquet comprehensively.

Summary of the invention

Aim to provide ten seconds timers of a kind of croquet in the present invention, improve the precision of croquet motion judge timing.The present invention and existing timer product difference are: have for the prompting buzz that starts timing and timing end and adopt the color-changing light-emitting diode to send the technical scheme of two kinds of different colours light indications at these two time point places.Start two time points that timing and timing finish respectively send into the time prompting buzz of a second, the color-changing light-emitting diode changes the glow color indication according to the different time points of timing process, it is green starting timing, and timing completes as redness, is applied to judge's timing of croquet competition field rule.

The utility model is comprised of following part: this timer forms ten seconds timing circuits by digital integrated circuit CD4017; CD4011 forms controlled audio frequency oscillator circuit; Dichromatic LED VD3, VD4, transistor VT1, VT2 resistance R 7, R8 R9, R10 form timing process status display circuit.This timer is 100 * 60 * 30mm plastic casing; Both sides, plastic casing upper end are provided with link, in order to connect to be linked with for the referee, are worn on front.

Described technical scheme is as follows:

In order better to realize clocking capability purpose of the present invention, can also comprise following technical scheme:

The described second signal oscillator formed by CMOS integrated circuit Sheffer stroke gate.

The calibration circuit of described second signal oscillator oscillation frequency.

The described decade counter formed by CMOS integrated circuit pulsqe distributor.

The described decade counter start reset circuit for being formed by CMOS integrated circuit pulsqe distributor.

In order better to realize prompting buzz purpose of the present invention, can also comprise following technical scheme:

The described controlled audio frequency oscillator formed by CMOS integrated circuit Sheffer stroke gate.

Described formed by switching diode or gate logic.

The Circuit tuning of the described controlled audio frequency oscillator oscillation frequency for being formed by CMOS integrated circuit Sheffer stroke gate.

The described complementary amplifying circuit formed by difference conduction polar transistor.

In order better to realize variable color purpose of the present invention, can also comprise following technical scheme:

Described by CMOS integrated circuit pulsqe distributor output terminal driving circuit, except VD3, VD4 and loudspeaker, after all the other electronic devices and components all are welded on printed circuit board (PCB) in dress and timer plastic casing.

Described light emitting diode green VD3, red VD4 are arranged on respectively the front of timer plastic casing, in order to check the timing situation during match.

Principle of work of the present invention: two

Sheffer stroke gates

1,2 by CMOS integrated circuit two input end four Sheffer stroke gate CD4011 form a second signal oscillator, by adjust timing resistor R and a timing capacitor C calibration second signal, vibrate the square wave second signal that produce export to the clock pulse input terminal of CMOS integrated circuit pulsqe distributor CD4017 in signal oscillator second.CD4017 carries out decimal system counting to the second signal pulse of input, and successively at these 10 output terminal output high level of Q0-Q9.Other two Sheffer stroke gates 3,4 of CD4011 form controlled sound signal oscillator, in the sound signal oscillator by adjusting timing resistor R and timing capacitor C to select suitable audio tones, two of Sheffer stroke gate 3 input ends wherein, one is connected on the oscillator loop, a control end of drawing as controlled oscillator, by the counting level of the output terminal of CD4017 output via or gate logic controlled, become controlled oscillator.At this device, CD4017 has two to the output high level of signal-count second, and respectively: the beginning sprocket pulse that QO provides, the timing that ten seconds timing times that Q9 provides arrive finishes pulse.These two pulse signals by or gate logic trigger controlled sound signal oscillator, the sound signal of controlled sound signal oscillator output is through amplifying the output of rear drive loudspeaker.In order to guarantee that the each start of CMOS integrated circuit pulsqe distributor CD4017 can both accurate counting, form reset circuit by capacitor C and resistance R, provide a high level pulse at booting moment to CMOS integrated circuit pulsqe distributor CD4017 reset terminal, the inner forced resetting of CMOS integrated circuit pulsqe distributor CD4017 is made zero, after the capacitor C charging finishes, CMOS integrated circuit pulsqe distributor CD4017 reset terminal becomes low level, and end resets.CMOS integrated circuit pulsqe distributor CD4017 clock allows end EN high level to forbid counting, low level allows counting, it and reset terminal are linked together, in the start reseting procedure, clock allows end EN in high level, CMOS integrated circuit pulsqe distributor CD4017 forbids counting, end resets, clock allows end EN and reset terminal RST to enter low level simultaneously, CMOS integrated circuit pulsqe distributor CD4017 enters count status, makes the work of CMOS integrated circuit pulsqe distributor CD4017 counting more reliable.In order to make the user can grasp timing process situation, this device is provided with the color-changing light-emitting diode display circuit, starting timing sends when pointing out buzz, green LED is lighted a second, ten seconds timing times are to sending when finishing to carry buzz, and green LED is lighted a second.

The accompanying drawing explanation

Fig. 1 is the utility model block diagram.

Fig. 2 is the circuitry schematic diagram.

In Fig. 2,

segment

1,2,3,4,5,6 is divided for each functional circuit unit.

Embodiment

In order to make the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the present invention is described in further detail.

Be illustrated in figure 1 the utility model block diagram, showed workflow of the present utility model.

Be illustrated in figure 2 the circuitry schematic diagram.

As piece in Fig. 21 is depicted as a second signal oscillator.By A, the B input end of two

Sheffer stroke gates

1,2 and be connected into phase inverter, form multivibrator by timing capacitor C1 and timing resistor R2, selection and adjustment by timing capacitor C1 and timing resistor R2 numerical value, obtain needed oscillation frequency.

As piece in Fig. 22 is depicted as the decade counter that CMOS integrated circuit pulsqe distributor CD4017 forms.The main pin function of this integrated circuit is: RST reset terminal, EN clock allow end, CP clock pulse input terminal, Q0-Q9 count pulse output terminal.Reset circuit is comprised of reset capacitance C2 and R3, tri-elements of R4, booting moment, reset capacitance charging both end voltage equals zero, obtain high level (equaling vdd voltage) at resistance R 4 two ends, the RST reset terminal linked together and EN clock allow end be forced to reset under the effect of high level zero clearing and forbid counting, and after reset capacitance C2 charging end, reset capacitance C2 both end voltage equals supply voltage, the RST reset terminal linked together and EN clock allow the end low level, and end resets.The resistance R 3 of reset capacitance C2 two ends parallel connection has two effects, and the first and resistance R 4 form the series winding bleeder circuit after the end that resets, and guarantee that the integrated circuit reset terminal is in low level state; Its two be after shutdown for reset capacitance C2 provides a discharge loop, the electric charge filled above reset capacitance C2 is released in time, to guarantee at any time once in start, accurately to enter reset mode upper.The CP clock pulse input terminal of the square-wave pulse input CMOS integrated circuit pulsqe distributor CD4017 that second, signal oscillator produced carries out decimal system counting, count results is exported at Q0-Q9 count pulse output terminal, each output terminal is according to signal pulse Sequential output second, the utility model gets Q0 and two output terminals of Q9 start the output terminal finished with timing as timing, just in time meets the 0-10 clocking requirement of second.

As piece in Fig. 23 be depicted as by VD1, two diodes of VD2, formed or gate logic.Due to the unilateal conduction character of diode, any diode has obtained the input signal of high level, or gate logic all can have high level output, for other diode circuits, owing to being Opposite direction connection, the diode cut-off, the high level of output terminal can not impact.The utility model input end is taken from Q0 and two output terminals of Q9 of IC2, can obtain timing at output terminal and start to finish two high level signals with timing, and former and later two high level signals that synthesize 0-10 interval second are exported to rear class, as trigger pip.

Be illustrated in figure 4 the color-changing light-emitting display circuit.Color-changing light-emitting diode green VD3, red VD4 are driven by VT1, VT2 respectively.The current-limiting resistance that wherein R8, R10 are light emitting diode, VT1 is driven and sent green when timing starts by Q0; VT2 is driven and sent redness when timing finishes by Q9.Fluorescent lifetime is determined by pulse width, is all one second.

As being depicted as by two Sheffer stroke gates 3,4, piece in Fig. 25 forms controlled sound signal oscillator.Wherein by Sheffer stroke gate form phase inverter, to form the multivibrator principle of work by timing capacitor C3 and timing resistor R6 identical with second signal oscillator.By selection and adjustment to timing capacitor C3 and timing resistor R6 numerical value, obtaining needed oscillation frequency is audio tones, and the utility model is got the 800HZ left and right, and tone is comparatively soft.This unit focus on controllable oscillatory, the path of realizing is: according to the principle of work of Sheffer stroke gate, two input ends of Sheffer stroke gate 3 separately, no longer link together and form the phase inverter use, but an input end is connected on multivibrator circuit, another input end is drawn with prime or gate logic output terminal and is connected.The input end that this is connected with prime or gate logic output terminal and another input end that is connected on multivibrator circuit have formed the relation of logical and, and become the control end of this sound signal oscillator.When this input end when being low level, Sheffer stroke gate 3,4 failure of oscillations absence of audio signals outputs; When this input end is high level, Sheffer stroke gate 3,4 starting oscillations have sound signal output.Or the gate logic output terminal is exactly to be spaced apart the timing of 10 seconds to start to finish the synthetic of these two high level signals with timing to the control signal of Sheffer stroke gate 3 input ends, realized the work of controlled sound signal oscillator.

As piece in Fig. 26 is depicted as audio signal amplifier.In order to make loudspeaker obtain enough driving powers, by conduction polarity, two different transistor VT3, VT4 form the complementary push-pull amplifier.Due to circuit working in pulse square wave amplify and also loudspeaker output be the buzzing prompt tone, the utility model has been simplified the circuit such as direct current biasing, makes circuit more succinct reliably.Loudspeaker is arranged in the box in the front of timer plastic casing, and front panel is provided with the circular hole of 5 decent 2mm, so that the outside propagation of sound, its spread scope is decent 50m.

Claims

1. ten seconds timers of a novel croquet, is characterized in that, this timer forms ten seconds timing circuits by digital integrated circuit CD4017; CD4011 forms controlled audio frequency oscillator circuit; Dichromatic LED VD3, VD4, transistor VT1, VT2 resistance R 7, R8 R9, R10 form timing process status display circuit; This timer is 100 * 60 * 30mm plastic casing; Both sides, plastic casing upper end are provided with link, in order to connect to be linked with for the referee, are worn on front; Diode green VD3, red VD4 are arranged on respectively the front of timer plastic casing, in order to check the timing situation during match; Loudspeaker is arranged in the box in the front of timer plastic casing, and front panel is provided with the circular hole of 5 diameter 2mm, so that the outside propagation of sound; After all the other electronic devices and components all are welded on printed circuit board (PCB) in dress and timer plastic casing.