CN215728787U - Pulse generator - Google Patents
Pulse generator Download PDFInfo
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- CN215728787U CN215728787U CN202122296565.7U CN202122296565U CN215728787U CN 215728787 U CN215728787 U CN 215728787U CN 202122296565 U CN202122296565 U CN 202122296565U CN 215728787 U CN215728787 U CN 215728787U
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Abstract
The utility model discloses a pulse generator, comprising: a power divider for dividing the applied trigger pulse into two portions for output; a positive pulse generator for generating a positive pulse from a portion of the trigger pulse output from the power divider; a delay circuit for delaying another part of the trigger pulse output from the power divider by a set time; a negative pulse generator for generating a negative pulse from the trigger pulse delayed by the delay circuit; and the common-mode power combiner is used for combining the positive pulse generated by the positive pulse generator and the negative pulse generated by the negative pulse generator. Compared with the prior art, the utility model does not need to use a differential synthesizer, and can prevent the amplitude and waveform distortion caused by the differential synthesizer from being reduced; meanwhile, the same-phase power synthesizer used in the utility model is cheaper than a differential synthesizer, so that the cost can be reduced.
Description
Technical Field
The utility model relates to the technical field of electronics, in particular to a pulse generator.
Background
The pulse generator is a key component of the range radar. In prior art generation circuits, a single pulse generator generates a positive pulse when a trigger pulse is applied to the input. The trigger pulse is extended for a certain time in an extension circuit and then applied to a single pulse generator to generate another positive pulse. The two positive pulses are applied to a differential combiner which inverts one of the pulses and combines the two pulses to produce a monocycle from the output.
However, in conventional monocycle generators, the original pulse is attenuated by the differential synthesizer, which reduces the amplitude of the output monocycle and distorts the waveform.
Disclosure of Invention
The present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a pulse generator capable of generating a monocycle pulse having a large amplitude and a small waveform distortion.
In order to solve the technical problems, the utility model adopts the technical scheme that:
a pulse generator, comprising:
a power divider for dividing the applied trigger pulse into two portions for output;
a positive pulse generator for generating a positive pulse from a portion of the trigger pulse output from the power divider;
a delay circuit for delaying another part of the trigger pulse output from the power divider by a set time;
a negative pulse generator for generating a negative pulse from the trigger pulse delayed by the delay circuit;
and the common-mode power combiner is used for combining the positive pulse generated by the positive pulse generator and the negative pulse generated by the negative pulse generator.
Compared with the prior art, the utility model has the beneficial effects that:
1. the amplitude and waveform distortion caused by the differential synthesizer can be prevented from being reduced without using the differential synthesizer.
2. The same-phase power synthesizer used in the application is cheaper than a differential synthesizer, and the cost can be reduced.
Drawings
Fig. 1 is a circuit diagram of a pulse generator of the present invention.
Detailed Description
The monocycle generator of the present invention, as shown in fig. 1, includes a power divider 13, a delay circuit 15, a positive pulse generator 17, a negative pulse generator 19 and a common mode power combiner 21.
The power divider 13 is used to divide the trigger pulse applied to the input terminal 9 into two parts, one part being output to the positive pulse generator 17 and one part being output to the negative pulse generator 19.
When a trigger pulse is input from the power divider 13, the positive pulse generator 17 generates a positive pulse.
The delay circuit 15 delays the trigger pulse output from the power divider 13 by a predetermined time and outputs the delayed trigger pulse to the negative pulse generator 19. The delay time is the width of one negative pulse.
The common mode power combiner 21 is connected to the positive pulse generator 17 and the negative pulse generator 19, and is used for combining the positive pulse generated by the positive pulse generator 17 and the negative pulse generated by the negative pulse generator 19.
When a trigger pulse is input from the power divider 13, the positive pulse generator 17 generates a positive pulse. The delay circuit 15 delays the trigger pulse output from the power divider 13 by a certain time. When the delayed trigger pulse is inputted, the negative pulse generator 19 generates a negative pulse. The common mode power combiner 21 combines the positive and negative pulses.
The power divider 13 is composed of a first transmission line transformer 23 and a first resistor 25, and the first resistor 25 is connected to both ends of the transmission line transformer 23.
The positive pulse generator 17 includes a first capacitor 27, a first diode 29, a second resistor 31, a third resistor 33, a fourth resistor 35, a first three-terminal transistor 37, and a second capacitor 39. The first capacitor 27 and the first diode 29 are connected in sequence to the base of the first three-terminal transistor 37, the third resistor 33 is connected to the emitter of the first three-terminal transistor 37, and the fourth resistor 35 and the second capacitor 39 are connected to the collector of the first three-terminal transistor 37.
The delay circuit 15 is composed of a delay line 41 and a capacitor 43.
The negative pulse generator 19 includes a fourth capacitor 45, a fifth capacitor 47, a second diode 49, a fifth resistor 51, a sixth resistor 53, a seventh fifth resistor 55, and a second three-terminal transistor 57. The fourth capacitor 45, the second diode 49 and the fifth resistor 51 are sequentially connected to the base of the second three-terminal transistor 57, and the seventh resistor 55 and the fifth capacitor 47 are connected to the collector of the second three-terminal transistor 57; a sixth resistor 53 is connected to the output of the fifth capacitor 47 and to ground.
The common mode power combiner 21 is composed of an eighth resistor 59 and a second transmission line transformer 61.
When the input terminal 9 inputs a trigger pulse, the trigger pulse is divided into two parts by the power divider 13 composed of the first transmission line transformer 23 and the first resistor 25, and one of the two parts is input to the first three-terminal transistor 37 through the first capacitor 27 and the first diode 29. A high voltage is applied to the first three-terminal transistor 37 through the fourth resistor 35, and therefore, when three pulses are applied to the base of the first three-terminal transistor 37, the first three-terminal transistor 37 operates in an avalanche mode and generates a positive pulse in the third resistor 33.
When a trigger pulse is applied to the base, transistor 37 operates in avalanche mode and produces a positive pulse in resistor 33. The trigger pulse distributed by the power distributor 13 is delayed by a predetermined time by the delay circuit 15 and is input to the second three-terminal transistor 57 through the fourth capacitor 45 and the second diode 49. When the trigger pulse is applied to the base of the second three-terminal transistor 57, the second three-terminal transistor 57 operates in an avalanche mode of the collector output, and generates a negative pulse in the sixth resistor 53. Thus generating a monocycle at the output 11. Therefore, the present application can prevent the amplitude and waveform distortion caused by the differential synthesizer from being reduced without using the differential synthesizer. In addition, since the in-phase power combiner 21 is cheaper than the differential combiner, the cost can be reduced by the present application.
Claims (6)
1. A pulse generator, comprising:
a power divider for dividing the applied trigger pulse into two portions for output;
a positive pulse generator for generating a positive pulse from a portion of the trigger pulse output from the power divider;
a delay circuit for delaying another part of the trigger pulse output from the power divider by a set time;
a negative pulse generator for generating a negative pulse from the trigger pulse delayed by the delay circuit;
and the common-mode power combiner is used for combining the positive pulse generated by the positive pulse generator and the negative pulse generated by the negative pulse generator into a monocycle.
2. A pulse generator as defined in claim 1, wherein the power divider comprises a transmission line transformer and a first resistor connected across the transmission line transformer.
3. The pulse generator of claim 1, wherein the positive pulse generator comprises a first capacitor, a first diode, a second resistor, a third resistor, a fourth resistor, a first three-terminal transistor, and a second capacitor; the first capacitor and the first diode are sequentially connected to the base of the first three-terminal transistor, the third resistor is connected to the emitter of the first three-terminal transistor, and the fourth resistor and the second capacitor are connected to the collector of the first three-terminal transistor.
4. The pulse generator of claim 1, wherein the delay circuit comprises a delay line and a third capacitor.
5. The pulse generator of claim 1, wherein the negative pulse generator comprises a fourth capacitor, a fifth capacitor, a second diode, a fifth resistor, a sixth resistor, a seventh resistor, and a second three-terminal transistor; the fourth capacitor, the second diode and the fifth resistor are sequentially connected to the base of the second three-terminal transistor, and the seventh resistor and the fifth capacitor are connected to the collector of the second three-terminal transistor; and the sixth resistor is connected to the output end of the fifth capacitor and is grounded.
6. A pulse generator as defined in claim 1, wherein the common mode power combiner comprises an eighth resistor and a second transmission line transformer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122296565.7U CN215728787U (en) | 2021-09-23 | 2021-09-23 | Pulse generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122296565.7U CN215728787U (en) | 2021-09-23 | 2021-09-23 | Pulse generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215728787U true CN215728787U (en) | 2022-02-01 |
Family
ID=80023565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122296565.7U Active CN215728787U (en) | 2021-09-23 | 2021-09-23 | Pulse generator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215728787U (en) |
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2021
- 2021-09-23 CN CN202122296565.7U patent/CN215728787U/en active Active
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