CN215646741U

CN215646741U - Variable intermediate frequency group delay equalizer

Info

Publication number: CN215646741U
Application number: CN202122101113.9U
Authority: CN
Inventors: 程建国
Original assignee: Individual
Current assignee: Tianshui Kaihua Electronic Weighing Apparatus Co ltd
Priority date: 2021-09-01
Filing date: 2021-09-01
Publication date: 2022-01-25
Anticipated expiration: 2031-09-01

Abstract

The utility model provides a variable intermediate frequency group delay equalizer, which comprises a first active matching circuit used for input impedance matching, a second active matching circuit used for output impedance matching and a group delay equalizing circuit arranged between the first active matching circuit and the second active matching circuit; the group delay equalizing circuit comprises a resistor R, a transmission transformer B, an inductor L and a capacitor C; the resistor R is connected with the transmission transformer B in parallel, and the inductor L is connected with the capacitor C in series and then connected with the midpoint of the transmission transformer B; the inductor L is an adjustable inductor, and the capacitor C is an adjustable capacitor. The utility model ensures that the variable time delay equalizing circuit has good input and output matching impedance, and the equalizing adjustment is convenient and reliable.

Description

Variable intermediate frequency group delay equalizer

Technical Field

The utility model relates to the field of microwave communication, in particular to a variable intermediate frequency group delay equalizer applied to microwave communication.

Background

In large capacity microwave systems, the system is required to have a very wide frequency band, e.g. f₀±15MH_zThe frequency is 70 ± 15MHz, and the system is required to have flat group delay characteristics within 70 ± 12MHz to obtain good broadband phase frequency characteristics, improve data error performance, and reduce noise output. In general, the components causing distortion of the in-band delay in microwave systems, mainly intermediate frequency and radio frequency band pass filters. Fig. 1 shows the amplitude-frequency characteristic k (f) and the group delay characteristic τ (f) of a conventional if band-pass filter. In the diagram, Δ τ in the 70 + -12 MHz frequency range₁And Δ τ₂Up to the order of 10ns or more, whereas microwave systems require Δ τ₁And Δ τ₂Within 1 ns. Therefore, needs to be equalized.

The currently common equalization technique is to use a fixed network with all-pass characteristic as a group delay equalizer, and to improve the total group delay characteristic after connecting the equalizer in series with a band-pass filter. As illustrated in fig. 2, the requirement of group delay characteristics can be basically solved by using two stages of passive fixed equalization. However, in an actual microwave system, due to the inconsistency of mass production, different group delay balances are required, and a plurality of various passive fixed group delay equalizer boxes are often manufactured in advance. For example, the equalization unit has a positive slope type, a negative slope type, a parabola type, and the like, and various equalization amounts, and the equalization unit is combined to meet the requirements of different equalization characteristics. It is inconvenient and difficult to achieve the requirement of accurate equalization because a plurality of equalizing units need to be prepared in advance.

In summary, the prior art delay equalizer has disadvantages and drawbacks in practical use, and therefore needs to be improved.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks, an object of the present invention is to provide a continuous variable if group delay equalizer, which has good input and output matching impedances, so that the equalization adjustment of the circuit does not affect the matching connection of the circuit, and is more convenient and reliable.

The technical scheme for realizing the technical purpose of the utility model is as follows: a variable intermediate frequency group delay equalizer comprises a first active matching circuit used for input impedance matching and a second active matching circuit used for output impedance matching, and further comprises a group delay equalizing circuit arranged between the first active matching circuit and the second active matching circuit; the group delay equalizing circuit comprises a resistor R, a transmission transformer B, an inductor L and a capacitor C; the resistor R is connected with the transmission transformer B in parallel, and the inductor L is connected with the capacitor C in series and then connected with the midpoint of the transmission transformer B; the inductor L is an adjustable inductor, and the capacitor C is an adjustable capacitor.

Further, in the above variable if group delay equalizer: the transmission transformer B is a broadband transmission transformer.

Further, in the above variable if group delay equalizer: the first active matching circuit (10) comprises a triode Q1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, a resistor R3 and a resistor R4; an intermediate frequency input signal is input through a capacitor C1 and then connected with a parallel circuit consisting of a resistor R1 and a variable capacitor C2, and then connected with an emitter of an NPN type triode Q1, a 19V power supply is connected with an emitter of a triode Q1 through a resistor R2, a base electrode of the triode Q1 is connected with a 19V power supply through a resistor R3, a collector electrode of the triode Q1 is grounded through a variable resistor R4 and a capacitor C5 which are connected in series, a collector electrode of the triode Q1 is grounded through a variable capacitor C6, and a collector electrode of a triode Q1 is connected with an input end of the group delay equalizing circuit; the two ends of the resistor R3 are grounded through a capacitor C3 and a capacitor C4 respectively.

Further, in the above variable if group delay equalizer: the second active matching circuit (20) comprises a triode Q2, an inductor B2, an inductor B3, a capacitor C9, a capacitor C10, a resistor R6, a resistor R7 and a resistor R8;

the output end of the group delay equalizing circuit is connected with the emitter of an NPN type triode Q2, the base of the triode Q2 is connected with a-19V working power supply through a resistor R8 and a resistor R3, and is grounded through a parallel circuit formed by the resistor R5 and a capacitor C9, the collector of the triode Q2 is grounded through an inductor B2, the middle tap of the inductor B2 is connected with an intermediate frequency output after being connected in series through a resistor R6 and a capacitor C10, and the common end connected with the resistor R6 and the capacitor C10 is connected with the ground in series through an inductor B3 and a resistor R7.

The utility model ensures that the variable time delay equalizing circuit has good input and output matching impedance, and the equalizing adjustment is convenient and reliable.

The utility model will be explained in more detail below with reference to the drawings and examples.

Drawings

Fig. 1 is a graph of amplitude-frequency characteristics and group delay characteristics of a prior art if bandpass filter.

Fig. 2 is a diagram of the delay characteristics of a prior art delay equalizer using a two-stage all-pass network.

Fig. 3 is a block diagram of the group delay equalizer of the present invention.

Fig. 4 is a circuit diagram of an embodiment of the group delay equalizer of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.

Fig. 3 is a basic structure diagram of the variable if group delay equalizer of the present invention, which includes a group delay equalizing circuit 30 composed of a resistor R, a transmission transformer B, an inductor L, and a capacitor C, a first active matching circuit 10, and a second active matching circuit 20, wherein the group delay equalizing circuit 30 has the following structure: the resistor R is connected with the transmission transformer B in parallel, and the inductor L is connected with the capacitor C in series and then connected with the midpoint of the transmission transformer B. The first active matching circuit 10 is connected to an input terminal of the group delay equalizing circuit 30 for input impedance matching, and the second active matching circuit 20 is connected to an output terminal of the group delay equalizing circuit 30 for output impedance matching. Preferably, the transmission transformer B in the group delay equalizing circuit 30 is a broadband transmission transformer, and both the first active matching circuit 10 and the second active matching circuit 20 can perform matching adjustment. In the circuit structure, the f0 position and the curve shape of the group delay characteristic of the group delay equalizer can be changed only by adjusting the inductance L and/or the capacitance C. Therefore, the intermediate frequency group delay equalizer has good input and output impedance matching, so that the intermediate frequency group delay equalizer has a good equalizing effect, and the equalizing adjustment is simple and reliable.

Fig. 4 is a circuit diagram of an embodiment 1 of the present invention, in which capacitors except capacitors C2 and C6 are variable capacitors, and capacitor C consisting of capacitor C7 and variable capacitor C8 can be 0.033 μ F capacitors, and they can be regarded as short circuits for intermediate frequency (70 ± 12MHz) signals, and they function as coupling capacitors (loss ≈ 0) or bypass capacitors (grounding intermediate frequency signals). In this embodiment, the inductor L1, the capacitor C, the transmission transformer B1, and the 100 Ω resistor R10 form a bridge type group delay equalizer circuit, which is properly designed and adjusted to obtain a group delay characteristic opposite to that of the filter.

According to fig. 4, the impedance of the input terminal can be adjusted by the input matching circuit, whereby a suitable input impedance matching can be obtained. The two 2G711B triodes form an intermediate frequency broadband common base amplification circuit, and the two circuits have current amplification function and broadband (10 MHz-130 MHz) current amplification function. To compensate for losses in the matching circuit. The variable resistor R4 is a 2.2K potentiometer and the capacitor C6 is a 2.2/10 half-variable capacitor for adjusting the matching of the transistor Q1(2G711B amplifier tube) and the delay circuit. The transistor Q2 (circuit right side 2G711B) is amplified and then sent to the transmission transformer B2, and two 75 Ω resistors R6 and R7 and a 0.1 μ H inductor B3 form an amplification output circuit and an output matching circuit, so that output impedance matching can be adjusted. According to analysis, the phase-frequency characteristics of the circuit are as follows: phi (omega) 2tg^-1x, the delay characteristic is:

the time delay characteristic is parabolic, wherein: and omega is 2 pi f, x is the series reactance value of L1 and C2, and the time delay characteristic can be continuously adjusted by adjusting semi-variable capacitors C2 and L1.

In the circuit of the embodiment, a two-stage amplification circuit adopts a-19V direct current power supply for power supply, and a two-stage amplification stage adopts a series connection type bias power supply for power saving. The insertion loss of the whole component is adjusted within 0 +/-1 dB, and the fluctuation of a pass band (70 +/-15 MHz) is adjusted within 0.2 dB. The input return loss and the output return loss can be adjusted to be more than 26dB (70 +/-12 MHz), the group delay adjustable range is changed from +3ns to 3ns, a parabolic curve opposite to the group delay characteristic of the filter can be formed through proper change, and therefore the total group delay characteristic requirement can be met by flexibly adjusting according to actual needs.

When the embodiment is applied to a 1920-path high-capacity digital microwave system, the balance adjustment is convenient and reliable, the speed of building and adjusting the station is greatly improved, and the effect is good. Preferably, the present invention is also applicable to other systems, such as a medium-capacity 480-path digital microwave system, a 1800-path analog microwave system, a 960-path analog microwave system, etc.

In summary, the input end of the variable delay equalizer is connected with an active matching circuit for input impedance matching, and the output end of the variable delay equalizer is connected with an active matching circuit for output impedance matching, so that the delay equalizer obtains good input and output impedance, thereby obtaining good equalization effect, and equalization adjustment is more convenient and reliable.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the utility model as defined in the appended claims.

Claims

1. A variable intermediate frequency group delay equalizer comprising a first active matching circuit (10) for input impedance matching and a second active matching circuit (20) for output impedance matching, characterized by: the circuit also comprises a group delay equalization circuit (30) arranged between the first active matching circuit (10) and the second active matching circuit (20); the group delay equalizing circuit (30) comprises a resistor R, a transmission transformer B, an inductor L and a capacitor C; the resistor R is connected with the transmission transformer B in parallel, and the inductor L is connected with the capacitor C in series and then connected with the midpoint of the transmission transformer B; the inductor L is an adjustable inductor, and the capacitor C is an adjustable capacitor.

2. The variable intermediate frequency group delay equalizer of claim 1, wherein: the transmission transformer B is a broadband transmission transformer.

3. The variable intermediate frequency group delay equalizer of claim 2, wherein: the first active matching circuit (10) comprises a triode Q1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, a resistor R3 and a resistor R4; an intermediate frequency input signal is input through a capacitor C1 and then connected with a parallel circuit consisting of a resistor R1 and a variable capacitor C2, and then connected with an emitter of an NPN type triode Q1, a 19V power supply is connected with an emitter of a triode Q1 through a resistor R2, a base electrode of the triode Q1 is connected with a 19V power supply through a resistor R3, a collector electrode of the triode Q1 is grounded through a variable resistor R4 and a capacitor C5 which are connected in series, a collector electrode of the triode Q1 is grounded through a variable capacitor C6, and a collector electrode of a triode Q1 is connected with an input end of a group delay equalizing circuit (30); the two ends of the resistor R3 are grounded through a capacitor C3 and a capacitor C4 respectively.

4. The variable intermediate frequency group delay equalizer of claim 3, wherein: the second active matching circuit (20) comprises a triode Q2, an inductor B2, an inductor B3, a capacitor C9, a capacitor C10, a resistor R6, a resistor R7 and a resistor R8;

the output end of the group delay equalizing circuit (30) is connected with the emitter of an NPN type triode Q2, the base of the triode Q2 is connected with a 19V working power supply through a resistor R8 and a resistor R3, the base is grounded through a parallel circuit formed by the resistor R5 and a capacitor C9, the collector of the triode Q2 is grounded through an inductor B2, the middle tap of the inductor B2 is connected with an intermediate frequency output after being connected in series with a resistor R6 and a capacitor C10, and the common end connected with the resistor R6 and the capacitor C10 is connected with the ground in series through an inductor B3 and a resistor R7.