CN215643445U - Display panel and display device - Google Patents
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- CN215643445U CN215643445U CN202121369268.4U CN202121369268U CN215643445U CN 215643445 U CN215643445 U CN 215643445U CN 202121369268 U CN202121369268 U CN 202121369268U CN 215643445 U CN215643445 U CN 215643445U
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Abstract
The utility model discloses a display panel and a display device, wherein the display panel comprises a substrate, the substrate comprises a display area and a mounting area, the mounting area is positioned below the display area, the display area is provided with a pixel array, the display panel also comprises a connecting plate, a grid driving chip and a source driving chip, the source driving chip is arranged on the connecting plate and receives a data driving signal, and the grid driving chip receives a time sequence control signal through the connecting plate. The utility model reduces the invalid display area of the display panel, so that the side frame of the display device using the display panel can be made narrower.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the development of liquid crystal displays towards the direction of frameless and full-screen displays, the requirements on the frame of the display are higher and higher, and the frame of the display is larger at present, so that the display effect is seriously influenced.
The display panel generally includes a substrate, and a source driver chip, a gate driver chip, and a pixel array mounted on the substrate; the source driving chip converts the received data driving signal into a gray scale voltage and outputs the gray scale voltage to the pixel array; the grid driving chip outputs grid driving signals line by line through the scanning lines to start the pixel array line by line, so that the display panel is lightened, and the display panel displays corresponding pictures.
The gate driving chips are mounted on two side edges of the display panel and electrically connected with the sub-pixels, here, a binding region required by the gate driving chips and electrically connected with the sub-pixels needs to be set, the binding region is an invalid display region, and in order not to affect the viewing effect, the binding region can be covered by a black frame. This results in a display device using the display panel having a wide side frame. Or for symmetry and beauty, the frames on the two sides of the display device are arranged to be wide so as to shield the binding area. The increase of the frame of the display device greatly affects the use of users.
SUMMERY OF THE UTILITY MODEL
The main object of the present invention is to provide a display panel, which aims to reduce the side invalid display area of the display panel.
In order to achieve the above object, the present invention provides a display panel, which includes a substrate, wherein the substrate includes a display area and a mounting area, the mounting area is located below the display area, and the display area is provided with a pixel array; the display panel further includes:
the connecting plate is electrically connected with the substrate and is used for accessing a timing sequence control signal and a data driving signal;
the source electrode driving chip is arranged on the connecting plate and used for converting the data driving signals into corresponding gray scale voltages and outputting the gray scale voltages to the pixel array; and
and the grid driving chip is arranged in the mounting area and electrically connected with the connecting plate, and is used for receiving the time sequence control signal and outputting a corresponding grid driving signal to the pixel array so as to drive the pixel array to work.
In an embodiment, the number of the gate driving chips is multiple, the substrate includes a bottom edge, and the gate driving chips are arranged in a row along the bottom edge.
In one embodiment, the connection plate includes:
and the source electrode driving chip is arranged on the flexible circuit board and is used for accessing the time sequence control signal and the source electrode driving chip, outputting the time sequence control signal to the grid electrode driving chip and outputting the data driving signal to the source electrode driving chip.
In one embodiment, the connection plate further comprises:
one side of the printed circuit board is connected with the flexible circuit board, one side of the printed circuit board, which is far away from the flexible circuit board, is provided with a signal input end, and the signal input end is used for accessing the sequential control signal and the data driving signal.
In an embodiment, the number of the signal input terminals is two, and the signal input terminals are respectively a first signal input terminal and a second signal input terminal, the substrate is divided into a first display area and a second display area along a horizontal direction, the gate driving signal and the data driving signal accessed by the first signal input terminal are used for driving a pixel array of the first display area, and the gate driving signal and the data driving signal accessed by the second signal input terminal are used for driving a pixel array of the second display area.
In one embodiment, the first display area and the second display area are disposed in half along a middle line of the substrate in the horizontal direction.
In an embodiment, the number of the source driver chips is two, and the two source driver chips are a first source driver chip and a second source driver chip respectively;
the first source electrode driving chip is used for converting the data driving signals into corresponding gray scale voltages and outputting the gray scale voltages to the pixel array in the first display area;
and the second source electrode driving chip is used for converting the data driving signals into corresponding gray scale voltages and outputting the gray scale voltages to the pixel array in the second display area.
The utility model also provides a display panel, which comprises a substrate, wherein the substrate comprises a display area and a mounting area, the mounting area is positioned below the display area, the display area of the substrate is divided into a first display area and a second display area along the horizontal direction, and the display area is provided with a pixel array; the display panel includes:
a first flexible circuit board; the first timing control signal and the first data driving signal are accessed;
a second flexible circuit board; the second data driving circuit is used for accessing a second time sequence control signal and a second data driving signal;
a first group of gate driving chips; the first group of gate driving chips comprise a plurality of first gate driving chips, the plurality of first gate driving chips are arranged in the mounting region below the first display region and are arranged in a row along the bottom edge direction of the substrate, and the plurality of first gate driving chips are used for receiving the first timing control signal and outputting a corresponding gate driving signal to the pixel array in the first display region;
the second group of gate driving chips comprise a plurality of second gate driving chips, the second gate driving chips are arranged in the mounting area below the second display area and are arranged in a row along the bottom edge direction of the substrate, and the second gate driving chips are used for receiving the second time sequence control signal and outputting a corresponding gate driving signal to the pixel array in the second display area;
the first source electrode driving chip is arranged on the first flexible circuit board and used for converting the first data driving signal into corresponding gray scale voltage and outputting the gray scale voltage to the pixel array in the first display area;
and the first source electrode driving chip is used for converting the second data driving signal into corresponding gray scale voltage and outputting the gray scale voltage to the pixel array in the second display area.
The utility model also provides a display device, which comprises a time sequence control panel and the display panel; the time sequence control board is electrically connected with a source electrode driving chip and a grid electrode driving chip of the display panel respectively.
In one embodiment, the display panel has two side edges located at two sides of the display area in the horizontal direction, and the width of each side edge in the horizontal direction is less than or equal to 2 mm.
According to the technical scheme, the substrate is divided into the mounting area and the display area, the grid driving chip is directly packaged on the mounting area of the substrate, the connecting plate receives the time sequence control signal, and meanwhile, the connecting plate is provided with the source driving chip; the grid driving chip outputs grid driving signals to sequentially start the thin film transistors in the pixel arrays in the mounting area according to the time sequence control signals accessed by the connecting plate, and the source driving chip converts the data driving signals accessed by the connecting plate into corresponding gray scale voltages and outputs the gray scale voltages to the thin film transistors, so that the display panel displays corresponding pictures. Because the Gate driving chip is directly packaged in the mounting area of the substrate, the problem that the frame of the display is enlarged due to the fact that the invalid display area needs to be shielded by the frame because the Gate COF (Gate on film) is bound on the side surface of the substrate, namely the binding area, is avoided. The utility model can make the frame of the display panel narrower, even no frame, improve the ratio of the effective display area of the display panel and improve the display effect. In addition, in the utility model, the grid driving chip arranged on the substrate receives the time sequence control signal through the connecting plate provided with the source driving chip, namely the source driving chip and the grid driving chip use the same connecting plate to receive the driving signal, thereby effectively reducing the binding area between the connecting plate and the substrate and saving the cost for manufacturing the connecting plate.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a display panel according to another embodiment of the present invention;
fig. 3 is a schematic structural diagram of a display panel according to another embodiment of the utility model.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | |
12 | |
| 20 | |
21 | |
| 30 | |
22 | Printed |
| 40 | Source electrode driving chip | 221 | A first signal input terminal |
| 50 | Grid |
222 | Second |
| 11 | |
61 | First external flexible circuit board |
| 111 | A |
62 | Second external flexible circuit board |
| 112 | A |
70 | Time sequence control panel |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a display panel. The display panel has narrow side margins or no side frames.
Referring to fig. 1 to 3, in the first embodiment of the present invention, the mounting region 12 of the substrate 10 is located below the display region 11, and the display panel further includes:
the connection board 20 is electrically connected with the substrate 10, and the connection board 20 is used for accessing a timing control signal and a data driving signal;
the source driving chip 40 is mounted on the connection board 20, and the source driving chip 40 is configured to convert the data driving signal into a corresponding gray scale voltage and output the gray scale voltage to the pixel array; and
and the gate driving chip 30 is installed in the installation region 12 and electrically connected to the connection board 20, and the gate driving chip 30 is configured to receive the timing control signal and output a corresponding gate driving signal to the pixel array to drive the pixel array to work.
In this embodiment, the connection board 20 is electrically connected to the timing control board 70, and the source driver chip 40 is mounted on the connection board 20 by COF technology, and circuit traces are disposed to connect the timing control signal from the timing control board 70 to the gate driver chip 30. The connection board 20 may be a printed circuit board, a flexible circuit board, or the like.
The gate driving Chip 30 is mounted On the mounting region 12, and the gate driving Chip 30 may be mounted On the mounting region 12 of the substrate 10 of the display by a COG (Chip On Glass) technology. Therefore, the grid flexible circuit board 50 provided with the grid driving chip 30 is not required to be bound with the substrate 10, and the grid driving chip 30 can be electrically connected with the pixel array, so that the binding region does not exist on the side edge of the substrate 10, a black frame is not required to be arranged on the side edge of the substrate 10 to cover the binding region, and the frame of the display panel can be narrower or even be frameless; the cost of the gate flexible circuit board 50 can also be saved.
According to the technical scheme, the substrate 10 is divided into the mounting area 12 and the display area 11, the gate driving chip 30 is directly packaged on the mounting area 12 of the substrate 10, the connecting plate 20 receives a time sequence control signal, and meanwhile, the connecting plate 20 is provided with the source driving chip 40; the gate driving chip 30 outputs a gate driving signal to sequentially turn on the thin film transistors in the pixel array in the mounting region 12 according to the timing control signal accessed by the connection board 20, and the source driving chip 40 converts the data driving signal accessed by the connection board 20 into a corresponding gray scale voltage to output to the thin film transistors, so that the display panel displays a corresponding picture. Since the Gate driver chip 30 is directly packaged in the mounting region 12 of the substrate 10, the problem that the frame of the display becomes large due to the fact that the invalid display region needs to be shielded by the frame because the Gate COF is bound to the side surface of the substrate 10, that is, the binding region is generated at the side of the substrate 10 is avoided. The utility model can make the frame of the display panel narrower, even no frame, improve the ratio of the effective display area of the display panel and improve the display effect.
In addition, in the present invention, the gate driving chip 30 mounted on the substrate 10 receives the timing control signal through the connection board 20 mounted with the source driving chip 40, that is, the source driving chip 40 and the gate driving chip 30 use the same connection board 20 to receive the driving signal, which saves the cost for manufacturing the connection board 20.
Referring to fig. 1, in the second embodiment of the present invention, the number of the gate driving chips 30 is multiple, the substrate 10 includes a lower bottom edge, and the multiple gate driving chips 30 are arranged in a row along the lower bottom edge.
In this embodiment, the number of the gate driver chips 30 may be determined according to the number of rows of the pixel array and the number of output pins of each gate driver chip 30. It is sufficient that the total number of the pins of the gate driver chip 30 is greater than or equal to the number of rows of the pixel array.
The plurality of gate driving chips 30 are disposed parallel to and near the bottom side of the display panel. So set up, compare a plurality of gate drive chips 30 and be the matrix setting or be a setting, the height of the shared base plate 10 of gate drive chip 30 of this embodiment is minimum, so, can make display panel's display area more complete, and can not occupy the side of base plate 10. The side of the display panel is narrower, so that the display device using the display panel of the embodiment can be made into a narrow frame or a frame-free frame.
Referring to fig. 1, in a third embodiment of the present invention, the connection plate 20 includes:
the source driving chip 40 is mounted on the flexible circuit board 21, and is configured to access the timing control signal and the source driving chip 40, output the timing control signal to the gate driving chip 30, and output the data driving signal to the source driving chip 40.
In this embodiment, the flexible circuit board 21 is mounted with the source driver chip 40, and a circuit trace for transmitting the timing control signal is disposed on the flexible circuit board 21 in a region avoiding the source driver chip 40, so as to output the timing control signal output by the timing control board 70 to the gate driver chip 30, so that the gate driver chip 30 can operate. The source driver chip 40 is mounted on the flexible circuit board 21 by COF technology, and is not mounted in the mounting region 12 of the substrate 10, so that the space of the mounting region of the substrate 10 is saved, and the display area ratio of the display panel can be increased.
In this embodiment, the flexible circuit board 21 may be called a source flexible circuit board 21, and the gate driving chip 30 receives the timing control signal through the source flexible circuit board 21, so that it is not necessary to additionally provide a component electrically connected to the timing control board 70 for the gate driving chip 30, thereby effectively reducing the cost.
Referring to fig. 1 to 3, in a fourth embodiment of the present invention, a printed circuit board 22, one side of the printed circuit board 22 is connected to the flexible circuit board 21, and a side of the printed circuit board 22 away from the flexible circuit board 21 is provided with a signal input terminal for accessing the timing control signal and the data driving signal.
In this embodiment, the signal input terminal may be a pad or other terminal that can be electrically connected to the timing control board 70. The signal input terminal may be connected to the timing control board 70 through a flexible circuit board to receive the timing control signal and the data driving signal output by the timing control board 70, and the circuit traces on the printed circuit board 22(PCB) output the timing control signal and the data driving signal to the gate driving chip 30 and the source driving chip 40.
In the fifth embodiment of the present invention, the signal input terminal is a signal interface, and is detachably connected to the timing control board 70. Therefore, according to actual requirements, the corresponding time sequence control board 70 can be selected to be plugged with the signal input end, and the flexibility of connection between the display panel and the time sequence control board 70 is improved.
Referring to fig. 1 to 3, in a sixth embodiment of the present invention, the number of the signal input terminals is two, which are respectively a first signal input terminal 221 and a second signal input terminal 222, the substrate 10 is horizontally divided into a first display area 111 and a second display area 112, the timing control signal and the data driving signal which are accessed by the first signal input terminal 221 are used for driving a pixel array of the first display area 111, and the gate driving signal and the data driving signal which are accessed by the second signal input terminal 222 are used for driving a pixel array of the second display area 112.
In this embodiment, the number of the signal input terminals is two, and the embodiment takes the signal input terminals as pads for illustration, the two signal input terminals are electrically connected to the timing control board 70 through the first external flexible circuit board and the second external flexible circuit board, respectively, and the timing control board 70 can divide the output timing control signal and the data driving signal into two parts, and output the two parts to the first signal input terminal 221 and the second signal input terminal 222, respectively. The two signal input ends are respectively connected with the gate driving chip 30 and the source driving chip 40 of the first display area 111 and the second display area 112 correspondingly, the gate driving chip 30 and the source driving chip 40 of the first display area 111 and the second display area 112 respectively drive the pixel arrays of the first display area 111 and the second display area 112 to work, compared with the case that only one signal input end is provided, circuit wiring on the connecting plate 20 can be more uniformly dispersed, and circuit wiring on the connecting plate 20 is simplified.
Referring to fig. 2, further, the first display region 111 and the second display region 112 are disposed in half along a middle line of the substrate 10 in a horizontal direction.
In this embodiment, the central line along the horizontal direction of the substrate 10 can be understood as a central line along the horizontal direction of the display panel when the display displays a picture.
The first display area 111 and the second display area 112 are arranged in half, so that the number of the thin film transistors in the first display area 111 and the second display area 112 can be averaged, the workload of the gate driving chip 30 and the source driving chip 40 for driving the first display area 111 and the second display area 112 is equalized, the working balance of the display panel is improved, and the service life of the display panel is prolonged.
Further, the number of the source driver chips 40 is two, and the two source driver chips 40 are respectively a first source driver chip and a second source driver chip;
the first source driver chip is configured to convert the data driving signal into a corresponding grayscale voltage, and output the grayscale voltage to the pixel array in the first display region 111;
the second source driver chip is configured to convert the data driving signal into a corresponding gray scale voltage, and output the gray scale voltage to the pixel array in the second display region 112.
In this embodiment, the first source driver chip and the second source driver chip may be both mounted on one connection board 20. The number of the connecting plates 20 may also be two, and the first source driver chip and the second source driver chip are respectively mounted on the two connecting plates 20.
In this embodiment, the number of the source driver chips 40 is set to two, and the pixel arrays in the first display area 111 and the second display area 112 are respectively driven, and compared with the setting of only one source driver chip 40, the scheme of this embodiment not only can make the transmission wiring of the gray scale voltage shorter, avoid signal attenuation, but also can avoid the transmission wiring of all the gray scale voltages from being stacked together, resulting in dense wiring.
Referring to fig. 1 and 2, the present invention further provides a display panel, where the display panel includes a substrate 10, the substrate 10 includes a display area 11 and a mounting area 12, the mounting area 12 is located below the display area 11, the display area 11 of the substrate 10 is divided into a first display area 111 and a second display area 112 along a horizontal direction, and the display area 11 is provided with a pixel array; the display panel includes:
a first flexible circuit board; the first timing control signal and the first data driving signal are accessed;
a second flexible circuit board; the second data driving circuit is used for accessing a second time sequence control signal and a second data driving signal;
a first group of gate driving chips 30; the first group of gate driver chips 30 includes a plurality of first gate driver chips, and the plurality of first gate driver chips are mounted in the mounting region 12 below the first display region 111 and are arranged in a row along the bottom edge direction of the substrate 10, and the plurality of first gate driver chips are configured to receive the first timing control signal and output a corresponding gate driver signal to the pixel array in the first display region 111;
a second group of gate driving chips 30; the second group of gate driver chips 30 includes a plurality of second gate driver chips, and the plurality of second gate driver chips are mounted in the mounting region 12 below the second display region 112 and arranged in a row along the bottom edge direction of the substrate 10, and are configured to receive the second timing control signal and output a corresponding gate drive signal to the pixel array in the second display region 112;
the first source driving chip is mounted on the first flexible circuit board, and is configured to convert the first data driving signal into a corresponding grayscale voltage and output the grayscale voltage to the pixel array in the first display area 111;
and a second source driver chip mounted on the second flexible circuit board, wherein the first source driver chip is configured to convert the second data driving signal into a corresponding gray scale voltage, and output the gray scale voltage to the pixel array in the second display region 112.
In this embodiment, the first gate driving chip and the second gate driving chip may be the same type of gate driving chip or different types of gate driving chips. The first source driver chip and the second source driver chip may be the same type of source driver chip or different types of source driver chips. In this embodiment, the first gate driving chip and the second gate driving chip are the same type of gate driving chip, and the first source driving chip and the second source driving chip are the same type of source driving chip.
The first flexible circuit board is provided with a first source driver chip and a transmission trace of a first timing control signal, and is connected to the first gate driver chip in the mounting region 12.
The second flexible circuit board is provided with a second source electrode driving signal and transmission wiring of a second book order control signal, and is electrically connected with a second gate driving chip arranged in the mounting area 12.
The first flexible circuit board and the second flexible circuit board are arranged on the left and right of the substrate 10 in the horizontal direction.
In this embodiment, the first timing control signal and the first data driving signal are accessed through the first flexible circuit board, so that the first gate driving chip and the first source driving chip work to drive the first display region 111 to work; a second timing control signal and a second data driving signal are accessed through a second flexible circuit board, so that a second gate driving chip and a second source driving chip can work to drive the first display area 111 to work; in this embodiment, the first gate driver chip receives the first timing control signal through the first flexible circuit board on which the first source driver chip is mounted, and the second gate driver chip receives the second timing control signal through the second flexible circuit board on which the second source driver chip is mounted, thereby avoiding extra setting of a path for receiving the timing control signal for the first gate driver chip and the second gate driver chip, and also avoiding setting of the gate flexible circuit board and the binding region on the side surface of the substrate 10, which can make the side frame of the display panel narrower, and can also avoid increasing the cost caused by adding the flexible circuit board 21.
The utility model also provides a display device.
In a seventh embodiment of the present invention, the display device includes the display panel described above. The specific structure of the display panel refers to the above embodiments, and since the display adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
In an eighth embodiment of the present invention, the display device further includes:
the display panel is provided with an invalid display area, and the invalid display area is arranged on the display side of the display panel in a blocking mode through the blocking frame.
In this embodiment, the shielding frame may be made of metal, plastic, or other materials.
The display panel with the time sequence control board 70 electricity is connected, and the installing zone 12 region of grid display panel is invalid display area, this embodiment through shelter from the frame in the display side fender of display panel establishes invalid display area to improve display panel's display effect, and shelter from the frame and can also fix base plate 10, the liquid crystal layer among the display panel.
Referring to fig. 1, in the ninth embodiment of the present invention, the display panel has two side edges located at two sides of the display area 11 in the horizontal direction, and the width of each side edge in the horizontal direction is less than or equal to 2 mm.
In this embodiment, the two side edges of the display panel are framed by the shielding frame, and each side edge has a width in the horizontal direction smaller than or equal to 2 mm, so that the width of the shielding frame can be smaller than or equal to 2 mm, so as to realize a narrow frame of the display device, improve the screen occupation ratio, and improve the display effect.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A display panel comprises a substrate, wherein the substrate comprises a display area and a mounting area, the mounting area is positioned below the display area, and the display area is provided with a pixel array; characterized in that, the display panel still includes:
the connecting plate is electrically connected with the substrate and is used for accessing a timing sequence control signal and a data driving signal;
the source electrode driving chip is arranged on the connecting plate and used for converting the data driving signals into corresponding gray scale voltages and outputting the gray scale voltages to the pixel array; and
and the grid driving chip is arranged in the mounting area and electrically connected with the connecting plate, and is used for receiving the time sequence control signal and outputting a corresponding grid driving signal to the pixel array so as to drive the pixel array to work.
2. The display panel of claim 1, wherein the number of the gate driver chips is plural, the substrate includes a bottom edge, and the plurality of the gate driver chips are arranged in a row along the bottom edge.
3. The display panel according to claim 1, wherein the connection plate comprises:
and the source electrode driving chip is arranged on the flexible circuit board and is used for accessing the time sequence control signal and the source electrode driving chip, outputting the time sequence control signal to the grid electrode driving chip and outputting the data driving signal to the source electrode driving chip.
4. The display panel according to claim 3, wherein the connection plate further comprises:
one side of the printed circuit board is connected with the flexible circuit board, one side of the printed circuit board, which is far away from the flexible circuit board, is provided with a signal input end, and the signal input end is used for accessing the sequential control signal and the data driving signal.
5. The display panel according to claim 4, wherein the number of the signal input terminals is two, and the signal input terminals are respectively a first signal input terminal and a second signal input terminal, the substrate is divided into a first display region and a second display region along a horizontal direction, the gate driving signal and the data driving signal inputted from the first signal input terminal are used for driving a pixel array of the first display region, and the gate driving signal and the data driving signal inputted from the second signal input terminal are used for driving a pixel array of the second display region.
6. The display panel according to claim 5, wherein the first display region and the second display region are disposed in half along a center line of the substrate in a horizontal direction.
7. The display panel according to claim 5, wherein the number of the source driver chips is two, and the two source driver chips are a first source driver chip and a second source driver chip, respectively;
the first source electrode driving chip is used for converting the data driving signals into corresponding gray scale voltages and outputting the gray scale voltages to the pixel array in the first display area;
and the second source electrode driving chip is used for converting the data driving signals into corresponding gray scale voltages and outputting the gray scale voltages to the pixel array in the second display area.
8. A display panel comprises a substrate, wherein the substrate comprises a display area and a mounting area, the mounting area is positioned below the display area, the display area of the substrate is divided into a first display area and a second display area along the horizontal direction, and the display area is provided with a pixel array; characterized in that the display panel comprises:
a first flexible circuit board; the first timing control signal and the first data driving signal are accessed;
a second flexible circuit board; the second data driving circuit is used for accessing a second time sequence control signal and a second data driving signal;
a first group of gate driving chips; the first group of gate driving chips comprise a plurality of first gate driving chips, the plurality of first gate driving chips are arranged in the mounting region below the first display region and are arranged in a row along the bottom edge direction of the substrate, and the plurality of first gate driving chips are used for receiving the first timing control signal and outputting a corresponding gate driving signal to the pixel array in the first display region;
the second group of gate driving chips comprise a plurality of second gate driving chips, the second gate driving chips are arranged in the mounting area below the second display area and are arranged in a row along the bottom edge direction of the substrate, and the second gate driving chips are used for receiving the second time sequence control signal and outputting a corresponding gate driving signal to the pixel array in the second display area;
the first source electrode driving chip is arranged on the first flexible circuit board and used for converting the first data driving signal into corresponding gray scale voltage and outputting the gray scale voltage to the pixel array in the first display area;
and the first source electrode driving chip is used for converting the second data driving signal into corresponding gray scale voltage and outputting the gray scale voltage to the pixel array in the second display area.
9. A display device comprising a timing control board and the display panel according to any one of claims 1 to 8; the time sequence control board is electrically connected with a source electrode driving chip and a grid electrode driving chip of the display panel respectively.
10. The display device as claimed in claim 9, wherein the display panel has two sides located at two sides of the display area in a horizontal direction, and a width of each of the two sides in the horizontal direction is less than or equal to 2 mm.
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| CN202121369268.4U CN215643445U (en) | 2021-06-18 | 2021-06-18 | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114660860A (en) * | 2022-03-21 | 2022-06-24 | 惠科股份有限公司 | Display panel and display device |
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2021
- 2021-06-18 CN CN202121369268.4U patent/CN215643445U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114660860A (en) * | 2022-03-21 | 2022-06-24 | 惠科股份有限公司 | Display panel and display device |
| CN114660860B (en) * | 2022-03-21 | 2024-03-01 | 惠科股份有限公司 | Display panel and display device |
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